Arcade Game Manual: Defender by Williams Electronics

^lUmrn/^

16P-3001-301
OCTOBER, 1981

FOR SERVICE...

NOTE NEW TOLL-FREE

TELEPHONE NUMBERS:

800-621-1253

IN ILLINOIS CALL:

800-572-1324

THEORY OF OPERATION

LATER SYSTEM BOARDS
UPRIGHT OR TABLE GAMES

• CPU/VIDEO BOARD

• ROM BOARD

• INTERFACE BOARD

• POWER SUPPLY

(Refer to 16P-3001-300 for theory on
Defender early system boards)

ELECTRONICS, INC.

3401 N. California Ave.. Chicane. IL 606r
Cable Aaoress: WILCOIN, rHiCAGO
(312) 267-?:40

CONTENTS

IDENTIFICATION OF LATER SYSTEM BOARDS I

INTRODUCTION 1

BLOCK DIAGRAM THEORY 3

DETAILED THEORY 9

Reset Circuit 9

Watchdog Circuit 10

MPU 11

Clock Generator 12

E and Q Generator 13

Video Address Generator 14

Video Ram Control 15

Video Ram Timing 17

Video Ram Address Multiplexer 18

Video Ram 20

Video Shift Registers 22

Color Ram Circuit 23

Monitor Sync Generator 24

Blanking Circuit 25

Page O Decoder 25

CMOS RAM 26

Vertical Count Buffer 27

Count240 27

ROM Board Memory Scheme 28

Section/Page Select Decoder 29

ROM Section/Half Decoder 30

ROM Board PIA/Decoder 31

Interface Board Assembly 32

Power Supply 34

IDENTIFICATION OF LATER SYSTEM BOARDS

• CPU/VIDEO BOARD

TWO DECODER ROMS.
BATTERIES AT LOWER RIGHT,

ROM BOARD

14 AND 16-PIN ICS
MOUNTED PERPENDICULAR
TO ROM ICS.

INTERFACE BOARD

TOTAL OF SIX CHIPS
PLUS RESISTOR PACK.

SECTION 1 INTRODUCTION

The video system in this game consists of five (5) printed circuit boards, a
number of switches, and a Video Monitor. The printed circuit boards contain
most of the electronic circuitry in the game. Switches provide controlling
inputs for play of the game and the Video Monitor provides a high-resolution
color display of game action.

The basic functions of the five circuit boards are as follows. (Refer to Figure
1-1.) The Power Supply provides the necessary voltages for proper game
operation. Regulated DC outputs of +5VDC, -5VDC, +12VDC, and unregulated DC
outputs of +12VDC, -12VDC, and +27 VDC are supplied. An additional AC output
(6.3 VAC) is used to power lamps for general illumination purposes.

The CPU/Video board contains a microcomputer Central Processing Unit (CPU),
which performs the "brain" function of the system. The CPU controls the rest of
the system according to the program (list of instructions) assigned to it by a
programmer. This board also contains the Video Control circuitry and Video
Memory. The information stored in the Video Memory represents the picture the
CPU wants displayed on the Video Monitor. The Video Control circuits read the
contents of the Video Memory and convert these contents into color signals which
are then fed to the Video Monitor.

The ROM board provides ROM storage for the programs and data base which control
the operation of the Video System and supply the necessary data for game
operations. The ROM board contains: the game program, the diagnostic
(self-test) programs, permanent data used by programs, and I/O (Input/Output)
ports. An Input port is used by the system to check the status of input
switches. An Output port is used to control the on-board Self-Test indicator
LEDs, and game play-selected sounds produced by the Sound Board.

SYNC. VIDEO

MONITOR

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COIN DOOR
LOCKOUT
RELAY

SOUND
BOARD

Figure 1-1. Simplified Block Diagram

The Sound Board is able to generate various sound effects upon appropriate
command from the CPU. These commands are received via the ROM board • The audio
signals generated In response to these commands are amplified on-board, and
routed directly to the game speaker system.

The Interface Board provides Input ports to Interface the Video System to the
Player Control Panel. These Inputs allow the CPU to check the status of the
1-and 2- player start switches and player panel control switches.

SECTION 2 BLOCK DIAGRAM THEORY

The Williams Video Game System generates a color video display of 360 x 240
pixels (picture elements) on a standard Color Monitor. The Color Monitor
provides one complete (non-interlaced) scan of the screen every 16.66 mSec, for
a standard frame rate of 60 Hz. The screen may contain up to 16 different
colors at once, which are selected under program control from a total of 256
available colors. For each pixel to be displayed, a 4-bit binary code
representing one of the 16 currently-available colors is stored in a memory
called the Video RAM. These 4-bit pixel codes are continuously read out of the
Video RAM in the order they are to be displayed, and used as an address to
access 1 of 16 8-bit codes stored in a 16 byte memory called the color RAM.
Each of these 16 codes represents 1 of the 256 total available colors
(2°=256). Each 8-bit color code output from the color RAM represents a
different combination of brightness levels for the Red, Blue, and Green guns in
the monitor, producing 1 of the 256 possible color combinations.

The result is a process of two basic steps for the display of a picture:

1. Select 16 of 256 available colors for the current display by loading the
8-bit value for each color selection into 1 of the 16 color RAM
locations. The address at which each color code is stored determines
which 4-bit pixel code will cause it to be displayed.

2. Select which of the 16 currently available colors will be displayed at
each pixel location on the screen by storing the appropriate 4-bit codes
in the Video RAM.

Figure 2-1 is a block diagram showing the main features of the Williams Video
Game System hardware.

The Reset circuit produces 2 reset pulses, RESET (Reset Not) and CR (Clocked Re-
set Not), in response to either a low supply voltage (power-up or power-down) or
the reset pushbutton being depressed. These pulses assure that the MPU
(Microprocessor Unit) and critical timing components such as the Video Address
Generator are forced into a stable state during power fluctuations or testing,
and synchronized when normal operation begins. When the reset condition has
terminated, a properly functioning MPU will restart the main program, executing
system diagnostics and then the game program itself.

The Watchdog circuit is a timer which resets the MPU unless it is cleared before
it counts 8 vertical scans. The timer is cleared by writing a specific data
pattern at a specific memory address. The command to clear the Watchdog is
hiilt into the game program so that during normal game operation the Watchdog is
always cleared before it forces the MPU to reset. Should the MPU stop executing
the proper instruction sequences and fail to clear the Watchdog, the reset will
bring the game up in "Game Over".

The Clock Generator provides basic timing for the video system and co nsists of a
12 MHz oscillator and dividers to 4 MHz and 6 MHz clocks. The 12 MHz clock is
also applied to the Video RAM Timing Circuit with ot her de rived timing signals
to provide timing for access to the Video RAMs. The 4 MHz clock signal derives
the E and Q clo cks required by the MPU, clocks the Video Address Generator, and,
(with the 6 MHz clock), provides timing for the Video Shift Registers.

The E and Q Generator divides the 4 MHz clock to produce E and Q clocks. These
1 MHz clock phases provide the timing for the MPU and are also applied to the
Video RAM Timing Circuit.

The Video Address Generator provides the 14 addresses that scan the Video RAM to
produce a frame on the monitor 60 times a second. Function CR, (Clocked Reset
Not), is synchronized with the E clock and holds the counter reset when it is
low. When it goes high, the 4 MHz clock is counted to produce the addresses.
The addresses are applied through the Vertical Decoder and Video Address
Multiplexer to scan the Video RAM banks. In addition, an output is applied to
the Watchdog circuit and outputs are decoded to provide horizontal and vertical
sync for the Color Monitor and blanking in the Video D-to-A Driver. The Screen
Control reverses and inverts the screen image for player 2 in a cocktail table
game. Its signal is applied to the Vertical and Horizontal Decoders, as well as
to the Video Shift Registers.

The three RAM Banks are scanned simultaneously by the Video Address Bus, and
individually by the microprocessor.

The Video RAM Control Circuit accepts microprocessor address bits A8 through A15
to address a PROM. The PROM provides pseudo-address bits PAS through PA13, and
E and WE (Enable Not and Write Enable Not) functions. This control circuit al-
lows the microprocessor to access the Video RAM Banks individually with sequen-
tial addresses. The circuit also provides multiplexing signal MUX 1 to the
Video RAM Address Multiplexer.

The Video RAM timing circuit uses the 12 MHz, E, and Q clocks to produce Video
RAM timing. Each Video RAM bank provides 16K address locations, and is accessed
with seven address bits at a time. The memory in the RAM is configured in a
matrix with 7 of the 14 address bits latched in to select a row in the memory
matrix and then the remaining 7 address bits latched in to select a column.

Function RAS (Row Address Select Not) and CAS (Column Address Select Not) latch
the addresses into the RAM at the proper time. Functions MUX 1 from the Video
RAM control circuit and MUX pass high, and low-order video address bits for
video access, also low-order microprocessor address bits and pseudo-address bits
for microprocessor video access.

Function SRL (Shift Register Load Not) latches the data outputs from the three
RAM Banks into the Video Shift Register after each video access. Function WE is
produced at an appropriate time during microprocessor access to enable the WE
(Write Enable Not) outputs from the Video RAM control circuit.

The Video RAM Address Multiplexer uses the MUX and MUX 1 signals to place ap-
propriate addresses on the Memory Address Bus (MA0 through MA6) for latching
by the RAS and CAS signals.

MUX MUX 1 ADDRESSES RAM

LOW

LOW

UP AD, Pseud. A8-A13

Row

HIGH

LOW

UP A1-A7

Co lumn

LOW

HIGH

VA0-VA6

Row

HIGH

HIGH

VA7-VA13

Co lumn

Video RAM is accessed ly the Video Address Bus every microsecond and the data is
latched into the Video Shift Register. When the microprocessor reads from RAM,
the ¥ (Enable Not) signal from the Video RAM control circuit latches the data
from the appropriate RAM Bank into the MPU Data Bus.

The Video Shift Registers load the data from the RAM Banks into shift registers.
Functions SRL (Shift Register Load Not ) and the 4 MHz clock synchronize loading
of data into the shift register. The 6 MHz clock shifts out the 4-bit sets of
data in parallel. The data loaded into the shift registers in sets of four bits
define a pixel (picture element). Four bits from RAM Bank 1 are first presented

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to the Color RAM Address Multiplexer for a pixel. The next 6 MHz clock pulse
shifts the other 4 bits from RAM Bank 1. The next two clock pulses shift out
the hits from RAM Bank 2 and the third and fourth clock pulses, the bits from
RAM Bank 3.

Function SRL oc curs at a 1 MHz rate, loading sets of four bits into the shift
register. The 6 MHz clock shifts the sets of bits out prior to the next load.

The Color RAM Address Multiplexer passes 4-bit sets from the Video Shift Re-
gisters to the color RAM. The color RAM is a 16 x 8-bit memory addressed hf the
four hits. Data stored in the color RAM selects a color for a pixel.

The content of the color RAM is set up initially, and changed during the game by
the MPU. When the MPU writes to the color RAM, function E5 (Enable 5 Not) is
produced to select MPU address bits AO through A3 through the address multi-
plexer, and the state of MPU data bits DO through D3 are written into the de-
sired color RAM location.

The 8-bit output from the color RAM is applied to the video D-to-A driver.
Three bits define seven intensities for the Red gun, three bits for seven
intensities of the Green gun, and the remaining two hits for three intensities
of the Blue gun.

The Monitor Sync Generator decodes video outputs from the Video Address Bus to
produce horizontal and vertical sync pulses for the Color Monitor. The
Horizontal Blanking circuit also decodes Video Address Bus outputs to blank the
Color Monitor at the left and right edges of the screen. The Video RAM cor-
responding to these areas are available to the MPU for "scratchpad" RAM, and the
horizontal blanking overlaps the internal Color Monitor horizontal retrace
blanking to prevent display on the Color Monitor.

The program is able to determine the vertical position of the s can on the screen
at any time by reading the Vertical Count Buffer. Function E7*PS0 (Enable 7
Not AND Page Select Not) latch the higher order Video Address Bus bits onto
the MPU data bus for reading.

In addition, when the trace reaches the bottom of the screen, count 240 is de-
coded from the Video Address Bus and applied to an I/O (Input/Output) port on
the ROM Board to produce an MPU Interrupt. Also, Video Address Bit All is ap-
plied to the I/O port on the ROM Board to produce a 4 mSec Interrupt.

The Page decoder is provided with Page select functions from the ROM Board
and MPU Address leads and enables MPU access to the Interface Board I/O, the
Vertical Count Buffer, CMOS RAM, and the color RAM. The MPU reads and writes to
the Interface Board and CMOS RAM, reads the Vertical Count Buffer, and writes to
the color RAM.

The CMOS RAM is provided with standby battery power to maintain audit informa-
tion and game adjustments. The CMOS RAM provides 256 4- bit memory locations.
Audit information stored in the lower half of the memory, is written to as a
part of game operation, and is read from as part of the high score signature at-
tract mode. Game adjustments are stored in the upper half, and during game
operation are only read. A "memory protect" switch is held closed when the coin
door is closed to provide the Memory Protect function. This prevents writing to
the upper half of the memory when the coin door is closed. With the coin door
open, writing to the upper half is allowed so that changes to adjustments can be
made.

Pages are selected by writing to D000i5 with data to select one of up to

10 pages. Address decoding provides chip-selects for the ROMs, for the inputs,

and PI A.

The ROM Board PIA scans coin door switches and provides outputs to the Sound
Board- This PIA also provides outputs for the diagnostic LEDs. The 4 mSec and
Count 240 functions from the CPU/Video Board produce interrupts to the MPU.

The Model Interface Board accepts inputs from player panel switches through a
PIA. The Page Decoder on the CPU/Video Board provides a select-input for the
PIA.

7/8

SECTION 3 DETAILED THEORY

RESET CIRCUIT (Figure 3-1)

The Reset Circuit ensures orderly start-up and recovery of the game ty forcing a

reset In response to any of the following situations:

1. Power-up (Unit Is turned on or power failure has ended)*

2. Power-down (Unit Is turned off or power failure has occurred).

3. Reset pushbutton on CPU/Video board Is depressed.

4. Low line or power supply voltage.

A Reset causes the MPU to start at the proper memory location, disables the CMOS
RAM until the MPU Is stable, forces all PIA ports to Inputs, and synchronizes
both the Video Address Generator and the 6MHz clock with the E clock.

Two signals are u sed fo r the Reset function: RESET (Reset Not), and CR (Clocked
Reset Not). The RESET pulse^wldth (approximately 1 second ) Is determined by the
RC time constant R58/C90. CR Is clocked high after RESET goes high by the next
rising edge of the E clock, ensuring that the Video Address Generator and 6MHz
divider are synchronized with the E clock when CR goes high.

When power Is applied, C90 begins to charge through R58. At this poin t trans-
istors Q9, QIO, Qll, & Q12 are all off._Thls allows R66 to pull RESET low, as-
serting the reset^functlon- Since the CL (Clear Not) input of the data latch
which generates CR is tied to RESET, Its Q output is forced low, asserting CR.

As the charge on C90 reaches approximately 0.9 VDC, QIO is biased on through R57
and R62. This has no immediate effect, but enables Q12, which turns on later.
C90 continues to charge, and at approximately 3.0 VDC biases on Q9. As Q9
begins to conduct, it pulls its collector current thru R61 and R59, increasing
the voltage drop across these resistors. When the voltage drop across R59
Increases to 0.7 VDC, Q12 is biased on and starts to pull RESET toward +5 VDC

Since QIO was turned on earlier, there is a current path to gr ound from the
emitter of Qll, causing Qll to turn on as the voltage on RESET rises. Once Qll
turns on, its collector draws current thru R64, increasing the base current of
Q12. At this point Qll and Q12 continue to Increase each other's base drive
until both transistors are saturated, latching each other on. The purpose

(5D-I0, 50-13^0-1,60-4)

E

_^ TO CLOCK GENERATOR ft
^^ VIDEO ADDRESS GENERATOR

legend: I. V0LTACE5 IN PARENTHESES TAKEN WITH RESET SWITCH DEPRESSED.
2. COMPONENT REFERENCE DESIGNATIONS UNDER VOLTAGE READINGS
ARE PROBABLE OCFeCTS IF VOLTAGE IS AeNORMAL.

c>;

TO MPU RESET GATE
a CMOS RAM
TO PIA'S ON ROM a
NTERFACE BOARDS.

Figure 3-1. Reset Circuit

of this latch is to provide a fast transition of RESET from its asserted (low)
state to its negated (high) state.

With RESET high, CR will go high at the next rising edge of E clock, which
clocks the high present at the D input of the data latch out to the Q output

Depressing Reset switch, SWl, shorts the charge on C90 to ground. This turns
off both QIO and Q9. When QIO turns off it breaks the emitter circuit of Qll,
forces it off and breaks the Q11/Q12 latch eff ect* Since neither Qll or Q9
supplies base drive to Q12, it turns off, and RESET is pulled low by R66,
forcing Cr low. When the Reset button is released, C90 begins to charge again.
From this point, the circuit operates as described in the power-up sequence.

The power-down sequence is triggered by either the +12 VDC unregulated supply or
the +5 VDC regulated supply dropping below acceptable limits. Since the oper-
ation of the sensing circuits is similar, only the +12 VDC sensor is described.

During normal circuit operation, ZRl is biased on, but is operated close to its
turn-off point by R48. Some of the current flowing through ZRl also flows
through R49, biasing Q5 on. The collector of Q5 pulls the base of Q6 down to
0.1 VDC, forcing Q6 off.

When a power-down (or voltage drop) occurs, ZRl stops conducting as the supply
voltage drops. This removes the base bias of Q5, turning it off and allowing
R50 to bias Q6 back on. This has the same effect as pushing the RESE T but ton,
shorting the charge on C9 to ground, thereby asserting reset outputs RESET and
CR.

WATCHDOG CIRCUIT (Figure 3-2)

The Watchdog Circuit is a timer which resets the MPU if it is not cleared at
least once every 133 mSec. To clear the watchdog timer, the MPU writes a
specific data byte (38x6 °^ ^^16 ^ ^^^^ address C3FFx6 with page
selected. The game program is designed to perform this clear operation reg-
ularly, ensuring that the watchdog will not reset the MPU during normal
operation.

Noise transients and other problems will sometimes cause an MPU to jump out of
the normal program sequence. If this happens the MPU will often misinterpret

BUS BUS

FROM COCOR
RAM ADDRESS O
DECODE UWIC

FROM VIDEO ,^
ADDRESS COUNTER '^

INDICATES MPU
LOCKUP

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INDICATES FAULTY
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TO MPU
RESET GATE

NOTE:

TO DISABLE WATCHDOG RESET, CUT PAD tt GROUND INPUT TO
30 GATE. TO RESTORE CIRCUIT REMOVE GROUND AND FLOW
SOLDER ACROSS PAD.

Figure 3-2. Watchdog Circuit

10

instructions and data, causing it to become stuck in a continuous program loop
which has nothing to do with the real intent of the program. Because it is
"caught in a loop", the MPU will not cl ear the watchdog timer, and after 133
mSec, the watchdog circuit issues a WDR (Watchdog Reset Not) pulse to the MPU
reset gate* The MPU is forced to reset and begin proper program execution.

Function WDFF (Watchdog Flip-Flop) from the color RAM address decode logic is
gated with the MPU Address and Data bits as shown. The output of gate 0D goes
low when the MPU writes 38i5 or 34][6 into address C3FFi6 with Page
selected. This signal is inverted to clear the Watchdog timer 3C. The timer
counts vertical scans from the Video Address Generator Circuit parallel- load
pulse at inverter IJ pin 10. If the counter is allowed to count eight vertical
scans (133 mSec) without being cleared, its Q4 output will go high, causing WDR
to go low, to force an MPU reset.

Note that there is a special pad shown which may be broken, and one side
grounded in order to disable the Watchdog circuit. This may be necessary to
troubleshoot certain problems if the Watchdog circuit repeatedly resets the MPU,

MPU (Figure 3-3)

The MPU (Microprocessor Unit) address and data busses, and the R/w" (Read/Write
Not) control signal are buffered because the number of devices loading them
would exceed the drive capability of the MPU chip.

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FROM ESQ GENERATOR

HALT a as 'BA ARE USED ON
L ATE R MODELS WITH MA ONLY.
NMI a FIRO PROVIDED BY SOME
CONTROL PANEL INTERFACE
MODELS.

MPU DATA BUS

Figure 3-3. MPU

11

The buffers driving the address and R/W lines are uni-directional, transmitting
signals from the MPU outputs to the bus. The data bus buffers are
bi-directional, transmitting data from the bus to the MPU when R/W is high, and
from the MPU to the data bus when R/W is low. R/W is also used by memory de-
vices and other peripheral devices during data transfers.

During normal operation the buffers are continuously enabled. When a DMA
(Direct Memory Access) contro^^ler is used, (on later games), the MPU may allow
it to drive the busses and R/W control line by asserting BA. This disables the
buffers, effectively disconnecting the MPU from the address and data busses, and
R/W. The DMA device is then notified by signal BS*BA that it may use the bus-
ses.

Four inputs to the MPU (HALT, NMI, IRQ, FIRQ) are pulled high by resistors (R14,
R13, R12, & Rll) to ensure that t hey are not active unless pulled low by a
peripheral device. A low on the HALT input causes the MPU to enter a halt
state, disable its bus buffers and allow the busses to be controlled by another
device. At this point BA and BS are asserted: (BA*BS). As stated above, this
output is used on later games with a DMA controller.

NMI; FIRQ; and IRQ are interrupt inputs. Asserting any of these signals causes
the MPU to finish its current instruction, save the s tat us of the program being
executed, and execute an i nterrupt service ro utine . N MI an d FIRQ are not used
in early-model games. IRQ is supplied by the IRQA and IRQB outputs (4 mSec and
Count 240 interrupt respectively) of the ROM board PIA.

The E and Q inputs to the MPU are both 4 MHz clock signals, with the Q leading E
by 90®. A timing diagram of these signals may be found in the E and Q Generator
paragraph. Clamping diodes D12 through D15 prevent the MPU E and Q inputs from
being driven more than 0.7 VDC above -fSVD C or be low gr ound. The MPU reset gate
(60) allows the MPU to be reset by either WDR or RESET.

CLOCK GENERATOR (Figure 3-4)

The Clock Generator Circuit provides three basic clock frequencies from which
all system timing is derived. The 12 MHz clock is divided by two to obtain a 6
MHz clock, and by three to obtain a 4 MHz clock.

The 12 Mhz source is a two-inverter crystal oscillator with a third inverter to
buffer its output. It is inverted once more to become 12 MHz for the Video RAM
timing circuit, and 12 MHz is then inverted to provide a delayed 12 MHz clock
for a latch section of 6R.

The 6R latch supplying 6 MHz is connected in the toggle mode, with the D
input driven by the Q output. The output (6 MHz) changes states on the rising
edge of the 12 >ffiz clock, providing an output 6f one half the clock pulse input
frequency. The S input is driven by CR, forcing Q to a logic zero as long as CR
is low. CR goes high in synchronization with the E clock signal. The 6 MHz
output always starts from a logic zero and is in sync with the E clock.

Two JK flip-flops (7R) are configured as a divide- by-three counter. Since the K
inputs are tied high, the flip-flops toggle when the J input is high during a
high clock pulse. If the J input^ is low during the clock pulse the flip-flop
will perform a clear operation (Q - 0, Q = 1). With the J inputs wired to Q and
Q outputs as shown, the circuit has 3 stable states as shown in the timing dia-
gram. The output pulse rate is an as3mimetrical 4 MHz.

To obtain a 50% duty-cycle, the pulse at 7R-6 is used to clear a D latch section
of 6R. The rising edge of 12 MHz following this pulse clocks the high at the D
input to the Q output, producing a 4 MHz, 50% duty-cycle clock as shown in the

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C> SHIFT REGISTERS

Figure 3-4. Clock Generator

timing diagram. The Q output provides a 4 MHz signal which is 180* out of phase
with the Q output. Note that the 12 Mhz clock used here is delayed to com-
pensate for the propagation delay of the 7R flip-flops.

E AND Q GENERATOR (Figure 3-5)

The E & Q Generator supplies two overlapping clock signals necessary to the
operation of the MPU. These clocks are called E and Q. They are both 1 >fHz, 50%
duty-cycle, and Q leads E by 90** (250 nSec). Since the MPU accesses memory only
when the E clock is high, E is also used by some of the memory decoding cir-
cuits, the Video RAM timing circuit, and synchronizes the 6 MHz clock and the
Video Address generator.

The E^ and Q Generator consists of three D-type latches. The first flip-flop has
its Q output wired to its D input causing it to toggle on the rising edge of the
4 MHz clock.^ The first flip-flop is wired in the toggle mode with its D input
tied to its Q output. This produces a 2 MHz output at the Q and Q terminals of
this flip-flop. The 2 MHz signal clocks a second flip-flop, also wired in the
toggle mode, causing a 1 MHz square wave to appear at its Q output. This is the
Q clock signal.

The third flip-flop has its D input tied to the Q clock signal, causing its Q
output (the E clock signal) to follow the Q clock. Because this flip-flop is
clocked by the 2 MHz signal, it is clocked 90** later than the flip-flop provi-
ding the Q clock, causing E to lag Q by 90**. See the timing diagram in Figure

13

FROM
CLOCK t>
GENERATOR

^6D-I0
'■{POWER-ON RESET)

TO MPU, VIDEO
RAM TIMING,
DECODING CIRCUIT,
a POWER ON RESET

"H |*-500nt

5D-5

r— ""-1

'-^_J— L

_r

-M •— 250n»

° _r-L_

Figure 3-5. E AND Q GENERATOR

Video Address Generator (Figure 3-6)

The Video Address Generator supplies the 14 address-bit which scans the entire
Video RAM 60 times each second, reading out pixel codes to the Video Shift Re-
gisters. When power is first applied to the system, the Reset circuit asserts
CR (Clocked Reset Not), clearing the four 9316 type counters (5J, 5H, 5F, and
5E) which generate the Video Address. Function C5 is synchronized with the 1
MHz E clock. The generator is a 16-bit binary counter with the most-significant
14 bits used as the Video Address bus. The two least-significant bits of the
counter generate a carry to VAO once every 4 counts of the 4 MHz clock, causing
VAO to toggle at a 1 MHz rate, hence incrementing (adding 1 to) the video ad-
dress once every microsecond.

The least-significant 4-bit counter stage (5J) is continuously enabled by
pulling its CEP and GET inputs high, allowing it to count the 4 MHz clock
whenever CR is high. The parallel inputs for preloading the counter are not
used and are grounded. The PE input is disabled by tying it high. When this
first state reaches its terminal count (all Q outputs high), output TC enables
the CEP inputs of the three most-significant counter stages. The GET input of
the second 4-bit stage (5H) is pulled high, allowing it to count a 4 MHz clock
pulse every time the TC output of the first stage is high. (A high TC output
indicates a carry from that stage on the next clock pulse). The second and
third 4-bit stages (5F and 5E) enable the GET inputs of the next stages in the
same manner, causing each stage to count only on a carry from the previous st-
age, and since all stages are clocked ty the same 4 MHz signal, all outputs
change on the same clock pulse.

When the last video address (16, 3833^0) ^^ reached, all pixel codes in the
Video RAM have been read out to the screen, and the Video Address Generator is
ready to reset to count on the next clock pulse. Since the video address is
incremented once per microsecond, the elapsed time from video address zero to
video address 16,383io is approximately 16.4 raSec.

14

+5V

+5V

CR

O-

R42
4.7K

MR PQ **l ^ P3 PEp-^
CEP 5J 9316

CETCPQoQ) Q2Q3TC

R4I
4.7 K

MR Pq P} Pz P3 PE
CEP 5H 9316
CETCPQ0Q1Q2Q3TC

3

R40
4,7K

MR fb P| Pz P3 PE
CEP 5F 9316

cetCPQqQi Q2Q3TC

:R39
•4.7K

MR PQ P| Pz P3 f*t
CEP 5E 9316
CETCPQqQi QgQ; rC ^

250 ms

H — t6.6m«-

5E-I5

-JU-Z50r

50-1
*• {WATCHDOG
CIRCUIT)

Figure 3-6. Video Address Generator

At this count, the TC output from stage 5E latches a high at the 4E output. This
is gated with the TC outputs from stages 5J and 5E to produce a low to the PE
inputs of stages 5F and 5E. The next clock pulse preloads these counters to
16,128]^0 ^^^ counting, continuing until 16,383x0 is reached a second time,
increases the counting time to approximately 16.6 mSec.

When TC from 5E goes high the second time, a low is latched at the output of 4E.
The following clock pulse advances the counter to all zeroes. The CL input of
the latch is connected to VA13, and as VA13 goes low, the latch (4E) is cleared
to provide a parallel load at the next full count.

The Screen Control applied to AS of the Vertical decoder provides a top to
bottom flip, allowing the second player access to an upright and right-reading
image in a cocktail table game. The signal from the Screen Control is also
applied to the Horizontal Decoder and to the Video Shift Registers-

VIDEO RAM CONTROL (Figure 3-7)

The Video RAM Control Circuit allows sequential MFU addressing of the three lOK
video RAM banks. With eight low-order MPU Address Bus bits applied to the RAM,
the high-order bits access a PROM for generation of psuedo-address bus and
bank-enable signals.

MPU adddress bits AS through A15 are applied to Horizontal decoder PROM 3K and
appropriate PAS through PA13 (Pseudo-Address) bits are produced at the DO
through D5 outputs. Bits D6 and D7 provide a bank-select code. MPU Address
bits A14 and A15 are gated to produce a low enable function for all addresses
below COOO. (For addresses COOO through FFFF, both A14 and A15 are high and MPU
access to the RAM is inhibited). The Screen Control applied to AS of the
Horizontal decoder provides a left to right flip of the screen for Player 2 in

15

TO VIDEO RAM
ADDRESS MULTIPLEXER

TO CMOS RAM ft
COLOR RAM ADDRESS DECODER

SCREEN COffTROL [I|> ^

TO VIDEO RAM
DATA LATCHES

TO VI DEO RAM

Figure 3-7. Video RAM Control

cocktail table games. The Screen Control is also applied to the Horizontal
decoder and to the Video Shift Registers -

With both the D6 and D7 PROM outputs low, l-of-4 decoder 2F produces a low YO"
enable signal for RAM Bank 1. A high D6 and low D7 produce a low YT enable
signal for RAM Bank 2; A low D6 and high D7 produce a low Y2 enable for RAM
Bank 3.

Function R/W (Read/Write Not) is inverted to produce a low during read which is
gated with the YO, Yl, and Y2 functions. This pulses El, E2 and E3 low, to en-
able Video RAM data latches for Banks 1, 2, and 3. With a write operation, R/W
(Read Not/Write) is gated with the E Clock and WE (Write Enable) from the Video
RAM Timing Circuit to produce a low from 6P pin 6. The E Clock ensures that the
function is in phase with the MPU and WE synchronizes the function to the Video

RAM access timi ng. ^The l ow o utput is gated with the YO, Yl and Y2 lows to

produce low WEI, WE2, and WE3 (Write Enable Not) to enable writing to the three
RAM Banks.

The E Clock is gated to produce a low MUX 1 (Multiplex 1) enabling MPU RAM ac-
cess. For addresses from COOO to FFFF, A14 and A15 inhibit MUX 1. The inverted
R/W function is applied to the CMOS RAM and to the Color RAM Address Decoder.

16

VIDEO RAM TIMING (Figure 3-8) ^

The Video RAM Timing Circuit uses the 12 MHz and E and Q clocks to produce the
timing required for access to the Video RAM. The timing for multiplexing seven
memory address bits at a time and latching them into the RAMs is required. In
addition, a load pulse is produced every microsecond for shift registers that
forward video information toward the Color Monitor.

The E and Q clocks are applied to Exclusive-OR gate 5R; which provides a high
output when one, and only one, input is high. A low output occurs if both
inputs are high or both are low. The result is a 2 MHz square wave that is
clocked into a AS data latch section at 12 MHz. The Q output is then clocked
into the second 4S latch section to provide the 2 MHz MUX signal. Clocking
through the latches provides the phase relationship needed to multiplex the 14
video address bits into two groups of seven memory address bits for RAM rows and
columns (and MPU/Pseudo-Address bits into two groups). When MUX is low, row
address bits are selected; when it is high, column address bits are selected.

NOTE
MUX is used in conjunction with MUX 1 from the Video RAM
Control Circuit. When the MPU is addressing the RAM (any
address below COCO) and during the high state of the E clock,
MUX 1 is low, selecting the two groups of MPU and pseudo-
address bits. When the E clock is low, MUX 1 is high, select-
ing the two groups of video address bits. When the MPU is
accessing memory locations from COCO through FFFF, MUX 1 is
high, regardless of the state of the E clock. During such
MPU cycles, video address bits are selected and the RAM is
accessed; however, the data read from the RAMs remains
isolated from the video shift register and the MPU data bus.

:R35

-4.7K

R37
4TK

FROM ^

.E_aQ Q

GENERATOR [>-

40 X3

7486

CL
<\S Q

4S

74LS74

D Q

CK

FROM CLOCK
GENERATOR

12 MHZ

-.| [.-83. 3r

\zvmi mnJUumjiruuuiJTJUuuumnjuumr

.— 500ns— .t 1 ■ ■

;R36
■4.7K

:R45
4.7K

;R47
•4.7K

< — CIS

CL

Q

4S

74LS74

D Q

CK

TO VIDEO
-O ADDRESS

MULTIPLEXER

CL

-ds

5S

74LS74

D

CK

CAS

-I> TO VIDEO RAM

WE

FROM /

E ao n>^

GENERATOR

_^ TO VIDEO RAM
"^^ CONTROL

7404

10 1 7408

E

4D-3
3K-5
SO
RAS
CAS
SRL

iHJ \ TO SHIFT REGISTER

LL 6P ye SRLp ^ tSR) LOAD CONTROL
9 7410 f-* ^

ft SR CLOCK
INHIBIT FLIP-FLOP

TO VIDEO RAM ft
-D* VIDEO RAM DATA
LATCH / BUFFERS

-.i f.- 250 ns

-*\ 333n9 [.-

-.j f.-l67f»

J~l

■^ {.-125ns -^ [.-250n» •jl*-^'-6'«

~LI

-M ^-41.6n»

Figure 3-8. Video RAM Timing

17

Outputs of the 4S latches are gated to produce RAS (Row Address Select Not). As
this function goes low (alway s during the low state of MUX 0, row addresses are
latched into RAM. The 12 MHz clock is inverted to dela y th e 2 MHz signal from
the second 4S latch by approximately 42 mSec, producing CAS (Column Address
Select Not) and WE (Write Enable) signals. As function CAS goes low (always
during the high state of MUX 1), column address bits are latched into RAM. The
high state of WE causes the Video RAM Control Circuit to produce write-enable
signals to the Video RAM during the MPU write operation to the Video RAM.

The Q Clock, function WE, and RAS are gated to produce function SRL (Shift
Register Load Not). This function pulses low every microsecond to load data
from the RAM into the shift register.

VIDEO RAM ADDRESS MULTIPLEXER (Figure 3-9)

This circuit multiplexes 14 video address bits; 8 MPU, and 6 pseudo-address
bits, seven bits at a time, to provide row and column RAM memory address bits.
Video, MPU, and pseudo-address bits are applied through multiplexer chips and
selected with proper timing for the Video and MPU systems. Access is
with the video system reading and refreshing the screen, the MPU system writ-
ing to define the Color Monitor display, and reading/writing from/to the
portions of RAM that are off-screen and used for scratchpad memory. The multi-
plexer circuit consists of four dual 4-to-l multiplexers. With MUX and MUX 1
both low, PAS through PA13 and AO (applied to the 10 inputs of 4F, 3G, 31, and
4H) are placed on the MAO through MA6 memory address bus. When function RAS
(Row Address Select Not) goes low, MAO through MA6 are detected into the RAMs.
When MUX goes high, MPU address bits Al throug h A7 are placed on the MAO
through MA6 bus, and then latched into RAM when CAS (Column Address Select Not)
goes low. This completes the addressing cycle for MPU access.

When MUX 1 goes high, video address bits VAO through VA6 (MUX low) and VA7
through VA13 (MUX high) are selected and latched into RAM by the falling edges
of RAS and CAS.

18

iViViViV

VP7

VP8

VAO

VA1

VP9

VPtO

VPII

VA3

VA2

VA4

VA5

VPI2

Al

A2

A3

A4

AS

PA8

PAS

PA 10

PAII

PAI2

PAIS

A6

AO

A7

VP6

VPI3

RAS

CAS

19

Ea Cb

lOa

Ilo Yo

I2o

X3a

I0b4F

I.b™««
I2b Yb
X3b
SO SI

K

iO

13

15

S TE

XOa

Ila Yd

I2a

Z3a

I0b3G
j„T4l53

I2b Ybl

I3b
SO SI

14

10

12

13

15

Ea Eb
lOo

Ila Ya
I2a
I3a

lOb 31
I„ 741531

I2b Yb

I3b
SO SI

14

10

13

Eb

Ea

lOa
Ila
I2a
I3a
I0b4H

I.b^-^«^
I2b
I3b
SO

Ya

Yb

SI

14

MUX I VIDEO ^^y

MUX 2 FROM

-VIDEO RAM

HC.

MAO

MAI

MA2

MA3

MA4

MAS

MA6

A^

Figure 3-9. Video RAM Address Multiplexer

19

VIDEO RAM (Figures 3-10)

The Video RAM is provided by 3 banks of eight 16K-by-l bit RAM chips. Seven ad-
dress inputs on a memory address bus are used to access the memory locations.
During video system access, the data outputs are loaded in shift registers to
provide video information for the monitor. During MPU read operations, data is
placed on the MPU data bus; during MPU write, MPU data from the MPU data bus is
written into the RAM. Because of the similarity of RAM banks 1, 2, and 3 only
bank 1 will be discussed.

For an MPU read operatio n, row addresses are placed on the MAO through MA6 his
and the falling edge of RAS (Row Address Select Not) latches the row address
int o th e RAM. Next, column addresses are placed on the bus and the falling edge
of CAS (Column Address Select Not) latches the column address bits.

Data is read out of all three RAM Banks. The rising edge of RAS clocks the RAM
Bank Data Bus/bits DIO through D17, D20 through D27, and D30 through D37 into
data buffers. Function El (Enable 1 Not) from the Video RAM Control circuit is
then applied to the OE (Output Enable) input of data buffer IM, placing the Bank
1 Data Bus bits DIO through D17 onto the MPU Data Bus.

For an MPU write operation to Bank 1, the three RAM Banks are accessed as des-
cribed for the read operation and data is read from Banks 2 and 3 onto the Data
Bus bits D20 through D27 and D30 through D37. The Video RAM Control Circuit
provides WEI (Write Enable 1 Not) and the MPU Data Bus DO through D7 is written
into RAM Bank 1.

Video system access to the RAM is the same as described for MPU access except
that neither El nor WEI is produced. Instead, the Video RAM Timing Circuit
causes the three RAM Bank Data Busses to be loaded into shift registers. Note
that during MPU access time, when the MPU is accessing addresses above RAM
COOO]^5-FFFFi5, the video add ress bus accesses the RAM, but the RAM Bank Data
Busses are ignored since El, WEI, and the Video RAM Timing Circuit load signal
are all inactive.

20

Figure 3-10, Video RAM

21

VIDEO SHIFT REGISTERS (Figure 3-11)

The Video Shift Registers convert the 24-line RAM Bank Data Bus into a 4-bit
serial data flow. With information for six pixels (picture elements) on the RAM
Bank Data Bus, a load pulse from the Video RAM Timing Circuit places the
information into the shift registers and the 6 MHz clock shifts it out to the
Color RAM Address Multiplexer through Multiplexer 2M. For upright games and
Player 1 in table games, 10 to 40 registers are selected. For Player 2 in table
games. Screen Control goes high to select the IP to 4P registers. The former
registers are discussed.

When function SRL (Shift Register Load Not) goe s lo w, the RAM Bank Data Busses
are loaded into the shift registers. Function SRL also sets the 5S latch
section to produce a high clock inhibit. The D14 through D17 bits loaded into
the H inputs of the shift registers are available at the QH outputs.

The rising edge of the 4 MHz clock clears the 5S latch to permit the following
rising edge of the 6 MHz clock to shift the DIG through D13 bits, loaded into G
of the shift register, to the QH output. The following four 6 MHz rising edges,
clock the D24 through D27, D20 through D23, D34 throug h D3 7, and D30 through D33
data bits to the QH output. After 1 microsecond, a new SRL pulse is produced to
load the new data available from the next video system RAM access. This process
is continuously repeated as a part of normal game operation.

TO
DATA
BANKS

TO
OATfl
ANK2

FROM RAM

T 1 M I NG

SHIFT REGISTER
LOAD CONTROL

Figure 3-11. Video Shift Registers

22

COLOR RAM CIRCUIT (Figure 3-12)

The Color RAM is accessible to the MPU for storing data to define available col-
ors for presentation on the Color Monitor, The circuit continuously accepts
four lines of serial address information from the Video Shift Registers to ac-
cess the color RAM and places the data out for digital-to-analog conversion to
drive the red, green, and blue color guns of the Monitor. During intervals be-
tween horizontal traces when the serial information represents data from
scratchpad RAM, a blanking signal inhibits the drive to the Color Monitor guns.

Functions ¥/W (Read Not/Write), PSO (Page Select Not) from the Page Select
Decoder (inverted to be PSO), and the E Clock are gated to provide a high to 60
and 6J gates. Function E5 (Enable 5 Not), which corresponds to address COOO]^^
and MPU address bit A4 are gated with this high to p roduce a high WDFF
(Watchdog-Flip-Flop) for address COlOig or a low WCR (Write Color RAM Not) for
address COOO15. WDFF is applied to the Watchdog Timer.

Function E5 is applied to the color RAM address multiplexer to selec t MP U ad-
dress bits AO through A3. RAMs IC and 2C are addressed with the low WCR, and
the state of the MPU Data Bus bits DO through D7 is written into the addressed
location.

FROM VIDEO
RAM CONTROL

w/S"

FROM PAGE
SELECT DECODEfi

6M
6M ^7404

7404 31

O^

FROM BLANK IMG

HORIZONTAL I > '"-*"'""^
BLANKING

MPU ADDRESS

BUS

1^

A0_

AL

MZI

fj^ SERIAL

3

FROM

VIDEO SHIFT

r^ SERIAL t

6

^SERIAL 2

10

REGISTERS

SERIAL 3

"

""ial 60 "\i2

WDFF (COIOl

TO COLOR RAM
-O CONTROL LOGIC ft

wATCHOoecmcuiT

A2

A3 Y1

74LS257

Bl Y3

" T4

B3

FROM PAGE r>
DECODER ^

E5

VTJ'

» W/R SIGNALS READ WHEN LOW. WRITE
WHEN HIGH. (OPPOSITE OF R/W)

MPU DATA
BUS

u

■M

w

AO

Al 2C
A2
A3

5

GNO

000
DO
DOZ
003

WL

10 0^

12 03

AO

010
D1I
DIE

Al IC 013
7489

A2 000

DO I
DOZ

003

12 07

R7S< 03
I50a> 2N4403

iR24 i
>I.2K >

R2G

5«oa

jroii

RZT
330a

^012
IN4l4e

«.

2T0Q
RS

4""

::r

IN4I4S

>Ra {RIO
|33on ;:Man

TO VIDEO
MONITOR

Figure 3-12. Color RAM Circuit

23

With E5 high, Serials 0, 1, 2, and 3 are passed through the 2E multiplexer to
RAMs IC and 2C for reading. Data Output bits DOO, DOl, and D02 from RAM 2C are
applied to a D-to-A converter for the red gun- With all three bits high, Q3 is
cut off and no red gun drive is provided. A low DOO forward biases D9 to turn
on Q3 for minimum red gun drive. Low outputs on DOO, DOl, and D02, and com-
binations of the three outputs forward bias D9, Dll, and D12 for seven different
intensity levels of red gun drive.

The green gun circuit is similar, using the 2C D03 and IC DOO and DOl outputs.
The blue gun circuit accepts the IC D02 and D03 outputs to provide no blue gun
drive with both outputs high and three intensity levels with either one or both
outputs low.

During the intervals that the data on the serial busses represent scratchpad
RAM, the BLANKING function goes high and cuts off Q4. This removes power from
Ql, Q2, and Q3 and no drive is provided to the Color Monitor guns.

MONITOR SYNC GENERATOR (Figure 3-13)

Horizontal and Vertical sync pulse timing is derived from the video address bus,
which advances to the next video address (1 count) every microsecond. The first
Horizontal Sync pulse after the game is turned on starts at video address count
56, or 56 uSec after the Video Address Generator begins counting.

Horizontal S3nac is a 4 uSec pulse which occurs once every 64 uSec at the 56th
video address count (count 55) of each 64 count horizontal line. Vertical ad-
dresses VA3, VA4 and VA5 are high, and VA2 low, at horizontal count 55 of each
line, causing horizontal sync to be asserted. When the horizontal count reaches
60, VA2 goes high, ending the horizontal sjnnc pulse.

The Vertical Sync pulse is a 0.77 mSec pulse that occurs every 16.6 mSec VA9
through VA13 are gated to produce a high vertical sync at vertical count 248.
The pulse ends when the Video Address Counter reaches the all-zero count.

VIDEO

ADDRESS

BUS

%

r

VA9

VAIO

VAII

VA5

VA4

VA3

VA2

-r

|^2.3m»

16.64ms

5B
7404

r

10JJ7486/

t-

16. 6ms

-*| I* 0.77mt

1

13

1>^

40
7421

>

3A
7486

13

3A
7486^

R3I
4.7K

^

VERT. SYNC.

-O MONITOR

z^i^y

-OCOMP.

H0RI2. SYNC.

-£> MONITOR

MONITOR SYNC. GENERATION
Figure 3-13 Monitor Sync Generator

24

BLANKING CIRCUIT (Figure 3-14)

This circuit is used to disable the video output to the Color Monitor when the

memory section (scratchpad memory) outside the limits of the Color Monitor

screen is being used.

Using video address bits VAO, VA2, VA4, and VA5, as inputs to a quad-input NAND

gate 5C, the blanking signal is activated (set high) when the video address bits

are all high by a low pulse from 5C-8 to the 4B latch. The blanking signal

remains high for 14 microseconds: the time it takes for address bits VAO, VAl,

and VA5 to reach the proper states to cause pin 6 of 4C to go low.

VIDEO

ADDRESS

BUS

t^

VA5

VA4

VAE

VAO

VAO

VAI

H32

Hi6

H4

HI

H2

+5V

VA5

H32

BLANKING

TO
-D> VIDEO
DRIVERS

I* 53ys-

w 3us |*-5us-^ 3us H

iru — mi

53ut-*\

l_

|4ms

f

SOUS

h-50ys-»j

3S-6

BLANKING

Figure 3-14. Blanking Circuit

PAGE DECODER (Figure 3-15)

The Page Decoder generates enable signals for MPU access of the color RAM,
CMOS RAM, Vertical Count Buffer, and Interface Board PIA when Page is
selected. Fun ction PSO (Page Select Not) is asserted as long as Page is
selected, and PE-PSO is asserted when the MPU accesses Page Selectable Memory
(COOO through CFFF) with Page selected. When the MPU a ccesse s Page Selectable
Memory (COOO through CFFF) with Page selected, PSO and PE^PSO are both
asserted, enabling one-of-four decoder 4K. With AlO and All as inputs, each
decoder output corresponds to a IK segment of the page, and is asserted (low)
whenever the MPU accesses an address within that IK segment. The address shown
on each output of the 74139 is the starting address of the IK segment for which
that output will be asserted. Function IPIA is an active high signal and is
generated by using a 7427 NOR gate as a negative- logic NAND gate (output is high
only when all inputs are low). Note that additional address decoding for the
Interface Board PIA is provided on the Interface Board.

25

FROM PAGE »— ^ PSO
SELECT DECODER 1-^

ROM /PAGE DECODER

FROM

MPU

ADDRESS

BUS j>, All

IPIA INTERFACE
BOARD
PIA ENABLE

VERTICAL

O RAM

ENABLE

Figure 3-15. Page Decoder

CMOS RAM (Figure 3-16)

The CMOS RAM has a standby power supply (Bl, B2, B3) to save critical data while
main power is off, and a memory protect circuit gating its R/W (Read/Write Not)
input to protect the upper 128 locations from being changed while the coin door
is closed. When the coin door is open, the data in the upper 128 locations of
the CMOS RAM may be changed.

When the coin door interface switch is closed, a low is applied to inverter 5B,
causing the MP (Memory Protect) signal to go high. Function MP will be low
anytime the coin door switch is open or disconnected. Function MP is gated with
MPU address bit A7 to produce a WI (Write Inhibit) signal which is asserted
anytime the coin door is closed and the MPU is addressing any location from
C600i5 to C7FFi5. JFunction WI is gated with the MPU R/W line to provide the
CMOS RAM with a R/W signal which will not go low (write) for any of the upper
128 locations (C600 through C7FF) while the coin door is closed. When the coin
door is open, MP is negated and no write signal is inhibited. If the MPU is ad-
dressing one of the lower 128 locations (C400]l6 through C5FF]^5), A7 will be
low and a write signal is not inhibited at any time.

Two chip-enable inputs (CEl, CE2) must be asserted to access the RAM chip.

Function CE2 is asserted by RESET , which is high during normal operation. CEl
is asserted when both E6 and PSO are asserted, enabling the CMOS RAM for a data
transfer when the MPU addresses any location from C400 to C7FF with Page

DI3
m5B!7

COIN DOOR WRITE
PROTECTION SWITCH
(HELD CLOSED WHEN
COIN DOOR IS CU:>SEO)

DI4
IN4148 8; B2 f3

1.5V 1.5V 1.5V ~

* W/R SIGNALS ARE READ WHEN
LOW, WRITE WHEN_HIGH
(OPPOSITE OF R/W )

MPU
DATA
SUS

Figure 3-16. CMOS RAM

26

selected. Which of the 256 RAM locations gets accessed is determined by MPU
address bits AO through A7«

The RAM output buffers are disabled (tri-stated) by R/W when the MPU writes
data to the RAM, and enabled when the MPU reads the RAM, thus allowing the RAM
input and output bits to be tied together to the bi-directional MPU Data Bus
with no drive conflicts. Data-transfers occur over MPU Data Bus bits DO through
D3, bits DA-D7 are ignored.

Diodes D14 and D13 form a switch that connects the CMOS RAM and gate 6H to the
higher of the two supply voltages. When main power is on, current flows through
D13 from the +5 power supply and D14 is reverse biased, isolating the standby
batteries from the circuit. When the main power is turned off (or fails), and
the +5VDC supply drops, D14 begins to conduct as its cathode reaches .7VDC below
its anode, and holds the RAM Vcc at 3.8 VDC. The +5VDC supply continues to drop
to OV, causing D13 to become reverse biased and isolating the +5VDC supply line
from the standby supply.

When the +5V supply has dropped to approximately 4.75 VDC the Reset circuit as-
serts CR, negating the CE2 input of the RAM and disabling any data transfers un-
til the main power is on and stabilized. IC 6H and resistor R5i are also con-
nected to the standty supply in order to prevent the r/w input of the RAM from
going low (write mode) with power off.

VERTICAL COUNT BUFFER (Figure 3-17)

This buffer provides the program the ability to determine the vertical position
of the scan on the monitor. When this circuit is accessed, the high-order 6
bits of the Video Address Bus are placed onto the MPU Data Bus. When the MPU
reads from address CBOO, the Pag e Decoder provides a low E7 (Enable 7 Not).
Function E7 is gated with a low PSO (Page Select Not) from the ROM Board to
place a low on the enable inputs of buffer 3D. Video address bits VA8 through
VA13 are then placed on MPU Data Bus bits D2 through D7.

MPU
DATA
BUS

FROM PAGE
SELECT DECODER

n?OM PAGE I>
DECODER

Figure 3-17. Vertical Count Buffer

COUNT 240 (Figure 3-18)

COUNT 240 produces an interrupt for the MPU indicating that the scan is at the
bottom of the screen. COUNT 240 is applied to the PIA on the RAM Board to
produce an interrupt for the MPU. When the video address reaches 15,360io
(Vertical Count 240), VAIO through VA13 are all high, causing COUNT 240 to go
high. Since VAIO through VA13 remain high for all video addresses above
15,359io> COUNT 240 will be asserted for approximately 1.3 mSec (until the
video address reaches maximum and starts again at zero). Since the screen is
"scanned" or "refreshed" 60 times per second, COUNT 240 occurs at a 16.6 mSec
rate.

27

VIDEO

ADDRESS

BUS

\

VAIO

W

VA12

VAI3

10

13

4C

742

)

-^ l*-l-3ms

COUNT 240

4 MS -IRQ

O

TO ROM
BOARD PIA

>T0 IJI-3

Figure 3-18. Count 240

ROM BOARD MEMORY SCHEME (Figure 3-19)

The ROM board in the DEFENDER game contains the main game program. Figure 4-1
shows a typical pair of memory devices used on the ROM board. The main game
program requires that there be 4K memory locations present in or between ICl and
IC4, IC2 and IC5, IC3 and IC6 to contain memory sections labeled D, E, and F.
These memory sections correspond to address blocks DOOO, EOOO, and FOOO.

If ICl is a 2K memory device, then IC4 must be a 2K memory device also to
provide the necessary memoiry locations. When the memory section (D, E, or F) is
split this way, th e U pper/Lower ROM Decoder LE (Lower-Half Enable Not) is con-
nected to pin 18 (CS2: Chip Select 2 Not) of ICl_and the Upper/Lower ROM Decoder
UE (Upper-Half Enable Not) connected to pin 18 (CS2) of IC4. These signals
select the memory section half (DOOO or D800).

While the memory section half is bein g selected, the ROM/Page Decoder selects
the memory section by supplying a CSl (Chip Select 1 Not) signal to pin 20 of
each memory IC (ICl and IC4) of the section (D) selected.

Note that jumpers Wl and W4 must be added when ICl and IC4 are 2K memory de-
vices. These jumpers are needed to make the pin 20 CSl connection common to
both ICs and to connect the UE signal as required.

FROM PAGE SELECT DECODER ICI6-3 D>

PS9

FROM ROM /PAGE DECODER IC26-8n>-

MAIN PROGRAM
LOWER HALF

DOOO

FROM
UPPER/

ROM or

1/LOWER
ECODER

LE

,04

MAIN PROGRAM
UPPER HALF O-

PAGE ENABLE
LOWER HALF

uf_W4

2A\

'aoi.

PLEq WsI 18

MPU ADDRESS BUS
MPU DATA BUS

^

28

AIO

AK

19

V

22

AS

23

A7

A6

AS

A4

A3

A2

AO

CS2/AI1

AtO

A9

A8

A7

A6 IC4

CSl

CS3
07
06
05

^_ De00/2K ^^
*5 C000/4K ^
A4 PAGE 9 D3

07

16

D6

D5

14

04

D3

02

10

DO

12

AIO

A9

AB

A7

A6

A5

A4

A3

A2.

At

AO

16

19

22

23

^ooii

CSl

CS2/AI1

AIO

A9 CS3

A8 07

A7 06

A6 IC I 05
. - D000/2K ^^

A4 03

TIT

20

17

16

14

13

10

Figure 3-19. ROM Board Memory Scheme

-t-5V

IC7-2I
ICl -21

07

^\

05

04

03

02

01

DO

When ICl is a 4K device, IC4 can be used to hold extra game features • (This Is
the case with IC3 and IC6.) Using ICl and IC4 as an example, pin 18 of ICl Is
address- bit 11 of the Input address, and pin 18 of IC4 becomes the input for the
PLE (Page enable lower half not) signal through jumper W3 from the Upper/Lower
ROM Decoder. Also, pin 20 of IC4 is independent of ICl pin 20, and is connected
to the Page Select Decoder through jumper W2. Table 4-1 shows the two versions
of DEFENDER produced. Note that only version 2 has need for jumpers W2 and W4.

TABLE 4-1

DEFENDER

MEMORY SECTION

VERSION

VERSION

IC

1

2

1

2

1

4K

2K

DOOO

DOOO

2

4K

4K

EOOO

EOOO

3

4K

4K

FOOD

FOOO

4
5

—

2K

-

D800

6

2K

2K

COOO/7*

COOO/7*

7

2K

2K

COOO/3*

COOO/3*

8

2K

2K

COOO/2*

COOO/2*

9

2K

2K

COOO/1*

COOO/1*

10

2K

2K

C800/3*

C800/3*

11

2K

2K

C800/2*

C800/2*

12

2K

2K

C800/1*

C800/1*

* Memory Section/Page

ICs 6 through 12 contain memory block COOO, and all pages thereof. Note that CS
3 (Pin 21) of each IC is tied high through resistor Rl, R2, or R3 so that input
is always enabled.

SECTION/PAGE SELECT DECODER (Figure 3-20)

This decoder provides page-enable signals PSO through PS9 using MPU data bits
DO, Dl, D2, and D3. These four bits are BCD input signals to IC17, which, when
clocked, presents these bits to pins 15, 14, 13, and 12 of IC13, a BCD-to-
Decimal converter. IC17 is clocked when pin 10 goes low. This occurs whenever
the E clock, R/W input from the MPU, and the memory section D enable signal (Yl
of IC15) all go low. IC13 then provides an enable signal to 1 of 10 possible
pages selected by the BCD input.

Memory section selections are made by IC15 and MPU address bits 15, 14, 13, and
12. Address bits 12 and 13 provide the selection input, and bits 14 and 15
(which activate once the address is above BFFF) provide a clock pulse from pin 8
of IC18 when both bits are high. When_page zero is selected by IC13 (PSO), and
memory sec tion C is selected by IC15 (PE), Pin 3 of IC14 goes low, effectively
producing PE'PSO for input to the page zero decoder on the CPU/Video Board.

29

+ 5V

MPU
DATA
BUS

FROM ESQ GENERATOR C>"

^

CK GNDp ft—i

14

13

9

8

IC13 7
7442 6

GND

PS9

10

PS8

iSLj

.£§6.

PS5

PS3,

•mi>

PS I

PSO,

AI2

AI3

CIS

-# ,ot

AI4 9

-fSV

YOO

B Yl

ICISyZO^
74139

— Y3
El

AI5

11

MPU

ADDRESS

BUS

ICiS
I0|7400

XQ

PAGE ENABLE

C^^

5 J 7432

l^CI9

404

IC26-I3

PSO
IC20-4^
IC20-II

SELECTS I OF tO PAGES TO
APPEAR AT COOO THROUGH
CFFF. PAGE CONTAINS
COLOR RAM, CMOS RAM.
VERTICAL COUNT BUFFER,
AND PI A. PAGES I THROUGH
9 CONTAIN ROM ONLY.

J— v> TO PAGE DECODER
' — ^ (CPU/VIDEO BOARD)

COOO

-O ENABLES SELECTED PAGE

DOOO

EOOO

FOOD

ENABLES MAIN
PROGRAM ROM'S

■C>IC26-9,-l2

EDMA

_^ TO DMA

"*> ( LATER MODELS ONLY)

ICI4
17432

PE- PSO

TO PAGE DECODER
(CPU/VIDEO BOARD)

PE
ICI5-I5

ICI6-I0

SECTION / PAGE SELECT DECODER

Figure 3-20. Section/Page Select Decoder

ROM SECTION/HALF DECODER (Figure 3-21) _

This decoder uses the eleventh MPU address bit (All) and the MPU R/W signal to
determine the tnemory section half to be used hy the main program* When address
bit All is low, IC19 presents a high to pin 4 of IC18. Then, when the R/W
signal is high, the output of IC18 (pin 6) is a low (LE), enabling the lower
half of the memory section selected.

When address bit All is high and the MPU R/W signal is high, the pin 3 output of
IC18 is a low (UE), enabling the upper half of the memory section selected.

FROM MPU r ^ All 1

ADDRESS BUS ^ *

ICI9

7404

FROM MPU [>

R/W

ICI8 \-6 LE^ MAIN PROGRAM

41 7400 P ^ LOWER HALF

OF 4K SECTION

1018 V3 UE^MAIN PROGRAM

n O UPPER HALF

' '^ OF 4K SECTION

Figure 3-21. ROM Section/Half Decoder

30

ROM BOARD PIA/DECODER (Figures 3-22 & 3-23)

The PIA decoder uses inputs from the MPU address bus and the Section/Page De-
coder. Address bits AID and All are applied to pins 14 and 13 of IC15 re-
spectively. A low output at Pin 9 (Y3) is produced when AID and All are both
high (CCOO) and PE (Page-Enable-Not) from the Section/Page Decoder is low.
This Y3 output is then gated with MPU address bit A4 and PSO (Page Select Zero
Not) from the Section/Page Decoder to produce RPIA (ROM PIA) (address CCIO).

The A2 output of IC19 is gated through IC20, and applied to pin 24 of IC22
(CSl). The RPIA output of IC20 is applied to Pin 22 of IC22 (CSO). MPU address
bit A3 is applied to Pin 23 of IC22 (CS2).

Data bits through 7 on the MPU Data Bus are used for, inputs from/outputs to,
the coin door switches and sound module. Peripheral register A is used for coin
door data and register B is used for sound module control. The program peri-
odically reads register A and writes to register B to request sounds.

Inputs CAl, CA2, and CBl are from the Count 240 circuit, the coin door slam
switch, and function VAll from the video address generator. The _
negative-to-positive transition of any of these inputs cause IRQA & B (Interrupt
Request Not) to go low. The MPU then reads the PIA to determine which input
occurred. The CB2 lead is incorporated to provide "handshake" between the MPU
chip on the Sound Board; this handshake is not implemented in DEFENDER.

MPU address bits AO and Al are applied to Pins 35 and 36 of IC22 fo^ Register
select zero and Register select one (RSO and RSI) controls. The R/W signal from
the MPU is applied to Pin 21 of IC22 and controls the direction of data flow
through the PIA. The E input at Pin 25 of IC22 is the clock source for the
chip. The Reset circuit input to the PIA at Pin 34 is used to clear the PIA
registers when the game is being reset.

+5V

FROM SECTION /PAGE ^ PSO
SELECT DECODER ^^

^ A4

FROM MPU
ADDRESS BUS

FROM SECTION /PAGE - ^ PAGE ENABLE
SELECT DECODER ^^ ~~

FROM MPU
ADDRESS BUS

O TO ROM BOARD PIA

O TO ROM BOARD PIA tIC22l

ik USED ON LATER MODELS ONLY-

ROM BOARD PIA DECODER

Figure 22. ROM PIA Address Decoder

31

+5V

TO MPU<3"

FROM RESET CIRCUIT O

FROM ESQ GENERATOR O

FROM MPU C>

FROM MPU C>

ADDRESS bus'

o

10F4
h- DIAGNOSTIC
LED OUTPUTS

TO/ FROM MPU <^ MPU DATA BUS ^ DO-7

A3

FROM
ROM BOARD , ^
PIA DECODER lO"

.{:

A2

24

RPIA

CB2
RSO
RSI IC22

23

-GCS2

CSI

cso

6N0

PAO-5
CA2I
CAI
CBI

±

SOUND
SELECT
OUTPUTS

<^ I INPUT

TO /FROM
SOUND MODULE

XC24
7404

39

40

FROM VIDEO p ^4 mSEC (VAHI)

ADDRESS GENERATOR
FROM COUNT 240 GATE O

COUNT 240

C40
470pF

<

■<3] FROM COIN DOOR SWITCHES

470 pF

109
7404

+5V

<J^

IC23-9
4.7K

_C3I
470 pF

^.^ I INPUT FROM
-<J COIN DOOR SWITCHES

C39
470pF

-M- THIS INPUT IS PROVIDED FOR SOUND MODULE BUSY
STATUS , USED ON LATER MODELS.

Figure 23. ROM Board PIA

INTERFACE BOARD ASSEMBLY (Figure 3-24)

Chip ICl, a PIA, is used to interface player switches with game circuits. MPU
Data Bus bits through 7 are used to connect the inputs to the MPU. The MPU
R/W signal controls the direction of data flow. MPU address bit A3 is inverted
through IC4 and applied to Pin 22 (CSO) of ICl. MPU address bit A2 is applied
to Pin 24, CSI.

The IPIA signal from the Page Decoder is inverted through IC4 and applied to
Pin 23, CS2. MPU address bits AO and Al are applied to RSO (ROM Select 0) and
RSI (ROM Select 1); respectively. The E clock is used to clock ICl, and the Re-
set Circuit input is at Pin 34.

Switched ground inputs from the 1- and 2-player start switches are inverted by
sections of IC2 and applied to the PIA. In upright games, jumper Wl is
connected and the low at PB7 identifies "upright" to the program. In table
games, Wl is removed and the high at PB7 identifies "table".

In upright games with red- labeled ROMs, CB2 is set to high impedance and the
input to pin 1 of the 74LS257 is high, always selecting Player 1 switches. With
earlier programs, the state of CB2 is not assured, so jumper W2 must be removed
for proper player panel operation.

In table games, the program altenates states of CB2 to select either switches
from the player 1 panel or switches from the player 2 panel.

32

+ 5V

FROM RESET CIRCUIT [3>

FROM ESQ GENERATOR Q>

FROM MPU Q>

TO/ FROM MPU < MPU DATA BUS

FROM MPU
ADDRESS BUS

NOTE : FOR COCKTAIL TABLE Wl
REMOVED. FOR UPRIGHT'
CONNECT Wl; IF ROMSARE
NOT RED-LABELED.
REMOVE W2.

FROM PAGE DECODER O

FROM MPU ADDRESS BUS O

- o

PLAYER 2
470PF

Figure 24. Interface Board Assembly

33

POWER SUPPLY

+5VDC Regulated. + 12, -12700 Unregulated Supplies (Fig ure 3-25)

A transformer secondary provides a nominal 21.4VAC referenced to a center-tapped

ground to 4J1. The AC is fused and applied across bridge rectifier BRl. A

nominal -14,8 VDC (measured at TP3) is filtered by C6 and applied through 4J2 to

the Sound Board for audio amplifier power. Similarly, a nominal +12.8 VDC

(measured at TP2) is filtered by C12 and applied through 4J2 to the CPU/Video

and Sound Board. The unregulated +12 VDC is applied to a power-on reset circuit

on the CPU Board and provides amplifier power and an input to a 5-volt regulator

on the Sound Board.

One leg of the AC input is applied to a voltage doubler consisting of C2-C3 and
D2-D3 to provide a nominal +27.4VDC to regulator ICl. Resistor Rl and R2
provide the voltage reference of 5.1VDC at ICl-5; the values are critical. The V
output at ICl-10 is applied to the base of the 2N6057 series regulator and the
unregulated +12VDC to the collector to produce 5.1VDC (measured at TPl) which is
applied through 4J2 to the CPU/Video, ROM, and (via the CPU/Video Board) the
Interface Board.

With an increase of the +5VDC load, the drop across R6 would be greater and the
output would tend to decrease. The voltage fed back to ICl-4 (inverting input)
causes the voltage at ICl-lO to go more positive to maintain the +5.1 VDC output
Similarly, a decrease in the load causes the ICl-lO voltage to go less positive.

The voltage divider consisting of R5 and R13 senses output current and at ap-
proximately 5A, applies a current limiting bias at ICl-2, dropping the ICl-10
voltage. If the load approaches approximately 6.2A, foldback current limiting
occurs and the current through R6 is limited to approximately 1.3A. Therefore,
a low voltage output with approximately 200mV dropped across R6 is an indica-
tion of an overload on one of the logic boards (CPU/Video, ROM, or Interface).
Resistor R7 aids in the foldback current limiting and diode Dl provides tem-
perature compensation for the current limiting.

LED 1 conducts through R16 to provide an indication of output voltage. Note,
however, that should a circuit fault cause a high or low voltage, LED 1 may
still be lit.

4J2-3J8

4J2-I2,I3,I4.I9

4 J2- 7.6,9, 10, 1

H2V0C
UNREGULATED

o

4JZ-4

Figure 3-25. +5VDC Regulated, +12,-12VDC Unregulated Supplies

34

+27VDC Unregulated and +12VDC Regulated Supplies (Figure 3-26)
A nominal 20.9VAC from a transformer secondary is applied through AJl where it
is fused and applied across bridge rectifier BR2. A nominal +26.6VDC is
filtered by C13 and applied out 4J3 for power to the coin lockout relay. The
+26.6VDC is also applied to regulator IC2 and pass transistor Ql. The 12.1VDC
output (measured at TP4) is applied through 4J2 to RAMs on the CPU/Video Board.

The voltage divider consisting of R9 and RIO provides both a reference voltage
and feedback to the inverting input at IC2-4. The V output at IC2-10 is applied
to the base of Ql, establishing +12.rVDC at TP4. With an increase of the load
on the +12VDC, the voltage at IC2-4 tends to go less positive which increases
the voltage at IC2-10 to maintain the output voltage. Similarly, a decrease in
the load causes the IC2-10 voltage to decrease.

The voltage divider consisting of Rll and R13 sets a current limiting bias of
approximately lA. Should the load increase to approximately 1.3A, foldback cur-
rent limiting goes into effect and the voltage at ICl-10 is dropped to a level
to allow only approximated 50 mA of current through Ql. Therefore, a low volt-
age output with approximately 15mV dropped across R14 is an indication of an
overload on the CPU/Video Board.

Resistor R8 provides temperature compensation. LED 2 conducts through R17 to
provide an indication of output voltage. Note, however, that should a circuit
fault cause a high or low voltage, LED 2 may still be lit.

X"

-O *J3-6

266 VDC

A.C
20.9VAC Q>

+2rVDC
UNREGULATED
O 4J3-3

Ql
2N3075

■i-fZ.JVDC

'h7.2VDC

//r|4
0,271

27n

TP4
-hlZJVDC (J) REGULATED

VREF

IC2
723

Vcc
VO

CL

IN

cs

COMP

10

57, 3W
'■('I2.9VDC
RM

I. IK 2%
2 -f-ft.eVDC

\

lOOpF
50V

^14 J VDC

-:r5

5 4

■hZZVDC

R9
99K

17.

RIO

7.32K

17,

C8

0.1 MFD
50V

C7

lOOMFD
25V

■C> *J2-3

<RI7

^l.2K

57.

LEO 2

1. 6 VDC

GND
O
4J2-8

Figure 3-26. +27VDC Unregulated and +12VDC Regulated Supplies

35

-5VDC Regulated, 6>3VAC Supplies (Figure 3-27)

A nominal 9.1VAC from a transformer secondary Is applied to 4J1. One line Is
fused and the two lines are applied out 4J3 for general Illumination power. On
cocktail table games, jumper Wl Is open and R15 drops the AC voltage to a
nominal 6.3VAC* On upright games, jumper Wl shorts R15 and a dropping resistor
on the power panel lowers the AC voltage.

A separate fuse Is In one line and the two lines are applied across bridge
rectifier BR3. A nominal 10.4VDC is produced and filtered by C14. The Q2
voltage regulator provides a -5, + or -0.2VDC output (regulation to within 50mV)
to RAMs on the CPU/Video Board. The regulator incorporates Internal current
limiting and will drop the output voltage to -I.IVDC with a short-circuited
load.

LED 3 conducts through R18 to provide an indication of output voltage. Note,
however, that should a fault cause a high or low voltage, LED 3 may still be
lit.

9,IVAC

4ja-7

6.3VAC

O 4J3-2
6.3VAC

C> 403-1

Figure 3-27. -5VDC Regulated, 6.3VAC Supplies

36