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Guidelines

ind

ion Notes

by Steve Ciarcia

Build Your Own

Z 80 Computer

Design Guidelines
and

Application Notes

Steve Ciarcia

BYTE Books/A McGraw-Hill Publication/70 Main St/Peterborough New Hampshire 03458

Build Your Own Z80 Computer

Copyright © 1981 by Steve Ciarcia. All rights reserved. Printed in the United States
of America. No part of this book may be reproduced, stored in a retrieval system,
or transmitted, in any form, or by any means, electronic, mechanical, photocopy¬
ing, recording, or otherwise, without the prior written permission of the author.

The author of the circuits and programs provided with this book has carefully re¬
viewed them to ensure their performance in accordance with the specifications
described in this book. Neither the author nor BYTE Publications Inc., however,
make any warranties concerning the circuits or programs and assume no respon¬
sibility or liability of any kind for errors in the circuits or programs, or for the con¬
sequences of any such errors. The circuits and programs are the sole property of the
author and have been registered with the United States Copyright Office.

The author would like to acknowledge that portions of this book have been re¬
printed by permission of the manufacturers. The instruction codes in Chapter 3 and
Z80 CPU technical information have been reprinted by permission of Zilog, Inc.
Chapter 9 is based on an application note reprinted by permission of SMC
Microsystems Corporation.

Library of Congress Cataloging in Publication Data
Ciarcia, Steve.

Build your own Z80 computer.

Includes index.

1. Electronic digital computers-Amateurs' manuals.
2. Zilog Model Z-80 (Computer) I. Title.
TK9969.C52 621.3819'582 81-4335

ISBN 0-07-010962-1 AACR2

5678910 KGPKGP 89876543

ISBN □-□7-D10 c ib2-l

Text set In Paladium by BYTE Publications

Edited by Bruce Roberts and Nicholas Bedworth

Design and Production Supervision

by Ellen Klempner

Production by Mike Lonsky

Cover Photo by Charley Freiberg

Copy Edited by Rich Friedman and Peg Clement

Figure and Table Illustrations

by Tech Art Associates

Printed and bound using 45# Bookmark

by Kingsport Press, Kingsport, Tennessee

Copyrighted material

To my wife Joyce,

Steve Sunderland, and Judy and Lloyd Kishinsky

Build Your Own

Z 80 Computer

Thls O n 9

SWP8-P3T-PERL

Copyrighted material

Introduction

A few years ago, when microprocessors were first introduced, computer enthusiasts
and electrical engineers were one and the same. Those of us who lived only to solder
kluge after kluge basked in our glory. Now, however, the prices of completely assem¬
bled and packaged systems have plummeted. Today anyone with an interest, almost
regardless of technical capabilities, can own and operate a computer. Buying a com¬
puter is now similar to purchasing a television set and the ranks of computer en¬
thusiasts have swelled accordingly.

With any popular movement, the available literature reflects the concerns of a ma¬
jority of the followers. And, consistent with the popularization of computer science,
the technical emphasis on computer bookshelves has shifted away from hardware

design. Other than introductory texts called, say. How Logic Cates Work , most com¬
puter books either treat microcomputer hardware simplistically or attempt to be
"catch-all" cookbooks, sometimes omitting tasty ingredients. Often, the only alter¬
natives are engineering texts and trade journals, tedious reading at best.

For a number of years, I have been writing a column for BYTE magazine, and reader
response has shown that there still exists a great deal of interest in hardware design and
do-it-yourself projects. At the same time. I've been painfully aware of the lack of
materials for such people. Most queries come from technical or high school students
who have read all the descriptions and studied the block diagrams, but who crave prac¬
tical answers and system examples. Unfortunately, there are very few books I can sug¬
gest.

Build Your Own Z80 Computer is a book written for technically minded individuals
who are interested in knowing what is inside a microcomputer. It is for persons who,
already possessing a basic understanding of electronics, want to build rather than pur*-

chase a computer. It is not an introductory electronics handbook that starts by describ¬
ing logic gates nor on the other hand is it a text written only for engineering students.
While serving to educate the curious, the objective of this book is to present a practical,
step-by-step analysis of digital computer architecture, and the construction details of a
complete and functional microcomputer.

The computer to be constructed is called a Z80 Applications Processor—ZAP com¬
puter for short. It is based on the industry standard Zilog Z80 microprocessor chip.
This chip was chosen on the basis of its availability and low cost, as were the other
components for ZAP. To further help the homebrew enthusiast, and for those ex¬
perimenters who prefer to start a book at the back, I have listed in Appendix A a com¬
pany that supplies programmed EPROMs (erasable-programmable read-only
memory).

I have structured the book as a logical sequence of construction milestones in¬
terspersed by practical discussions on the theory of operation. My purpose is twofold:
to help a potential builder gain confidence, and to make the material more palatable

through concrete examples.

Though this is basically a construction manual, considerable effort is given to the
"why's" and "how's" of computer design. The reader is exposed to various subjects, in¬
cluding: the internal architectures of selected microprocessors, memory mapping,
input/output interfacing, power supplies, peripheral communication, and program¬
ming. All discussions try to make the reader aware of each individual component's ef¬
fect on the total system. Even though I have documented the specific details of the ZAP
computer, it is my intention (and the premise of the book) that the reader will be able
to configure a custom computer. ZAP is an experimental tool that can be expanded to
meet a variety of applications.

ZAP is constructed as a series of subsystems that can be checked and exercised in¬
dependently. The first item to be built is the power supply. This is a good way to test
ability and provide immediate positive reinforcement from successful construction.
The three-voltage supply is both overvoltage and overtemperature protected and has
adequate current for an expanded ZAP system.

Next, the reader learns why the Z80 was chosen for ZAP and the architectural con¬
siderations that affect component selection on the other subsystems. A full chapter is
devoted to the Z80 chip. Each control signal is explained in detail and each instruction
is carefully documented.

The hardware construction proceeds in stages with intermediate testing in order to
ensure success. The basic elements of the computer are assembled first and then
checked out. The reader selects which peripherals are to be added. The book contains
sections on the construction of a hexadecimal display, keyboard, EPROM program¬
mer, RS-232C serial interface, cassette mass storage system, and fully functional CRT
terminal. In addition, a chapter addresses interfacing the ZAP to analog signals. I pro¬
vide specific circuits that can convert ZAP into a digital speech synthesizer or a data ac¬
quisition system and data logger.

A special 1 K (1024 bytes) software monitor coordinates the activities of the basic
computer system and the peripherals. Software is explained through flow diagrams and
annotated listings. With this monitor as an integral component, ZAP can function as a
computer terminal, a dedicated controller, or a software development system.

Build Your Own Z80 Computer is a book for hardware people. It cuts through the
theoretical presentations on microcomputers and presents a real "How-to” analysis
suitable for the reader with some electronics experience or for the novice who can call
someone for supervision. From the power supply to the central processor, this book is
written for people who want to understand what they build.

Steve Ciarcia
May 1981

Copyrighted material

TABLE OF CONTENTS

Introduction

Chapter 1 Power Supply.1

Chapter 2 Central Processor Basics.21

Chapter 3 » The Z80 Microprocessor.27

Chapter 4 Build Your Own Computer - Start With the Basics ... 91

Chapter 5 The Basic Peripherals.129

Chapter 6 The ZAP MONITOR Software.151

Chapter 7 Programming an EPROM.173

Chapter 8 Connecting ZAP to the Real World.183

Chapter 9 Build a CRT Terminal.213

Appendix A Construction Techniques.225

Append ix B ASCII Codes.229

Appendix C Manufacturers' Specification Sheets.233

Cl 2 7 03 3K ( I K x 8 ) UV Erasa b le PROM . 235

C2 271616K (2K X 8) UV Erasable PROM.239

C3 2102A IK X 1 Bit Static RAM.243

C4 2114A IK X 4 Bit Static RAM.247

C5 8212 8-Bit Input/Output Port.251

C6 KR2376-XX Keyboard Encoder Read-Only Memory.259

C7 CQM2017 Universal Asynchronous Receiver Transmitter . 263

C9 CRT 8002 Video Display Attributes Controller.279

CIO COM8Q46 Baud Rate Generator.287

Appendix D ZAP Operating System.293

Appendix E Z80 CPU Technical Specifications.307

El Electrical Specifications.309

E2 CPU Timing.313

E3 Instruction Set Summary.321

Glossary.325

Index.329

CHAPTER 1
POWER SUPPLY

It's not enough to build a central processor card with a little input/output (I/O) and
memory, and call it a computer. From the time you walk over to the computer and flip
the switch, the system is completely dependent upon the proper operation of its power
supply. A book concerned with building a computer system from scratch would be
completely inadequate without a description of how to construct an appropriate power
supply.

Much has been written on the subject of direct current (DC) power supplies. There
are DC to DC and AC (alternating current) to DC converters, switching and shunt
regulators, constant voltage transformers, and so on. It's not my intention to make a
power supply expert out of everyone. Instead, I will outline the design of the specific
DC power supply which we will use to power the Z80 Applications Processor (ZAP).

In large computers, the DC supplies convert enormous amounts of power to run
thousands of logic chips; by necessity, manufacturers choose the most efficient
methods of power conversion. These state of the art methods would be expensive and
difficult for the hobbyist to build in prototype form. Fortunately, the power demands
for ZAP are much less than those of the large computers; we can take advantage of
established design methods while incorporating the latest advances in regulator
technology. Figure 1.1 is a block diagram of the power supply for ZAP.

Each of the three DC supplies necessary to power ZAP consists of three basic
modules: a transformer section to reduce the 120 VAC line voltage to the lower voltage
used by the computer; an input rectifier/filter to convert AC to low ripple DC; and a
regulator which stabilizes the output at a fixed voltage level. Overvoltage protection
circuitry will be discussed separately.

1 AMP 3 AMP

♦ 3 VOLTS
(o) SAMPS

CIRCUIT CNO

♦ 12 VOLTS
<a> 1 AMP

-12 VOLTS
@ 1 AMP

Figure 1.1 A block diagram of the basic power supply for the Z80 Applications Processor (ZAP).

POWER SUPPLY 1

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The proper specification of the transformer and input filter is often neglected by hob¬
byists who overlook the consequences of a poorly designed filter. This is caused, in
part, by the abundant technical information circulated by semiconductor manufac¬
turers extolling the virtues of their regulator circuits. One can easily conclude from this
"publicity gap" that the regulation section of the power supply is the only component
worthy of consideration; and in fact, advances in regulator design and the advent of
high-power, three-terminal regulators have reduced the need for the analog designer in
the application. In the past, 25-odd components and considerable calculations were
necessary to produce an adequate voltage regulator. Now, however, the majority of
applications can be accommodated with a single, compact device. Even so, an input
filter section should not be taken lightly and still requires thorough consideration and a
modest amount of computation for each application.

There are three supply voltages necessary to operate ZAP. Each supply incorporates
an input filter section. Because the +5 V supply is the most important, it receives the
most attention. For the purposes of this discussion, we will divide the supply into two
sections: transformer/input filter, and output regulator.

A standard input filter block diagram is shown in figure 1.2. In its simplest form, it
consists of three components that function as follows:

• A transformer that isolates the supply from the power line and reduces the 120 VAC
input to usable, low-voltage AC.

• A bridge rectifier that converts AC to full-wave DC and satisfies the charging cur¬
rent demands of the filter capacitor.

• A filter capacitor that maintains a sufficient level between charging cycles to satisfy
the regulator input voltage limitations.

; f

f 5 -

>/VVWv

Photo 1.1 120 VAC RMS
input/output waveform of a
saturated transformer.

Photo 1.2 Rectifier waveform.

Photo 1.3 Ripple waveform at
various loads.

TRANSFORMER

RECTIFIER CAPACITOR FILTER

DC OUTPUT
TO REGULATOR

PRIMARY INPUT VOLTAGE SURGE CURRENT

SECONDARY OUTPUT VOLTAGE CAPABILITY

CONTINUOUS CURRENT OUTPUT VOLTAGE DROP

SECONDARY IMPEDANCE CONTINUOUS CURRENT

RATING

SURGE CURRENT RATING
VOLTAGE RATING

RIPPLE voltage

Figure 1.2 A block diagram of a standard input filter.

2 POWER SUPPLY

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DESIGNING AN INPUT FILTER

You would think that specifying the transformer would be the first consideration
when designing a power supply. Yes and no. The approximate output voltage can be
determined by rule of thumb, but the exact requirements are deduced only by a
thorough analysis that proceeds from the desired output voltage back. In practice, the
difference between a reasonable guess and a laborious analysis will be important only
to a person capable of manufacturing his own transformer. In most instances, the hob¬
byist will have to rely upon readily acquired transformers with standard output
voltages. For this reason, my approach is predicated on the practical aspects of power
supply design rather than on the minute engineering details that have no real bearing
on the outcome.

A 120 VAC RMS (root mean square) sine wave is applied to the primary of the
transformer. Figure 1.2 illustrates the waveforms anticipated at selected points through
the filter section. Photo 1.1 shows that 120 VAC is actually 340 V peak to peak; care
should be used in the insulation and mounting of components.

The secondary output of the transformer will be a similar sine wave, reduced in
voltage. It is then applied to a full-wave bridge and the waveform will appear as in
photo 1.2. You'll notice a slight flat spot between "humps." As a result of dealing with
actual electronic components rather than mathematical models, we should be aware of
certain peculiarities. Silicon diodes exhibit threshold characteristics and, in fact, have a
voltage drop of approximately 1 V across each diode. This voltage drop becomes
significant in full-wave bridge designs and, as figures 1.3a, 1.3b, and photo 1.2 il¬
lustrate, can accumulate as diodes are added in series. The 2 V loss in the bridge is an
important consideration and should be reflected in the calculations.

The voltage regulator requires a certain minimum DC level to maintain a constant
output voltage. Should the applied voltage dip below this point, output stability is

Figure 1.3 The direction of the current flow through the full-wave bridge.

a) During the positive half of the AC cycle, current flov/ is through D, and 0 3 ; D 2 and 0 4
are not conducting. V Dl + V D3 ~ 2 volts.

b) During the negative half of the AC cycle, current flow is through D, and D 4 ; D, and D,
are not conducting. V D2 + Vo* »* 2 volts.

POWER SUPPLY 3

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severely degraded. Thus, a filter capacitor is used to smooth out the "humps" in the
rectified sine wave. When the diodes are conducting, the capacitor stores enough charge
to maintain the minimum voltage required until the next charge cycle. (In practice, we
wouldn't want to cut it that close.) The input to the transformer is 60 Hz, but because
of the characteristics of full-wave rectification, the charging cycles occur at 120 Hz.
The capacitor charges up during one 8.3 ms cycle, and, as the regulator draws power
from it to satisfy the load demands, it must continue to provide at least the highest
minimum input voltage required by the regulator until the next charge cycle, 8.3 ms
later. This periodic charge/discharge phenomenon is shown in photo 1.3. The
magnitude of the voltage fluctuation between the two peaks of the cycle is referred to
as ripple. The highest magnitude of the waveform including the ripple is designated as
peak voltage. Both are important to remember and are shown in figure 1.4.

v FEAK rV R|PPLE 4 ’ V C

Figure 1.4 Output voltage as a combination of a certain steady-state voltage (V c ) plus a ripple voltage

(Vumm)-

Given a basic understanding of the individual components at this stage, we can pro¬
ceed to the case at hand: a 5 V, 5 A power supply. For reasons we'll discuss later, the
5 V regulator section of this supply will require an absolute minimum of 8.5 V for
proper operation. This means that whatever the magnitude of V PEAK and V ripple, the
final V c level must not go below 8.5 V, or the regulator will not work. By giving
ourselves some leeway, say V c — 10 V, we can take a little more poetic license with
the calculations and still produce a good design. Going much above 10 V, while still
satisfying the input criteria, would increase power dissipation and possibly destroy the
regulator. There is an answer to this vicious circle and that's to be conservative. Ex¬
perience shows that adding a little insurance is worthwhile.

Now that 10 V is the goal, we can appropriately select the other filter components to
meet it. Figure 1.5 is the filter circuit of our 5 V supply. R s is the resistance of the sec¬
ondary winding of the transformer. For a 5 to 8 A transformer, it will average about x
0.1 ohms. The first values to recognize follow:

Vc — V REGULATOR MINIMUM INPUT VOLTAGE — 10 V
I out = Ireculator LOAD = 5 A

Rj = ^TRANSFORMER SECONDARY RESISTANCE = 0.1 ohmS

Vpeak can be any voltage up to the maximum input for which the regulator is rated.
However, this will increase the circuit power dissipation. The rule of thumb I use when
designing supplies of this type is that V PEAK should be approximately 25% higher than
V c . In this way, the capacitor value will be kept within reasonable limits. The ratio of
V c to (Speak “ V c ) is referred to as the ripple factor of the filter capacitor.

25%

A ripple factor of 25% at 5 A will fall well within the acceptable capacitor ripple cur¬
rent ratings and eliminate the need for the hobbyist to dig into manufacturers' specifi¬
cations of capacitors. This ripple factor is arbitrary, but it is best to keep it as low as
possible.

4 POWER SUPPLY

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Figure 1.5 The input filter circuit of the 5 V power supply.

SIZING THE CAPACITOR

We now know that the capacitor must sustain 10 V from a peak input of 12.5 V.

V«*r

V RIPPLE

12.5 V
10 V

2.5 V

Vc “ VPC A K V ftIPPLC

The next consideration is to choose a capacitor that will accomplish this goal. Another
rule of thumb calculation that saves considerable labor is

where

C = capacitor value in farads = 7
I = maximum regulator current = 5 A
dt = charging time of capacitor ■» 8.3 ms (120 Hz)
dv = allowable ripple voltage = 2.5 V

Plugging in the values of our circuit,

r _ (5)(8.3 X10°)

(2.5)

16.6X10"’ farads

C = 16,600 microfarads (/iF)

Generally available commercial electrolytic capacitors have a tolerance of +50 and
—20%. To be on the safe side and to make it easier to find a standard stock compo¬
nent, a value of 20,000 /iF is better. The added 3,400 n? reduces the ripple by another
0.4 V and gives us a little "insurance/' The only other item to consider with the capaci¬
tor is operating voltage. Because the design dictates that Vtcak is 12.5 V, this should
be a satisfactory rating. However, experience shows that transformers end up running
at higher output voltages than labeled and that 12.5 V at 115 VAC hits 13.6 V when
the line voltage goes up to 125 VAC. A capacitor voltage of 15 VDC would appear to
satisfy the requirement, but I recommend using the next increased standard value of
20 VDC.

The capacitor is therefore 20,000 /*F at 20 VDC. The rectifier can be a monolithic
hill-wave bridge, or it can be four discrete diodes. Note that because a bridge is usual¬
ly encapsulated, the four terminals are labeled instead of showing the polarity mark¬
ings of the individual diodes. The designations for the four terminals are two AC input
terminals, and a + and — output terminal.

POWER SUPPLY 5

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THE RECTIFIER

There are three considerations when choosing a rectifier: surge current rating, con¬
tinuous current, and PIV (peak inverse voltage) rating. These choices are not inconse¬
quential and must be considered carefully.

When a power supply is first turned on, the capacitor is totally discharged. In fact, it
will instantaneously appear to be a 0 ohm impedance to the voltage source. The only
aspect of the circuit that limits the initial current flow is the resistance of the secondary
transformer windings and the connecting wiring; designers often add a series resistance
to limit surge current.

The surge current in this circuit is

URGE

Vrr.AK _ 12.5

Ks " 0.1

125 A

and the time constant of the capacitor is

T = Rj X C = (0.1X20X10°) “2 ms

As a rule of thumb, the surge current will cause no damage to the diode if I$(/* C e is less
than the surge current rating of the diode and if

7 < 8.3 ms (which it is)

We can't check surge rating until after we choose a diode bridge, but the other two
parameters can be defined.

The bridge can be either of the following:

Motorola MDA 980-2: Ico/vr = 12 A, \svrge * 300 A, PIV = 100 V
Motorola MDA 990-2: Icwr - 27 A, I WHG£ = 300 A, PIV = 100 V

Both of the above bridges have a surge current rating of 300 A, so our surge require
ment is also satisfied.

PIV

PIV (peak inverse voltage) is the maximum voltage that may appear across the diode
before it self-destructs. Diodes, unlike capacitors, are unforgiving; transients will wipe
them out. It is not unusual to have 400 V transients on the 115 VAC input line. This
causes our 12.5 V to shoot up momentarily to 43 V! The bridge rectifier should there¬
fore have a minimum PIV rating of 50 V. For a few pennies more, you can get a bridge
rated for 100 PIV. Remember, insurance costs less than computers.

CONTINUOUS CURRENT

The last consideration is continuous current rating. Whereas the regulator may be
designed for a 5 A output, the particular regulator I have chosen will draw 7 A if
shorted. This is not standard operating procedure, but it can happen. The suggested
standard component would be a 12 A, 50 PIV bridge. A preferred component would be
one rated for 12 A at 100 PIV or, for an additional 15% cost premium, a 27 A at 100
PIV. This last design choice is strictly brute force, but it saves the diode bridge should
the capacitor ever short-out accidentally. A 6 A transformer might put out more than
12 A in a short-circuit mode, but it's unlikely that it would be capable of 27 A. Either
choice will satisfy the design, but only one saves the design from the builder.

THE TRANSFORMER

Now let's consider the transformer. We have determined the voltage drops across the
various components. The values are used to calculate the required RMS (root mean

6 POWER SUPPLY

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square) secondary voltage in the following way:

\T _ ^ c Cripple + v RCCT

VSECiRMS) — VrECT

= 10 + 2.5 + 2.0
1.414

Voltage drop across each diode—
(approximately 1 V per diode)

= 10.25 V

In practice, a 10 V, 6 A standard value transformer will be close enough.

The components of the + and —12 V supplies are chosen in a similar manner, with
the exception that required current is only 1 A, and a 200 PIV bridge is recommended
because of the particular rectifier configuration. The finished schematic of the trans¬
former and filter section of our computer is illustrated in figure 1.6.

MDA990-2

V C • 10 VOLTS
VRIPPLE *2 3VOLTS

°GROUND

V C • 15 VOLTS
VRIPPLE* 4 VOLTS

V C*-15V0LTS

VRIPPLE '-4V0LTS

Figure 1.6 A schematic diagram of a transformer and input filter section.

VOLTAGE REGULATORS

The voltage regulator section of our power supply is the next consideration. All
voltage regulators perform the same task: they convert a given DC input voltage into a
specific, stable DC output voltage and maintain this setpoint over wide variations of
input voltage and Output load. The typical voltage regulator, as shown in figure 1.7,
consists of the following:

• a reference element that provides a known stable reference voltage

• a voltage translation element that samples the output voltage level

• a comparator element that compares the reference and output level to produce an
error signal

• a control element that can utilize this error signal to provide translation of the input
voltage to produce the desired output

The control element depends on the design of the regulator and varies widely. The
control determines the classification of the voltage regulator: series, shunt, or switch-

POWER SUPPLY 7

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ing. For the series regulator, the control element regulates the output voltage by
modulating the series element, usually a transistor, and causes it to act as a variable
resistor (figure 1.8). As the input voltage increases, the series resistance R s also in¬
creases, causing a larger voltage drop across it. In this way, the output voltage (Vovr) is
maintained at a constant level.

REGULATED

OUTPUT

VOLTAGE

Figure 1.7 A block diagram of a typical voltage regulator.

IN*

^y<£

LOAD

VOUT

v OUT

V OUT * V IN-(l«s )(, LOAo0

v OUT « V IN -V C £

WHERE VcE . (IlOAO) Rs

Figure 1.8 A series control element in the voltage regulator.

a) The series control element acts as a variable resistance, R s .

b) The series element is most often a transistor.

To accomplish this closed-loop control, a reference comparison and feedback system
is incorporated into the hardware. A fixed and stabilized reference voltage is easily pro¬
duced by a zener diode. The current produced is low, however; the device could not
serve as a power regulator by itself.

The voltage translator connected to the output of the series control element produces
a feedback signal that is proportional to the output voltage. In its simplest form, the
voltage translator is a resistor-divider network. The two signals, reference and feed¬
back, provide the necessary information to the voltage comparator for closed loop
feedback to occur (figure 1.9). The output of the comparator effectively drives the base
of the series pass transistor so that the voltage drop across the transistor will be main¬
tained at a stabilized preset value when subtracted from the input voltage.

Modem power supply designers can still use individual components to construct the
modular elements of a series voltage regulator, but most reserve this laborious
endeavor for specialized applications. The ZAP computer system outlined here re¬
quires +5 V, +12 V, and —12 V. The combined temperature, stability, and drift

8 POWER SUPPLY

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tolerances cannot exceeu ±5% on any of the three set points. The easiest way to
minimize risk is to reduce the number of circuit components to the bare minimum.
Other designers had the same idea and thus the three-terminal regulator was invented.
Figure 1.10 is the block diagram of such a device.

VQUT •!♦( ^)<VR£F>

VOUT *V|N-VCE
AND

V CE 'IlOAOCRsI
v 0UT * V IN “(iLOAO IRS*)

THIS IF TOO THINK OF IT AS A TRANSISTOR

THIS IF YOU THINK OF IT AS A SERIES
RESISTANCE

Figure 1.9 A schematic diagram of a series voltage regulator.

GR0UN0

Figure 1.10 A block diagram of a three-terminal voltage regulator.

Basically, a three-terminal regulator incorporates all the individual transistors,
resistors, and diodes into a single integrated circuit. While simple to use, these devices
have a far more complicated internal structure than the series regulator of figure 1.9.
Only three terminals are necessary in applications where the fixed output is a standard
value such as: ±5 V, ±6 V, ±8 V, ±12 V, ±15 V or ±24 V. The three connections
are unregulated DC from our input filter, a ground reference, and finally, regulated DC
output.

POWER SUPPLY 9

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In a three-terminal regulator, the voltage reference is the most important part
because any abnormality or perturbation will be reflected in the output. Therefore, the
reference must be stable and free from noise or drift. More advanced designs use band-
gap reference circuits rather than zener diodes. Because of its complexity, such an ap¬
proach is practical only in the integrated circuit (IC) environment. Essentially, a band-
gap reference voltage is derived from the predictable temperature, current, and voltage
relationships of a transistor base-emitter junction.

Another advantage of the three-terminal regulator is that in monolithic circuits,
stable current sources can easily be realized by taking advantage of the good matching
and tracking capability of monolithic components. Also, as in the previous case, the
designer can add as many active devices as necessary without significantly increasing
the IC circuit area. Operation of the reference circuit at a constant current level reduces
fluctuations due to line-voltage variation. Thus, the output has increased stability. The
error amplifier is also operated at a constant current to reduce line-voltage influence.

The most important consideration for the hobbyist is that these chips incorporate
protective circuitry, guarding the regulator from certain types of overloads. They pro¬
tect the regulator against short-circuit conditions (current limit); excessive input/out¬
put differential condition (safe operating area); and excessive junction temperatures
(thermal limit). Of course, all this circuitry is designed to protect the regulator, not the

computer.

CHOOSING A REGULATOR

The 5 A /*A78H05 hybrid voltage regulator has all the inherent characteristics of the
monolithic three-terminal regulator (ie: full protective circuitry). Each hermetically-
sealed TO-3 package contains a /iA78M05 monolithic regulator chip driving a discrete
series-pass transistor Ql and two short-circuit-detection transistors Q2 and Q3 (see
figure 1.11). The pass transistor is mounted on the same beryllium oxide substrate as
the regulator chip, thus insuring nearly ideal thermal transfer between Ql and the tem¬
perature-sensing circuit of the 78M05.

10 POWER SUPPLY

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ELECTRICAL CHARACTERISTICS: Tj • 25°C. IquT " 2 0 A unlett ottiervro* specified.

CONDITIONS

PA78M05C

1 liJfTC

UnAtmL I tnlillUi

MtN

TVP

MAX

UNITS

Output Vo*t*g*

•OUT - 2O A. V, M * tOV

4 6

5.2

Regulation

V,* » 8 5 lo 25 V

lo*d ReQul#t«oo

10 mA < «qut < 5.0 A V| N = 10 V

Qv*ictrnt Cuff*nt

•OUT *■ 0. V|* - VouT ♦ 5 0 V

R-C©v Reaction

•OUT 1 -O A. f « 210 Hi. 5 0 V P-P

Output Noivo

10 H/ < 1 « TOO kHl. V| N • Vour ♦ 5 0 V

PVrMS

Dfopoul Voft«0*

•O* 50A

•O* 30A

S*>o«l Circuit Currcni Lim*

V,n -10 V

Figure 1.12 Electrical characteristics of the nA78H05 voltage regulator.

The output circuit is designed so that the worst-case current requirement of the Ql
base, added to the current through R2, always remains below the current-limit thresh¬
old of the 78M05. Resistor Rl, in conjunction with Q2 and Q3, makes up a current
sense and limit circuit to protect the series-pass device from excessive current drain.

Safe area protection is achieved by brute force and is designed with the hobbyist in
mind. The series-pass transistor is capable of handling the short-circuit current at the
maximum input voltage rating of the 78H05. (See figure 1.12 for the electrical charac¬
teristics of the 78H05.)

The output of the device is nominally 5.0 V but can vary between 4.8 and 5.2 V. Even
though this falls within the 5.0 V ±15% tolerance necessary to run the computer, there
might be a problem with the voltage drop in the cabling between the power supply and
the computer. Up to 0.5 V could be lost in the wiring and connectors. Remember that
at 5 A, a resistance of only 0.1 ohms can cause a 0.5 V drop. Unfortunately, the 78H05
is a fixed-output device when referenced to ground. If 4.8 V happens to come out,
"that's all you gets" (sic). But, in a classic case of engineering razzle-dazzle, we can fool
the regulator by making the ground reference adjustable. Figure 1.13 shows the circuit
that makes this possible. A potentiometer sourced from the —12 V supply creates a
relative-ground reference for the 78H05. If the particular device in question had an out¬
put of 4.95 V, and we adjusted Rl for a potential of 0.20 V on the common regulator
pin, the output referenced to ground would change to 4.95 + 0.20, or 5.15 V. For the
fanatics in the crowd, this particular circuit also allows a high-output device to be
reduced to 5.00 V by selecting an appropriate negative voltage ground reference pin.

v INPl>T °-
10V

OND°-

OUT

33 V

SOLID

TANTALUM

p A78H03KC
COMMON

\?oci

-wv

^OUTPUT
♦SVt3%

10j» F

10 V

FROM 12V
REGULATED OUTPUT

Figure 1.13 Adding "trim adjust" to the nA78H05 three-terminal voltage regulator.

POWER SUPPLY 11

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With the 5 V supply complete, our next concern is the +12 V and —12 V supplies.
Other devices within the 7800 family of regulators will satisfy the requirements. The
7812 and a 7912 are 1 A positive and negative regulators respectively; they exhibit the
same protection characteristics as the 78H05. Figures 1.14 and 1.15 outline the exact
specifications. Because we are dealing with much lower currents than the +5 V supply,
there is considerably less concern over voltage losses through connecting cables, and it
is unnecessary to add trim adjustment circuitry. Figure 1.16 is the finished schematic of
the ZAP power supply. Additional regulator circuit diagrams (figures 1.17a, b, c and
d) are included to demonstrate how the 7800 series of regulators can be used in our ap¬
plication. Are we finished yet? Of course not. Close examination of figure 1.16 shows
two items not discussed previously: heat sinks and overvoltage protection. These two
subjects and a short discussion of the importance of correct layout complete the
chapter.

jiA7812

ELECTRICAL CHARACTERISTICS: V, N - 19 V. Iqut - 500 mA. -55* C < Tj < 1S0*C. C|N • 043 *F. CouT * 0.1 .

unltSI other**** fpttlf’td.

CHARACTERISTICS

CONDITIONS

MIN

TYR

MAX

UNITS

Output Voltage

Tj * 25*C

ii4

120

12.5

Line Regulation

Tj - 25*C

145V <V )N < 30V

120

16 V < V| N <22V

Load Regulation

Tj - 25* C

5mA< *OUT < I SA

120

250 mA < loot < 750 mA

Output Voltage

15.5 V < V|n < 27 V

5 mA < l 0 UT < 1 JO A

K 15 W

114

124

Ou*ic«nt Current

Tj - 25*C

Orescent Current Ch***?*

with i»rte

15 V« V| W <30 V

with load

5 mA < touT < 10 A

0.5

Output None Vo'tege

T A -75*C. 10M*<I< 100 hHi

uWVouT

R'po't Rejection

»-120HM5V<V, N <25V

Dropout VoJt* 9 *

•OUT- 1.0 A. Tj * 25*C

2.8

Output Renstence

f • 1 kMt

mfl

Short Circuit Current

Tj • 25*C. V, N - 35 V

0.75

Reek Output Currant

Tj - 25*C

1.3

3-3

Average Temperature Coefficient of Output V of tape

'OUT -5 mA

-55*C < Tj < *25* C

0.4

mWC/

vqut

♦25*C<Tj<4l50rC

0.3

Figure 1.14 Electrical characteristics of the nA7812 voltage regulator.

MA7912

ELECTRICAL CHARACTERISTICS: V, N • -19 V. I 0 UT • "A. C, M • 2t.f.CouT • 1**. -S5*C < T j < 150*C. «IM OttwerfM

Ipeof.ed,

CHARACTERISTICS

CONDITIONS

MIN

TVR

MAX

UNITS

Output Voltage

Tj - 2S*C

-11 5

-12 0

-12.6

Tj • 25*C

—14.5 V < V|ej < —30 V

120

-16 V< V lN <-22 V

toed Reputation

Tj - 25*C

6mA<l 0 UT< 1A A

120

750 mA < l 0uT < 750 mA

Output Voltage

-155V<V tN <-27V

5 mA < tom < 1.0 A
p< 15W

-114

-12.6

Ou<e«cent Current

Tj ■ 25* C

1.5

3.0

- . _ w»th line

-15V«V in <-30V

1 JO

with toed

6 mA < IquT < 1 0 A

Output None Vottege

T A • 25*C. 10 He < 1 < 100 kHe

av/v 0uT

Ripple Rejection

« - 120 He. -15 V < Vim < -25 V

Dropout Vottege

•OUT * 1.0 A, Tj » 25*C

i.i

Nek Output Current

Tj • 25*C

2.1

3.3

Amrege Temper at ixe Coefficient of

Output Vottege

lOUT « 5 mA. -55*C < Tj < 160*C

mV/*C/

v 0UT

Short Circuit Current

V, N --35V.Tj-2S*C

Figure 1.15 Electrical characteristics of the nA7912 voltage regulator.

12 POWER SUPPLY

Copyrighted material

MDA990-2

* THE ruS£ IS ATTACHED TO THE REGULATOR IM*UT ANO OCTaEEN THE FILTER CAPACITOR AMO
OIOOC 8RIOCC

Figure 1.16 A schematic diagram of the finished power supply for the ZAP computer.

2N4396

VBEI2N6124)

R SC

Figure 1.17 Additional voltage regulator circuit
diagrams to demonstrate how the 7800 series of
regulators can be used.

a) A high-current voltage regulator us¬
ing a 500 mA 7QM05 three-terminal
regulator.

b) A high-current short-circuit pro¬
tected voltage regulator, an en¬
hanced version of figure 1.17a.

c) Using a 7805 + 5 V voltage reg¬
ulator to produce a higher output
voltage.

d) A dual ±12 V tracking voltage reg¬
ulator.

POWER SUPPLY 13

Copyrighted material

LAYOUT IS IMPORTANT

Integrated circuit regulators employ wide-band transistors in their construction to
optimize response. As a result, they must be properly compensated to ensure stable
closed-loop operation. Their compensation can be upset by stray capacitance and line
inductance of an improper layout. Circuit lead lengths should be held to a minimum,
and external bypass capacitors in particular should be located as close as possible to the
regulator control circuit.

Figure 1.18a illustrates a typical layout of the components of our supply, and figure
1.18b details the areas that can cause problems. Improper placement of the input ca¬
pacitor can induce unwanted ripple on the output voltage. This occurs when the current
flowing in the input circuit influences the common ground line of the regulator. The
voltage drop produced across R2' will cause the output of the regulator to fluctuate in
the same manner as the voltage trim circuit we discussed previously. The peak currents
in the input circuit (which consists of the rectifier and filter capacitor) can be tens of
amperes during charge cycles. These high-current spikes can cause substantial voltage
drops on long-lead lengths or thin-wire connections. They can also degrade perfor¬
mance to the point that proper input voltage to the regulator cannot be maintained ex¬
cept during low-current operation.

The output current loop is also susceptible to circuit layout. In a three-terminal
regulator, the fixed-output voltage Vout(keg) is referenced between "out" and "com¬
mon" of the chip. Because the load current flows through R2', R3', and R4', as well as
the load itself, these combined voltage losses may reduce Vout to an intolerable level.
Notice that the ground for this circuit is at point C while the present R load is between
points A and B. If another load, more memory for example, is connected to this supply
between points A and C, it would have a different V ot rr. Adjusting the trim setting of
such a seesaw supply can be dangerous; it's possible to have one load completely
within tolerance and another over or under voltage. One last point to consider is that
R4' serves to negate the purpose of the regulator because it continually reduces Vout as
the load current increases.

TRANSFORMER RECTIFIER REGULATOR

Figure 1.18 A typical layout of the power supply components and associated problems.

a) A typical layout.

b) Errors contributed by the layout in figure 1.16a.

14 POWER SUPPLY

Copyrighted material

Figure 1.19 is the block diagram of a proper layout. All high-current paths should
use heavy wire to minimize resistance and resultant voltage drops. You'll notice now
that the input and output circuit current paths are separated effectively. Note that the
wires from the rectifier go directly to the capacitor and that two wires from the capaci¬
tor send power to the rest of the circuit. If you follow this convention and use two
separate pairs of leads, you can eliminate input-circuit induced errors.

Finally, we need to discuss the concept of the single-point ground. One point in the
power supply must be designated as ground; the grounds of all other supplies and loads
are connected to it. In practical terms, the best way to implement this ground connec¬
tion is to use a metal strip or several lengths of heavy wire soldered together. The strip
is a ground bus with such a low resistance that a voltage measured between point A
and any place along the bus will be virtually undetectable. Another +5 V bus should
be connected to the output of the supply so that voltage distribution throughout the
circuit is consistent. Use thick wire in power supplies. Even if zero-resistance wire isn't
easily obtainable, always remember—there is no such thing as wire that is too thick!

TRANSFORMER RECTIFIER REGULATOR

Figure 1.19 A block diagram of a proper layout for the pov/er supply components.

THERMAL CONSIDERATIONS

You've just built the power supply I've outlined, flipped on the power, and every¬
thing works. After a few minutes, something happens and the computer suddenly stops
running. Naturally, you start looking around and touching things. Eventually, your
fingers will end up on the regulator chip. Immediately you scream, jump back, and in
the process knock over the computer and your celebration martini. If you are lucky,
your fingers will be the only thing burned!

When not properly cooled, the regulators will protect themselves from destruction
by reducing their output or completely shutting off. In this case, the system could cease
to function. A more catastrophic problem arises from ICs that use all three voltages for
normal operation. Loss of one or more of these voltages could permanently damage the
device. This will never happen if power dissipation is limited and the proper cooling
methods are employed.

The first step is to check the power dissipation of our design with the ratings of the
particular devices. In practical terms, power, expressed in watts, is volts times
amperes:

P D = E X I

In our 5 V regulator we have V c — 10 V and V PEAK = 12.5 V at 5 A.

POWER SUPPLY 15

Copyrighted material

D{KOM)

D{PEAK)

D(AVERAGE)

(Vc — Voin - ) X 5 A
(10 - 5) X 5
25 W

(Vpeak Votrr) X 5 A

(12.5-5) X 5

37.5 W
37.5 ± 25
2

31.25 W

This means that under full load conditions, about 30 W of heat will be produced by the
78H05. The device is fortunately rated for 50 W at 25 °C and is still capable of handling
30 W up to 75 °C.

Although the internal power dissipation is limited, the junction temperature must be
kept below the maximum specified temperature (125 °C) in order for the device to func¬
tion at all. To calculate the heat sink required, there are specific equations to solve.

The required thermal data and calculations follow:

DlMAX)

Typical 0 JC — 2.0
Typical 0 JA = 32

Tj(MAX) T a

Ojc + 6

Maximum 0 JC
Maximum 0 JA

2.5

for 0,

Ocs + 0

Solving for Ty.

Ty — T* + P d(0jc “b Oca)

or without a heat sink.

D{MAX)

JIM AX)

- T

0 .

Ty = T A “b P dOja

where Ty =

junction temperature
ambient temperature
power dissipation
junction to case thermal resistance
junction to ambient thermal resistance
case to ambient thermal resistance
case to heat sink thermal resistance
heat sink to ambient thermal resistance

125 °C - 25 °C
31.25 W

3.2°C/W

Because $ JA as calculated is less than $ JA from the specification sheet, a heat sink is
definitely required, and a TO-3 type heat sink of 3.2°C/W is the minimum desired.

Before you size a heat sink for the 78H05, realize that there are two more regulators
and two bridge rectifiers that will need heat sinking. Each 12 V regulator will average
about 5 W dissipation. The diode bridge associated with the + 5 V supply (remember
the 2 V drop) dissipates about 10 W while the other is good for 2 W. Therefore, any
heat sinks in the power supply must handle more than 50 W.

WHAT IS THE PRACTICAL METHOD FOR CHOOSING HEAT SINKS?

Choosing a heat sink can be easy or hard depending upon your outlook on rule of

16 POWER SUPPLY

Copyrighted material

thumb measures. We already know that we need a 50 W heat sink. It's easy to assume
that buying one "rated for 50 W" from a local electronics supply will solve the prob¬
lem. What this rating usually means, however, is that if 50 W is applied through a tran¬
sistor to this sink, and the ambient temperature is 25 °C, the surface temperature of the
sink will climb to 100 °C. Fried eggs anyone?

We must not forget that manufacturers' specs always refer to limiting maximum
junction temperature, not to keeping the case cool enough to touch. Personally, I hate
red-hot power supplies. To get a heat sink that would take our 50 W and stay about
60-70 °C would probably mean getting one rated for 200-300 W! Remember that heat
sinks are expensive—-and big.

The simplest solution is best. I prefer forced air cooling. Put the 50 W on an
economical heat sink of, say, a 100 W rating and put your money into a good fan. You
can still run through all the calculations and determine how many square inches you
need, but the effect of blowing a little air ov^r a heat sink multiplies its capabilities
enormously.

OVERVOLTAGE PROTECTION

The final area to be addressed in the power supply is overvoltage protection. As
designed by manufacturers, regulators protect themselves by reducing output voltage
or complete shutoff. The chances of computer component damage from low voltage is
miniscule by comparison to overvoltage. It is unlikely to happen, but if the 78H05 were
to accidentally short out, as much as 12.5 V would be applied to the +5 V bus. You
could then kiss the computer good-bye I

_ + 5 volt OVP _ _ 12 volt OVP _

D, 5.6V 1N4734 D, 13V 1N4743

SCR, 50V 25A 2N682 SCR, 50V 8A 2N4441

Fuse 6amp fast-blow Fuse l.Samp fast-blow

The semiconductor components of this
12 volt OVP are reversed in polarity
for the —12 volt OVP.

OVP

REGULATOR

OUTPUT

COMPUTER

BUS

Figure 1.20 A simple overvoltage protection circuit.

The circuit of figure 1.20 is a simple OVP (over-voltage protector). It can be used as
shown on the 5 V and 12 V supplies. The appropriate components are listed in the
tables of figure 1.20. You'll notice that the fuses are rated higher than the output we've
previously discussed. The fuse is for the OVP and not to protect the regulators. Unfor¬
tunately, the nature of fast-blow fuses is not to pass 5 A, if it is a 5 A fuse, but to open
at 5 A. The fuse must have a higher rating in order to allow circuit operation at 5 A.

Figure 1.21 A schematic diagram of a more complex overvoltage protection circuit. The crowbar sec¬
tion of the OVP can be located next to the fuse while the OVP sensor Z, is located at the regulator out¬
put. This is a preferred placement of the parts if the sensor and clamp can be adequately separated.
Low-current sensor Z, fires SC/?, in an overvoltage condition. SCR t in turn fires high-current SCR* The
combination of SCRs allows considerable leeway in the choice of SCR 2 since the question of gate cur¬
rent becomes less relevant.

Because the short-circuit current of the 78H05 is 7 A, the 25 A silicon-controlled rec¬
tifier (SCR) will certainly make short work of the fuse if it triggers. Figures 1.21 and
1.22 are slightly more complex OVP circuits and can also be used.

fROM

TO LOAD

GND

Figure 1.22 Schematic diagrams of adjustable-voltage overvoltage protection circuits.

a) An adjustable-voltage OVP circuit with an internal current amplifier to drive the SCR gate.

b) An alternate circuit for a simple adjustable-voltage OVP circuit.

18 POWER SUPPLY

Copyrighted material

What does an OVP (often called an "overvoltage crowbar") do? It monitors a par¬
ticular bus voltage and shuts it down if it goes above a predetermined level. OVP cir¬
cuits can be designed to trigger 1 mV above our 5% tolerance band. Such circuits are
not only complicated, but they may also create additional problems through accidental
triggerings. The failure modes that are most likely to occur concern a regulator short or
accidentally tying two buses together, for example the +5 V and +12 V. In either
case, the result is a rapid voltage rise on the output lines. As voltage rises above the

zener value, current flows into the SCR gate. At a certain point, usually below where
any components would have been damaged, the SCR fires and shorts the output line to
ground. The excessive current blows the fuse, eliminating the problem regulator or
regulators (both fuses would blow if the +5 V and +12 V were connected). All this
occurs very fast. The test circuit of figure 1.23 demonstrates what happens when the
+ 5 V OVP suddenly has +12 V applied. Test circuits are the only way you ever want
to see the action of an OVP. If your power supply functions properly, it should never
trigger. The SCR never allows the line to go to 12 V before clamping it to ground. Re¬
placing the fuse with a 220 ohm resistor allows multiple applications of the push button
without replacing fuses.

♦12V

1 mi/cm

Figure 1.23 A test circuit to demonstrate the action of the overvoltage protector.

POWER SUPPLY 19

Copyrighted material

CHAPTER 2

CENTRAL PROCESSOR
BASICS

There are many different microprocessors on the market and while instruction
nomenclature is somewhat different for each one, the basic logical computing processes
are similar in all devices. The rule to remember the next time a discussion turns to the
capabilities of two computers is that "a computer is a computer/' I don't wish to imply
that they are all the same, but similarities abound and 1 would not like to spend a life¬
time analyzing instruction sets and interfacing details before choosing one.

I once had lunch with the designer of one of the largest selling personal computer sys¬
tems on the market. Thousands of computers had been sold, generating immense prof¬
its for the manufacturer. Our conversation eventually centered on the cost-effective¬
ness of his design. I had fanciful thoughts of a design team spending months reducing

component count and analyzing instruction sets to determine minimum memory re¬
quirements. In actuality, my designer friend was given two months to come up with a
manufacturable design. The investors' only question was the price and availability of
the particular components he had chosen. Being an avid personal computer enthusiast,
he simply built a computer around the microprocessor he already owned. The eventual
advertising for his system touted the advanced architecture embodied in the central
processor, but no machine-language programming facility was available to the user. It
had only a high-level language BASIC interpreter and was, from an engineering point
of view, simply a black-box computer. He could have used any microprocessor. So
much for textbook engineering design.

Unfortunately, the hobbyist who is building a microcomputer from scratch, and
who won't be making a black box, has to try to pick a device that is somewhere in the
middle of the performance and capability spectrum. The general rule that all computers
perform similar functions is true, but a printed-circuit board is a luxury. The hobbyist

who has to do all the wiring by hand will surely be interested in efficient design. It's a
fact that some of the more esoteric microprocessors require very expensive peripheral
circuitry. Even devices that seem quite straightforward, with limited instruction sets,
can require 50 or more ICs as interface elements. The ultimate configuration should be
a trade-off between circuit complexity, ease of testing, and component price.

MICROPROCESSOR ARCHITECTURE

The internal architecture of the microprocessor determines the support devices re¬
quired to make a microcomputer system. Perhaps the best place to start is to briefly
discuss the major architectural differences.

Definition: A microcomputer is a logical machine that manipulates binary numbers
(data) and processes this information by following an organized sequence of program
steps referred to as instructions.

All microcomputers, like all computers, have the following features:

1. Input — Facilities must exist to allow the entrance of data or instructions.

2. Memory — The program sequence must be stored before and after execution, and
resources must be available to store the result of any computations.

3. Arithmetic logic unit — Performs arithmetic operations on input or stored data.

CENTRAL PROCESSOR BASICS 21

Copyrighted material

4. Control section — Makes decisions regarding program flow and process control
based on internal states of the results of arithmetic computations.

5. Output — The results are delivered to the user or stored in an appropriate
medium.

The microprocessor is the single integrated circuit around which a microcomputer is
constructed. The microprocessor is a device; the microcomputer is a system. In their
least complex form, microprocessors include only the functions of items three and four
and must rely on external devices attached to buses to perform the other tasks. Figure
2.1 is the basic block diagram of an 8-bit microcomputer and shows the interconnec¬
tion of these buses and support elements. The computer in figure 2.1 uses six separate
buses: memory address, memory data in and out, I/O address, and data input and out¬
put. The microprocessor contains a central processor that consists of the circuitry re¬
quired to access the appropriate memory and I/O locations and interpret the resulting
instructions that are also executed in this unit. The central processor also contains the
ALU (Arithmetic and Logic Unit), which is a combination network that performs arith¬
metic and logical operations on the data. Additionally, the central processor includes a
control section that governs the operations of the computer, and the various data
registers used for manipulation and storage of data and instructions.

MICROPROCESSOR

MEMORY DATA REGISTER

MEMORY ADDRESS REGISTER

ARITHMETIC/LOGIC UNIT

ACCUMULATOR

OATA OUT
18 )

MEMORY
DATA OUT (8)

MEMORY OATA IN (8)

MEMORY ADDRESS
( 16 )

MEMORY

I/O

ADORESS

( 8 )

OUTPUT

DATA IN
( 8 )

INPUT

Figure 2.1 A basic block diagram of a microcomputer illustrating the data busing concept. Numbers
in parentheses are the usual required quantity of physical wires to perform bus functions for an 8-bit
microprocessor .

Actually few microprocessors support six separate buses. The number of pins that
would be required on the IC is out of the question. Instead, to reduce pinouts, compo¬
nent manufacturers often combine the data input and output buses and make them "bi¬
directional/' During an output instruction, data flows from the microprocessor to the
output device and vice versa during an input instruction. To further cut the number of
pins required on the central processor, the memory address bus can also serve as the
address bus for input and output devices. During input/output instructions, the ad¬
dress present on the address lines references a particular input/output device(s). The
resulting reduced configuration is shown in figure 2.2.

The concept of two buses is easy to understand and, from a hardware point of view,
easy to utilize. The buses are time and function multiplexed. That is, during memory
operations, the bits on the address bus refer to a memory location, and data on the data
bus represent the content of memory. The direction of the data flow (to or from the
central processor) is controlled within the microprocessor. Activities with input/out¬
put devices are performed in a similar fashion. During those instructions, input or out¬
put data and device addresses occupy the buses.

22 CENTRAL PROCESSOR BASICS

Copyrighted material

ADDRESS

BUS

(16)

Figure 2.2 A block diagram of a microcomputer utilizing multiplexed bi directional busing techniques
to reduce pinout.

The number of bus wires can be further reduced by combining both data and address
on the same lines and time multiplexing the data transfer along them. Figure 2.3 il¬
lustrates this final configuration. This method requires additional circuit elements to
demultiplex and store pertinent data. The additional external components necessary to
use this architectural feature defeat its purpose and make its use inadvisable for the
hobbyist. There are other microprocessors that are simpler to use.

STATUS

SINGLE COMBINATION BI-DlRECTlONAl ADDRESS/DATA BUS

_ ^ _

TIMING

tMf\

ADORESS

CONTROL

LOGIC

STORAGE

MEMORY

OUTPUT

INPUT

DERIVED ADORESS

Figure 2.3 A block diagram of a microcomputer utilizing a single multiplexed bi-directional bus for
both memory and input/output functions.

When building rather than buying a personal computer, the following criteria must
be carefully considered:

1. Circuit complexity — Keep components to a reasonable minimum. The more com¬
ponents in a design, the more likelihood of wiring errors and faulty devices.

2. Cost — While cost is important, it should not be the primary consideration. Any
microprocessor function could be simulated by using small scale integrated logic;
however, indirect costs resulting from using 200 chips to replace 3 or 4 LSI (laige
scale integration) devices would negate the value of using cheaper parts initially.
On the other hand, in the semiconductor industry, density means dollars. The
more functions a device can provide, and the fewer components necessary to ac-

CENTRAl PROCESSOR BASICS 23

Copyrighted material

complish these tasks, the higher the price. The level of integration incorporated in
a homebrew computer should fit somewhere in the middle. The ZAP computer
outlined in this book is a prime example of this philosophy. It uses a combination
of cost-effective LSI (large scale integration) and inexpensive SSI (small scale in¬
tegration) to produce a computer that the hobbyist can truly build, test, and use.
3. Software compatibility and availability — Building the hardware of a microcom¬
puter is only half the job. It must be programmed to perform useful work. Initially,
the builder will by necessity hand code and assemble his own programs. Eventual¬
ly, however, the need may arise for the computer to do a task requiring a very
large program which cannot be easily hand assembled. The user must rely upon an
assembler program in a larger machine. The assembler program would, of course,
have to be compatible with the instruction set of the microcomputer.

A further consideration is that personal computer enthusiasts are forever ex¬
changing software. It is possible to convert programs to run on any central pro¬
cessor, but the effort would be the same as writing the entire program from
scratch. This defeats the purpose of exchanging software. The personal computer
owner should choose a microprocessor that is somewhat compatible with the com¬
puters already on the market. My statement that all computers are alike is theoreti¬
cally true, but a book on how to build an esoteric one-of-a-kind computer is of lit¬
tle practical value.

Each criterion could be analyzed and answered individually, but we must give some
credit to the manufacturers of personal computers for doing some of the thinking for us
already. The fact that so many personal computers are in use has established de facto
standardization of central processor choice. To be compatible with existing software
and to have sufficient documentation available, the builder should consider choosing
among those central processors in commercial use. The four most used microproces¬
sors are

1. Intel 8080A

2. Motorola 6800

3. MOS Technology 6502

4. Zilog Z80

As a result of each device's wide following, documentation and software are readily
available. The availability of 8080A compatible software is highest; cost is low, but its
circuit complexity is also the greatest of the above. The 8080A, while described as a
“single-chip computer," relies on various external drivers and support devices. Its
minimum functional configuration consists of three chips as shown in figure 2.4. Its
central processor bus structure is similar to figure 2.3, but when combined with the
8224 and 8228 support chips, it emulates the more desirable bus architecture outlined in
figure 2.2.

8224

CLOCK

0RIVER

80804

PROCESSOR

)

8228

BUS

ORIVER

AND

CONTROLLER

TIMING a STATUS

)

ADDRESS BUS

DATA BUS

CONTROL BUS

Figure 2.4 A minimum three-chip 8080A configuration illustrating the necessary support devices. The

control bus contains the timing functions necessary to decode the contents of the data and address

buses.

24 CENTRAL PROCESSOR BASICS

Copyrighted material

The best of both worlds is incorporated within the Z80. Not only does it execute the
complete instruction set of the 8080A, but it also has additional instructions that serve
to make it a very powerful processor. The Z80 bus structure is illustrated in figure 2.5.
The Z80 is slightly more expensive than the other processors listed. However, its re¬
duced external circuitry results in an effective cost comparison. Further, the ease of in¬
terfacing the Z80 makes it the natural choice when building a microcomputer from
scratch.

AOORESS 8US
(16)

OATA BUS
( 8 )

CONTROL BUS
(13)

Figure 2.5 A block diagram of the Zilog Z80 bus structure.

CENTRAL PROCESSOR BASICS 25

Copyrighted material

CHAPTER 3

TUC 7QO

MICROPROCESSOR

Many books have been written on the software and hardware attributes of the Z80.
Although I am not attempting to duplicate the efforts of other authors, any book
dedicated to the construction of a microcomputer would be incomplete without a sec¬
tion describing the processor in some detail. By completely understanding the internal
logic and external control functions of the central processor, you will be able to under¬
stand better the way I've designed the rest of the system hardware. You have many op¬
tions when constructing a computer from scratch. The deeper your degree of under¬
standing, the greater your confidence in the outcome, and it is more likely that you will
add enhancements to your own design.

The ZAP computer allows considerable latitude in the selection of peripheral inter¬
facing. The choice depends primarily upon the design philosophy of the system, which
starts with the central processor.

CENTRAL PROCESSOR ARCHITECTURE

The Z80 is a register-oriented microprocessor. Eighteen 8-bit and four 16-bit registers
within the central processor are accessible to the programmer and function as static
programmable memory. These registers are divided into two sets, main and alternate,
each of which contains six general purpose 8-bit registers that may be used either in¬
dividually, or as three pairs of 16-bit registers. Also included are two sets of ac¬
cumulators and flag registers. Figure 3.1 illustrates the internal architecture of the Z80
central processor. Figure 3.2 shows that within the Z80 there are accumulators and flag
registers, along with general and special purpose registers.

Figure 3.1 A block diagram of the internal architecture of the Z80 central processor.

THE Z80 MICROPROCESSOR 27

Copyrighted material

MAIN REGISTER SET

ALTERNATE REGISTER SET

/-v

ACCUMULATOR

FLAGS

GENERAL

PURPOSE

REGISTERS

ACCUMULATOR

FLAGS

E 1

INTERRUPT

VECTOR

MEMORY

REFRESH

■N

INDEX REGISTER IX

INDEX REGISTER IV

STACK POINTER SP

PROGRAM COUNTER PC

SPECIAL

PURPOSE

REGISTERS

Figure 3.2 Z80 central processor register configuration.

The following is a description of the function and structure of the major components
of the central processor.

I. Registers

A. Accumulators and Flag Registers

The centra! processor contains two independent accumulator and flag-
register pairs, one in the main register set and the other in the alternate
register set. The accumulator receives the results of all 8-bit arithmetic
and logical operations, whereas the flag register indicates the occur¬
rence of specific logical or arithmetic conditions in the processor such
as parity, zero, sign, carry, and overflow. A single exchange instruc¬
tion allows the programmer to select either accumulator or flag-regis¬
ter pair.

B. General Purpose Registers

There are two similar sets of general purpose registers. The main regis¬
ter set contains six 8-bit registers called B, C, D, E, H, and L; the al¬
ternate register set also contains six 8-bit registers referred to as B',

C, D', E', IT, and L\ For 16-bit operations, these registers can be
grouped in 16-bit pairs (BC, DE, HL or BC, DE', HL'). A single ex¬
change instruction allows the programmer to alternately choose be¬
tween the register-pair sets.

C. Special Purpose Registers

1. PC (program counter)

The program counter contains a 16-bit address in memory
from which the current instruction will be fetched. Follow¬
ing execution of the instruction, the PC counter is either in¬
cremented, if the program is to proceed to the next byte in
memory, or the present PC contents are replaced with a
new value, if a jump or call instruction is to be executed.

2. SP (stack pointer)

The Z80 allows several levels of subroutine nesting
through use of a "stack" and a "stack pointer": when cer¬
tain instructions are executed, or when calls to subroutines
are made, the PC counter and other pertinent data can be
temporarily stored on a stack. A stack is a reserved area of
several memory locations, the top of which is indicated by
the contents of the stack pointer. That is to say, the stack
pointer shows the address of the most recently made entry,
because the memory locations are organized as a last-in,
first-out file. By looking at particular entries in the stack,

28 THE Z80 MICROPROCESSOR

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the central processor returns to a main program regardless
of the depth of nested subroutines. Theoretically, the stack
could be 64 K bytes long; however, program space must
not be overwritten by an expanding stack.

D. IX and IY Index Registers

These registers facilitate table data manipulation. They are two in¬
dependent 16-bit registers that hold the base addresses used in indexed
addressing modes, and point to locations in memory where pertinent
data is to be stored or retrieved. Incorporated within the indexed in¬
structions is a two's complement signed integer that specifies displace¬
ment from this base address.

E. Interrupt Page Address Register (I)

This is an 8-bit register that can be loaded with a page address of an in¬
terrupt service routine. During a mode 2 interrupt program, control
will vector to this page address.

F. Memory Refresh Register (R)

To enable dynamic memories for the Z80, a 7-bit memory refresh
register is automatically incremented after each instruction fetch.

II. Arithmetic and Logic Unit

Arithmetic manipulations and logical operations are handled eight bits at a time
in the Z80 ALU (arithmetic and logic unit). The ALU communicates internally
to the central processor registers and is not directly accessible by the program¬
mer. The ALU performs the following operations;

LEFT or RIGHT SHIFT
INCREMENT
DECREMENT
ADD

SUBTRACT

AND

EXCLUSIVE OR
COMPARE
SET BIT
RESET BIT
TEST BIT

III. Instruction Register and Central Processor Control

The instruction register holds the contents of the memory location addressed by
the PC (program counter) and is loaded during the fetch cycle of each instruc¬
tion. The central processor control unit executes the functions defined by the in¬
struction in the instruction register and generates all control signals necessary to
transmit the results to the proper registers.

IV. Central Processor Hardware

A. Figure 3.3 details the pinout of the Z80. It comes in an industry stan¬
dard 40 pin dual in-line package. The following is a listing and ex¬
planation of the pin functions:

A 0 —At* Three-state output, active high. A 0 —A, s constitute a
(Address 16-bit address bus. These signals provide the address for
Bus) memory data exchanges (up to 64 K bytes) and for I/O

device data exchanges. I/O addressing uses the eight
lower address bits to allow the user to directly select up
to 256 input or 256 output ports. A« is the least signifi¬
cant address bit. During refresh time, the lower seven
bits contain a valid refresh address.

D 0 —D 7 Three-state input/output, active high. D 0 —D 7 consti-

(Data Bus) tute an 8-bit bi-directional data bus which is used for

data exchanges with memory and I/O devices.

Ml Output, active low. Ml indicates that the current ma-

(Machine chine cycle is the operation-code fetch cycle of an in-

THE 280 MICROPROCESSOR 29

Copyrighted material

Cycle One) struction execu tion. Note that during execution of

2-byte opcodes. Ml is generated as each opcode byte
is fetched. These 2-byte opco des a lways begin with
CBH, DDH, EDH, or FDH. Ml also occurs with
IORQ to indicate an interrupt acknowledge cycle.

MREQ

(Memory

Request)

IORQ

(Input/

Output

Request)

(Memory

Read)

(Memory

Write)

RFSH

(Refresh)

HALT

(Halt

State)

WAIT

(Wait)

INT

(Interrupt)

NMI

(Non-

Maskable

Three-state output, active low. The memory request
signal indicates that the address bus holds a valid ad¬
dress for a memory-read or memory-write operation.

Three-state output, active low. The IORQ signal indi¬
cates that the lower half of the address bus holds a valid
I/O ad dress for an I/O read or wri te op eration. An
IORQ signal is also generated with an Ml signal when
an interrupt is being acknowledged to indicate that an
interrupt response vector can be placed on the data bus.
Inter rupt acknowledge operations may occur during
Ml time while I/O operations are prohibited.

Three-state output, active low. RD indicates that the
central processor wants to read from memory or an I/O
device. The addressed I/O device or memory should use
this signal to gate data onto the central processor data
bus.

Three-state output, active low. WR indicates that the
central processor data bus holds valid data to be stored
in the addressed memory or I/O device.

Output, active low. RFSH indicates that the lower
seven bits of the address bus contain a r efresh a ddress
for dynamic memories and the current MREQ signal
should be used to do a refresh read to all dynamic
memories.

Output, active low. HALT indicates that the central
processor has executed a HALT instruction and is
awaiting either a nonmaskable or a maskable interrupt
(with the mask enabled) before operation can resume.
While halted, the central processor executes NOPs (no
operation) to maintain memory refresh activity.

Input, active low. WAIT indicates to the Z80 central
processor that the addressed memory or I/O devices are
not ready for a data transfer. The cent ral proce ssor con¬
tinues to enter wait states as long as WAIT is active;
this signal allows memory of I/O devices to be syn¬
chronized to the central processor.

Input, active low. The Interrupt request signal is gener¬
ated by I/O devices. A request will be honored at the
end of the current instruction if the internal software
controlle d interrupt enable flip-flop is enabled and if the
BUSRQ signal is not active. When the central pro-
cessor accepts the interrupt, an acknowledge signal
(IORQ during Ml time) is sent out at the beginning of
the next instruction cycle. The central processor can re¬
spond to an interrupt in the three different modes.

Input, negative edge triggered. The nonmas kable inter¬
rupt request line has a higher priority than INT and is
always recognized at the end of the current instruction.

30 THE ZSO MICROPROCESSOR

Copyrighted material

Interrupt) regar dless of the status of the interrupt-enable flip-flop.

NMI forces the Z80 central processor to restart to loca¬
tion 0066 l6 . The program counter is automatically saved
in the external stack so that the user can return to the
program that was interrupted. Note that continuous
WAIT cycles can prevent th e current instru ction from
ending, and that a BUSRQ will override an NMI.

SYSTEM

CONTROL

MREQ

IORQ

£5

RFSH

f MALT

CPU

CONTROL

IN?

NMI

^ RESET

CPU BUS j BUSRQ
CONTROL ] BUSAK

CLOCK
♦ 5V
GNO

A10
All
A12
A13
A14
A15

ADDRESS

BUS

OATA

BUS

Figure 3.3 Pin configuration for the Z80 microprocessor.

The actual timing of these signals will be discussed in the hardware sections.

V. Z80 Instruction Types

The Z80 can execute 158 separate instructions including all 78 of the 8080A.
They can be grouped as follows:

A. LOAD AND EXCHANGE

Load instructions move data between registers or between registers
and memory. The source and destination of this data is specified
within the instruction. Exchange instructions swap the contents of two
registers.

B. ARITHMETIC AND LOGICAL

These instructions operate on data in the accumulator, a register, or a
designated memory location. Results are placed in the accumulator
and flags are set accordingly. Arithmetic operations include 16-bit ad¬
dition and subtraction between register pairs.

C. BLOCK TRANSFER AND SEARCH

The Z80 uses a single instruction to transfer any size block of memory
to any other group of contiguous memory locations. The block search
uses a single command to examine a block of memory for a particular
8-bit character.

D. ROTATE AND SHIFT

Data can be rotated and shifted in the accumulator, a central pro¬
cessor register, or memory. These instructions also have binary-coded

THE Z80 MICROPROCESSOR 31

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decimal (BCD) handling facilities.

E. BIT MANIPULATION

Bit manipulation includes set, reset, and test functions. Individual bits
may be modified or tested in the accumulator, a central processor, or
memory. The results of the test operations are indicated in the flag
register.

F. JUMP, CALL AND RETURN

A jump is a branch to a program location specified by the contents of

the program counter. The program counter contents can come from

three addressing modes: immediate, extended, or register indirect. A
call is a special form of jump where the address following the call in¬
struction is pushed onto the stack before the jump is made. A return is
the reverse of the call. This category includes special restart instruc¬
tions.

G. INPUT AND OUTPUT

These instructions transfer data between register and memory to ex¬
ternal I/O devices. There are 256 input and 256 output ports avail¬
able. Special instructions provide for moving blocks of 256 bytes to or
from I/O ports and memory.

H. CPU CONTROL

These instructions include halting the CPU or causing a NOP (no
operation) to be executed. The ability to enable or disable interrupt in¬
puts is a further control capability.

VI. Instruction and Data Formats

Memory for the Z80 is organized into 8-bit quantities called bytes (see figure
3.4). Each program byte is stored in a unique memory position and is referenced
by a 16-bit binary address.

Total direct addressing capability is 65,536 bytes (64 K) of memory, which
may be any combination of ROM (read-only memory), EPROM (erasable-pro¬
grammable read-only memory), or programmable memory. Data is stored in
the formats of figure 3.5.

MS8

(MOST SIGNIFICANT BIT)

ISB

(LEAST SIGNIFICANT BIT)

Figure 3.4 Organization of a data byte in the Z80.

SINGLE-BYTE INSTRUCTIONS

BYTE l 07

OPCODE

TWO-BYTE INSTRUCTIONS

BYTE 1

BYTE 2

OPCODE

OAT* OR
ADDRESS

THREE-BYTE INSTRUCTIONS

8YTE 1

OPCODE

BYTE 2 07

BYTE 3 07

DATA OR
(ADDRESS

FOUR-BYTE INSTRUCTIONS

BYTE 1 I 07
BYTE 2

BYTE 3 [07

BYTE 4

OPCODE

OATA OR
AOORESS

Figure 3.5 Machine-language instruction formats for the Z80.

32 THE Z80 MICROPROCESSOR

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VII. Z80 Status Flags

The flag register (F and F') supplies information to the user regarding the status
of the central processor at any given time. There are four testable and two
nontestable flag bits in each register. Figure 3.6 shows the position and identity
of these flag bits.

BIT 7 BIT 6 BITS BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

-1-1-1-I-1-1-1-

S Z X H X P/V N C

_I_I_I_1_I_I_I_

MSB LSB

C * CARRY FLAG
n * ado/subtract flag

P/Y» PARITY/OVERFLOW FLAG
H»HALF-CARRY FLAG
Z * ZERO FLAG
S• SIGN FLAG
X • NOT USED

Figure 3.6 Position and identity of status flag bits in the flag register.

Instructions set (flag bit = 1) or reset (flag bit = 0) flags in a manner rele¬
vant to the particular operation being executed.

VIII. The Z80 Instruction Set

The following symbols and abbreviations are used in the subsequent description
of the Z80 instructions:

Symbol Meaning

accumulator

address

high-order address
low-order address
data

high-order data
low-order data
port
r, r'

A 16-bit address quantity

The most significant 8 bits of the 16-bit address

The least significant 8 bits of the 16-bit address

An 8- or 16-bit quantity

The most significant 8 bits of the 16-bit data

The least significant 8 bits of the 16-bit data

An 8-bit address of an I/O device

One of the registers A, B, C D, E, H, or L

A 1-byte expression in the range of 0 thru 255

A 2-byte expression in the range of 0 thru 65,535

A 1-byte expression in the range of —128 to 127

An expression in the range of 0 thru 7

A 1-byte expression in a range of —126 to 129

The state of the flags for conditional JR and JP instructions:

XXH

Condition

Relevant Flag

000

NZ non zero

Z .

001

Z zero

010

NC non carry

011

C carry

100

PO parity odd

P/V

101

PE parity even

P/V

110

P sign positive

111

M sign negative

Denotes hexadecimal address value

Any one of the register pairs BC, DE, HL, or AF

Any one of the register pairs BC, DE, HL, or SP

Ti iE Z80 MICROPROCESSOR 33

Copyrighted material

Any one of the register pairs BC, DE, IX, or SP

Any one of the register pairs BC, DE, IY, or SP

Any of r, n, (HL), (IX + d), or (IY + d)

Any one of the register pairs BC, DE, HL, or SP

Any of r, (HL), (IX + d), or (IY + d)

(HL)

Specifies the contents of memory at the location
by the contents of the register pair HL

(nn)

Specifies the contents of memory at the location
by the 2-byte expression in nn

Program counter

Stack pointer

An expression in the range of 0 thru 7.

C,N,P/V, H, Z,S

Condition flags:

C Carry

N Add/Subtract

P/V Parity/Overflow

H Half-Carry

Z Zero

S Sign

—

"is transferred to"

Logical AND

Exclusive OR

Inclusive OR

Addition

—

Subtraction

"is exchanged with"

EIGHT-BIT LOAD GROUP
LDr, r*

r — r'

The contents of any register r' are loaded into any other register r.

—i—i— 1—1 i— n —l—

_l-1-1_I_I_L_i_

Cycles: 1
States: 4
Flags: none

LD r, n

r — n

The 8-bit integer n is loaded into any register r.

- 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1

0 0-—r--1 1 0

_j_i_i_i_ 1 1 1 I

Cycles: 2
States: 7
Flags: none

LD r, (HL)

r — (HL)

The 8-bit contents of memory location (HL) are loaded into register r.

—i—i—r~i—i—i—i—

0 -r--1 1 0

_I_I_I_I_L_J_I-

34 THE Z80 MICROPROCESSOR

Copyrighted material

Cycles: 2
States: 7
Flags: none

LD r, (IX+d)

r - (IX+d)

The operand (IX+d) (the contents of the Index Register IX summed with a
displacement integer d) is loaded into register r.

Cycles: 5
States: 19
Flags: none

LD r, (IY+d)

r - (IY+d)

The operand (IY+d) (the contents of the Index Register IY summed with a
displacement integer d) is loaded into register r.

Cycles: 5
States: 19
Flags: none

LD (HL), r

(HL) - r

The contents of register r are loaded into the memory location specified by
the contents of the HL register pair.

Cycles: 2
States: 7
Flags: none

LD (IX+d), r

(IX+d) - r

The contents of register r are loaded into the memory address specified by the
contents of Index Register IX summed with d, which is a two's complement
displacement integer.

Cycles: 5
States: 19
Flags: none

TOE ZSO MICROPROCESSOR 35

Copyrighted material

LD (IY+d), r

(IY+d) - r

The contents of register r are loaded into the memory address specified by the
sum of the contents of the Index Register IY and d, a two's complement
displacement integer.

Cycles: 5
States: 19
Flags: none

LD (HL), n

(HL) - n

Integer n is loaded into the memory address specified by the contents of the
HL register pair.

Cycles: 3
States: 10
Flags: none

LD (IX+d), n

(IX+d) - n

The n operand is loaded into the memory address specified by the sum of the
contents of the Index Register IX and the two's complement displacement
operand d.

Cycles: 5
States: 19
Flags: none

LD (IY+d), n

(IY+d) - n

Integer n is loaded into the memory location specified by the contents of the
Index Register IY summed with a displacement integer d.

Cycles: 5
States: 19
Flags: none

36 THE Z30 MICROPROCESSOR

Copyrighted material

LD A, (BC)

A - (BC)

The contents of the memory location specified by the contents of the BC
register pair are loaded into the Accumulator.

I —l—I I I—I—l-I-1

0 0 0 0 1 0 1 0
_I_I_I_I_I_I_I_I

Cycles: 2
States: 7
Flags: none

LD A, (DE)

A - (DE)

The contents of the memory location specified by the register pair DE are

loaded into the Accumulator.

f— i—r - 1—i—i i i |

0 0 0 1 1 0 1 0
_I_I_I_1_I_I_I—I

Cycles: 2
States: 7
Flags: none

LD A, (nn)

A — (nn)

The contents of the memory location specified by the operands nn are loaded
into the Accumulator. The first n operand is the low-order byte of a 2-byte
memory address.

Cycles: 4
States: 13
Flags: none

LD (BC), A

(BC) - A

The contents of the Accumulator are loaded into the memory location
specified by the contents of the register pair BC.

r t i ‘ T • i—i—i—i—

0 0 0 0 0 0 1 0

—I—I—I_I—I—I_I—

Cycles: 2
States: 7
Flags: none

LD (DE), A

(DE) - A

The contents of the Accumulator are loaded into the memory location

specified by the DE register pair.

—i-1—i-1—i - r~~i-1

0 0 0 1 0 0 1 0

_l_l_I_I_I_l l 1

Cycles: 2
States: 7
Flags: none

THE ZS0 MICROPROCESSOR 37

Copyrighted material

LD (nn), A

(nn) — A

The contents of the Accumulator are loaded into the memory address
specified by the operands nn. The first n operand is the low-order byte of
operand nn.

Cycles: 4
States: 13
Flags: none

LD A, I

A - I

The contents of the Interrupt Vector Register I are loaded into the
Accumulator.

Cycles: 2

Qf-ifpc* Q

Flags: S, Z, H, N, P/V

S: set if I < 0; reset otherwise
Z: set if 1=0; reset otherwise
H,N: reset

P/V: contains contents of IFF2

LD A, R

A — R

The contents of Memory Refresh Register R are loaded into the Accumulator.

Cycles: 2
States: 9
Flags: S,Z,H,N,P/V

S: set if R < 0; reset otherwise
Z: set if R=0; reset otherwise
H,N: reset

P/V: contains contents of IFF2

LD I, A

I - A

The contents of the Accumulator are loaded into the Interrupt Control Vec¬
tor Register I.

Cycles: 2
States: 9
Flags: none

33 THE Z80 MICROPROCESSOR

Copyrighted material

LD R, A

R - A

The contents of the Accumulator are loaded into the Memory Refresh
Register R.

—r—i—i—i—i—i—i—|

1110 110 1

—i—i—l—I—l—I—I—I

Cycles: 2
States: 9
Flags: none

SIXTEEN-BIT LOAD INSTRUCTIONS

LD dd, nn

dd — nn

The 2-byte integer nn is loaded into the dd register pair, where dd defines the
BC, DE, HL, or SP register pairs, assembled as follows in the object code:

Pair dd

BC 00

DE 01

HL 10

SP 11

Cycles: 3
States: 10
Flags: none

LD IX, nn

IX - nn

LD IY, nn

1Y - nn

Integer nn is loaded into the Index Register IY.

Cycles: 4
States: 14
Flags: none

THE Z80 MICROPROCESSOR 39

Copyrighted material

LD HL, (nn)

H — (nn-f 1), L — (nn)

The contents of memory address nn are loaded into register L, and the con¬
tents of the next highest memory location (nn-f 1) are loaded into register H.

Cycles: 5
States: 16
Flags: none

LD dd, (nn)

dd w — (nn-f 1), dd* — (nn)

The contents of address nn are loaded into the low-order portion of register
pair dd, and the contents of the next highest memory address (nn-f 1) are

LD IX, (nn)

1X„ - (nn-f 1), IX* - (nn)

The contents of the address nn are loaded into the low-order portion of Index
Register IX, and the contents of the next highest memory address (nn-f 1) are

LD IY, (nn)

IY* - (nn-f 1), IY* - (nn)

The contents of address nn are loaded into the low-order portion of Index
Register IY, and the contents of the next highest memory address (nn -f 1) are
loaded into the high-order portion of IY.

40 THE 230 MICROPROCESSOR

Copyrighted material

LD (nn),

LD (nn), dd

(nn + 1) — dd*, (nn) — dd*.

The low-order byte of register pair dd is loaded into memory address nn; the
upper byte is loaded into memory address nn + 1.

Cycles: 6
States: 20
Flags: none

LD (nn), IX

(nn+1) - IX*, (nn) - IX*

The low-order byte in Index Register IX is loaded into memory address nn;
the upper-order byte is loaded into the next highest address nn+1.

Cycles: 6
States: 20
Flags: none

LD (nn), IY

(nn + 1) - IY*, (nn) - IY,

The low-order byte in Index Register IY is loaded into memory address nn;
the upper-order byte is loaded into memory location nn+1.

THE Z80 MICROPROCESSOR 41

Copyrighted material

Cycles: 6
States: 20
Flags: none

LD SP, HL

SP - HL

The contents of the register pair HL are loaded into the SP (stack pointer).

Cycles: 1
States: 6
Flags: none

LD SP, IX

SP - IX

The 2-byte contents of Index Register IX are loaded into the SP (stack
pointer).

Cycles: 2
States: 10
Flags: none

LD SP, IY

SP - IY

The 2-byte contents of Index Register IY are loaded into the SP (stack
pointer).

Cycles: 2
States: 10
Flags: none

PUSH qq

(SP—2) — qq L , (SP-1) — qq„

The contents of the register pair qq are pushed into the external memory
LIFO (last-in, first-out) Stack. The Stack Pointer (SP) register pair holds the
16-bit address of the current "top” of the Stack. This instruction first
decrements the SP and loads the high order byte of register pair qq into the
memory address now specified by the SP; then decrements the SP again and
loads the low order byte of qq into the memory location corresponding to
this new address in the SP.

Cycles: 3
States: 11
Flags: none

42 THE 2S0 MICROPROCESSOR

Copyrighted material

PUSH IX

(SP-2) - IX t , (SP-1) - IX*

The contents of the Index Register IX are pushed into the Stack. This instruc¬
tion first decrements the SP and loads the high-order byte of IX into the
memory address now specified by the SP; it then decrements the SP again
and loads the low-order byte into the memory location corresponding to this
new address in the SP.

Cycles: 3
States: 15
Flags: none

1 —

T—

1—1

ill

I-

J—

-L_J

PUSH IY

(SP-2) - IY t , (SP-1) - IY*

The contents of the Index Register IY are pushed into the Stack. This instruc¬
tion first decrements the SP and loads the high-order byte of IY into the
memory address now specified by the SP; it then decrements the SP again
and loads the low-order byte into the memory location corresponding to this
new address in the SP.

Cycles: 4
States: 15
Flags: none

POP qq

qq* - (SP + 1), qq £ - (SP)

The top 2 bytes of the Stack are popped into register pair qq. This instruction
first loads into the low-order portion of qq the byte at the memory location
corresponding to the contents of SP; then SP is incremented and the contents
of the corresponding adjacent memory location are loaded into the high-
order portion of qq, and the SP is now incremented again.

I i ' l-1-1-1-1-1-1

llqqOOOll

_i_i_L—J_I_I_1—1

Cycles: 3
States: 10
Flags: none

POP IX

IX* - (SP+1), IXt - (SP)

The top 2 bytes of the Stack are popped into Index Register IX. This instruc¬
tion first loads into the low-order portion of IX the byte at the memory loca¬
tion corresponding to the contents of SP; the SP is incremented and the con¬
tents of the corresponding adjacent memory location are loaded into the

high-order portion of IX. The SP is now incremented again.

i i i i—i—i—i—I

110 1110 1

_l_l_ I _ I _ I _l— J _I

"—r—r—i—i—r— t— r-

Cvcles* 4 11100001

mT 14 I'll ' '''

Flags: none

THE Z80 MICROPROCESSOR 43

Copyrighted material

POP IY

IY„ - (SP+1), IY* - (SP)

The top 2 bytes of the Stack are popped into Index Register IY. This instruc¬
tion first loads into the low-order portion of IY the byte at the memory loca¬
tion corresponding to the contents of SP; then the SP is incremented and the
contents of the corresponding adjacent memory location are loaded into the
high-order portion of IY. The SP is now incremented again.

Cycles: 4
States: 14
Flags: none

EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP

EX DE, HL

DE - HL

The 2-byte contents of register pairs DE and HL are exchanged.

—i—i—i—i—i—i—i—

1110 10 11

—i—i—i—i—i—i— i —

Cycles: 1
States: 4
Flags: none

EX AF, A F

AF ~ AF'

The 2-byte contents of the register pairs AF and AF' are exchanged.

—i-1-1-1—i-1—i-1

0 0 0 0 1 0 0 0

-1-1—I—I—l—I_l_1

Cycles: 1
States: 4
Flags: none

EXX

(BC) - (BC), (DE) ~ (DE') # (HL) - (HL')

Each 2-byte value in register pairs BC, DE, and HL is exchanged with the
2-byte value in BC', DE', and HL' respectively.

—i—i—i—i—i—i—i—

110 110 0 1
_i—i_I_i_i .. . i i . -

Cycles: 1
States: 4
Flags: none

44 THE Z&Q MICROPROCESSOR

Copyrighted material

EX (SP), HL

H - (SP+1), L - (SP)

The low-order byte contained in register pair HL is exchanged with the con¬
tents of the memory address specified by the contents of register pair SP, and
the high-order byte of HL is exchanged with the next highest memory address

(SP+1).

—i—i—i—i—i—i i 1

1 1 1 0 0 0 1 1
1 1 III_I_ 1 _ I

Cycles: 5
States: 19
Flags: none

EX (SP), IX

IX„ - (SP+1), IX, - (SP)

The low-order byte in the Index Register IX is exchanged with the contents of
the memory address specified by the contents of register pair SP, and the
high-order byte of IX is exchanged with the next highest address (SP+1).

|—i—i—i—i—i—i—i—|

110 1110 1
I_i_i_I_i_I_I_l_1

—i—i—i—i—i—i—i—

Cycles: 6 1 1 1 0 0 0 1 1

States: 23 L 1 1 1 1 1 1 1 -

Flags: none

EX (SP), IY

I Yu - (SP+1), IY, - (SP)

The low-order byte in Index Register IY is exchanged with the contents of the
memory address specified by the contents of register pair SP, and the high-
order byte of IY is exchanged with the next highest memory address.

Cycles: 6
States: 23
Flags: none

LDI

(DE) - (HL), DE - DE + 1, HL - HL+1, BC - BC-1

A byte of data is transferred from the memory location addressed by the con¬
tents of the HL register pair to the memory location addressed by the contents
of the DE register pair. Then both register pairs are incremented and the BC
(byte counter) register pair is decremented.

-1-1-l-1-1-1-1-I

1110 110 1
_I_I_I_I_I_I_I_I

Cycles:

States:

Flags:

H,N,P/V

“T—i—i—i— r— l—i—

1 0 1 0 0 0 0 0

—I_I_I_I 1 i » -

H, N: reset

P/V: set if BC —1^0; reset otherwise

THE 280 MICROPROCESSOR 45

Copyrighted material

LDIR

(DE) - (HU DE - DE+1, HL - HL+1, BC - BC-1

This 2-byte instruction transfers a byte of data from the memory location ad¬
dressed by the contents of the HL register pair to the memory location ad¬
dressed by the DE register pair. Then, both register pairs are incremented and
the BC (byte counter) register pair is decremented. If decrementing causes the
BC to go to 0, the instruction is terminated. If BC is not 0, the program
counter is decremented by 2 and the instruction is repeated. Note: if BC is set
to 0 prior to instruction execution, the instruction will loop through 64 K
bytes. Also, interrupts will be recognized after each data transfer.

For BC*0:

Cycles: 5
States: 21

For BC = 0:

Cycles: 4
States: 16

Flags: H,N,P/V: reset

LDD

(DE) - (HL), DE - DE—1, HL - HL-1, BC - BC-1

cluding the BC (byte counter) register pair are decremented.

- 1 - 1 - 1 - 1 - 1 - 1 - 1 -

1110 110 1

— 1- 1 I „J_I—l—l—

- 1 - 1 - 1 - 1 — I — i — i -

10 10 10 0 0
I I _ I ■ 1—1_ I _I_

4
16

H,N,P/V
H, N: reset

P/V: set if BC —1=£0; reset otherwise

Cycles:

States:

Flags:

LDDR

(DE) - (HL), DE - DE —1, HL - HL-1, BC - BC-1

This 2-byte instruction transfers a byte of data from the memory location ad¬
dressed by the contents of the HL register pair to the memory location ad¬
dressed by the contents of the DE register pair. Then both registers, as well as
the BC (byte counter), are decremented. If decrementing causes the BC to go
to 0, the instruction is terminated. If BC is not 0, »he program counter is
decremented by 2 and the instruction is repeated. Note: if BC is set to 0 prior
to instruction execution, the instruction will loop through 64 K bytes. Also,
interrupts will be recognized after each data transfer.

46 THE Z60 MICROPROCESSOR

Copyrighted material

For BC*0:

Cycles: 5
States: 21

For BC=0:

Cycles: 4
States: 16

Flags: H,N,P/V: reset

CPI

A-(HL), HL - HL + 1, BC - BC-1

The contents of the memory location addressed by the HL register pair are

compared with the contents of the Accumulator. In case of a true compare, a

condition bit is set. Then HL is incremented and the byte counter (register

pair BC) is decremented.

I' l 1 'VI I I I—I—

1110 110 1
— j . i i_ 1 1 I —i—

Cycles:

States:

Flags:

S,Z,H,N,P/V

S: set if result is negative; reset otherwise

Z: set if A=(HL); reset otherwise

H: set if no borrow from bit 4; reset otherwise

N: set

P/V: set if BC —1*0; reset otherwise

CPIR

A —(HL), HL - HL + 1, BC - BC-1

The contents of the memory location addressed by the HL register are com¬
pared with the contents of the Accumulator. In case of a true compare, a con¬
dition bit is set. The HL is incremented and the BC is decremented. If
decrementing causes the BC to go to 0 or if A = (HL), the instruction is ter¬
minated. If BC is not 0 and if A* (HL), the program counter is decremented
by two, and the instruction is repeated. Note: if BC is set to 0 before instruc¬
tion execution, the instruction will loop through 64 K bytes, if no match is
found. Also, interrupts will be recognized after each data comparison.

—i—i—i—I l "" l—l—

1110 110 1
* «_» ■ ■_i_ j_

—i—i—i—i—i—i—i-

1 0 1 1 0 0 0 1

—I—I—I—I—I—I—I—

For BC=£0 and A*(HL):

Cycles: 5
States: 21

For BC=0 or A = (HL):
Cycles: 4

THE ZSO MICROPROCESSOR 47

Copyrighted material

States: 16

Flags: S,Z,H,N,P/V

S: set if result is negative; reset otherwise
Z: set if A = (HL); reset otherwise
H: set if no borrow from bit 4; reset otherwise
N: set

P/V: set if BC—1*0; reset otherwise

CPD

A—(HL), HL - HL-1, BC - BC-1

The contents of the memory location addressed by the HL register pair are
compared with the contents of the Accumulator. In case of a true compare a
condition bit is set. The HL and the BC are decremented.

Cycles:

States:

Flags:

s,z,h,n,p/v

S: set if result is negative; reset otherwise
Z: set if A = (HL); reset otherwise
H: set if no borrow from bit 4; reset otherwise
N: set

P/V: set if BC —1*0; reset otherwise

CPDR

A —(HL), HL - HL-1, BC - BC-1

The contents of the memory location addressed by the HL register pair are
compared with the contents of the Accumulator. In case of a true compare a
condition bit is set. The HL and BC register pairs are decremented. If
decrementing causes the BC to go to 0 or if A = (HL), the instruction is ter¬
minated. If BC is not 0 and A* (HL), the program counter is decremented by

2 and the instruction is repeated. Note: if BC is set to 0 prior to instruction ex¬
ecution, the instruction will loop through 64 K bytes if no match is found.
Also, interrupts will be recognized after each data comparison.

For BC * 0 and A * (HL):

Cycles: 5
States: 21

For BC = 0 or A=(HL):

Cycles: 4
States: 16

Flags: S,Z,H,N,P/V

S: set if result is negative; reset otherwise
Z: set if A“(HL); reset otherwise
H: set if no borrow from bit 4; reset otherwise
N: set

P/V: set if BC —1*0; reset otherwise

48 THE 280 MICROPROCESSOR

Copyrighted material

EIGHT-BIT ARITHMETIC AND LOGICAL GROUP

ADD A, r

A - A+r

The contents of register r are added to the contents of the Accumulator, and
the result is stored in the Accumulator.

—i-1-1-1-1-1-1-1

1 0 0 0 0 —-r-H

_i_i_t ii_i—i—I

Cycles: 1
States: 4

Flags: S, Z, H, N, C, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

C: set if carry from bit 7; reset otherwise
P/V: set if overflow; reset otherwise

ADD A, n

A — A+n

The integer n is added to the contents of the Accumulator, and the results are
stored in the Accumulator.

—r
1

—r

-T

—r
0

—r
1

T-

1 0
_1_

—r

n -

_1_

Cycles; 2

States: 7

Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

C: set if carry from bit 7; reset otherwise
P/V: set if overflow; reset otherwise

ADD A, (HL)

A - A+(HL)

The byte at the memory address specified by the contents of the HL register
pair is added to the contents of the Accumulator, and the result is stored in
the Accumulator.

-I-1-1-1-1-1-1-1

1 0 0 0 0 1 1 0

_J—I—I—' 1 I 1 1

Cycles: 2
States: 7

Flags: S, Z, H, N, C, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

C: set if carry from bit 7; reset otherwise
P/V: set if overflow; reset otherwise

THE 280 MICROPROCESSOR 49

Copyrighted material

ADD A, (IX+d)

A - A+(IX+d)

The contents of the Index Register IX are added to a displacement d to point
to an address in memory. The contents of this address are then added to the
contents of the Accumulator, and the result is stored in the Accumulator.

Cycles: 5
States: 19

Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

C: set if carry from bit 7; reset otherwise
P/V: set if overflow; reset otherwise

ADD A, (IY+d)

A - A+(IY-f d)

The contents of the Index Register IY are added to a displacement d to point
to an address in memory. The contents of this address are then added to the
contents of the Accumulator, and the result is stored in the Accumulator.

Cycles: 5
States: 19

Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: set

C: set if carry from bit 7; reset otherwise
P/V: set if overflow; reset otherwise

50 THE Z80 MICROPROCESSOR

Copyrighted material

ADC A, s

A - A+s+CY

The s operand is any of r, n, (HL), (IX+d), or (IY+d) as defined for the
analogous ADD instruction. These various possible opcode operand com¬
binations are assembled in the object code as follows:

ADC A, r
ADC A, n

ADC A, (HL)
ADC A, (IX+d)

ADC A, (IY+d)

The s operand, along with the Carry Flag ("C" in the F register) is added to
the contents of the Accumulator, and the result is stored in the Accumulator.

Instruction

ADC A, r
ADC A, n
ADC A, (HL)
ADC A, (IX+d)
ADC A, (IY+d)

Cycles

States

Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

C: set if carry from bit 7; reset otherwise
P/V: set if overflow; reset otherwise

THE Z80 MICROPROCESSOR 51

Copyrighted material

SUBs

A — A—s

The s operand is subtracted from the contents of the Accumulator, and the
result is stored in the Accumulator.

SUB r

SUB n

SUB (HL)
SUB (IX+d)

SUB (IY+d)

Instruction Cycles States

SUB r 1 4

SUB n 2 7

SUB (HL) 2 7

SUB (IX+d) 5 19

SUB (IY+d) 5 19

Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if no borrow from bit 4; reset otherwise
N: set

C: set if no borrow; reset otherwise
P/V: set if overflow; reset otherwise

52 THE Z80 MICROPROCESSOR

Copyrighted material

SBC A, s

A - A-s-CY

The s operand, along with the Carry Flag ("C" in the F register) is subtracted
from the contents of the Accumulator, and the result is stored in the
Accumulator.

SBC A, r

SBC A, n

SBC A, (HL)

SBC A,(IX+d)

SBC A, (IY+d)

Instruction Cycles States

SBC A, r 1 4

SBC A, n 2 7

SBC A, (HL) 2 7

SBC A, (IX+d) 5 19

SBC A, (IY+d) 5 19

Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if no borrow from bit 4; reset otherwise
N: set

C: set if no borrow; reset otherwise
P/V: set if overflow; reset otherwise

THE Z &0 MICROPROCESSOR 53

Copyrighted material

AND s

A — s

A logical AND operation, bit by bit, is performed between the byte specified
by the s operand and the byte contained in the Accumulator; the result is
stored in the Accumulator.

ANDr

AND n

AND (HL)
AND(IX-fd)

ANDUY+d)

Instruction Cycles States

ANDr 1 4

AND n 2 7

AND (HL) 2 7

AND (IX+d) 5 19

Flags: S, Z, H, N, C, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set
N: reset
C: reset

P/V: set if parity even; reset otherwise

54 THE Z80 MICROPROCESSOR

Copyrighted material

ORs

A — Avs

A logical OR operation, bit by bit, is performed between the byte specified
by the s operand and the byte contained in the Accumulator; the result is
stored in the Accumulator.

ORr

ORn

OR(HL)

OR(IX-fd)

OR(IY+d)

Instruction

Cycles States

ORr
ORn
OR (HL)
OR (IX+d)
OR (IY+d)

Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set
N: reset
C: reset

P/V: set if parity even; reset otherwise

THE Z80 MICROPROCESSOR S5

Copyrighted material

XORs

A — Aes

A logical exclusive-OR operation, bit by bit, is performed between the byte
specified by the s operand and the byte contained in the Accumulator; the
result is stored in the Accumulator.

XORr

XORn

XOR (HL)
XOR (IX+d)

XOR (IY+d)

■ ■ T

—r

-r
1

—r

-r

—r

. A _

—r

i ; , , ■ , , . i

—r
1

—r
0

—r
1

—r

. A _

—r

_ L

' U

_ L

Instruction

XORr

Cycles

States

XORn
XOR (HL)
XOR (IX+d)
XOR (IY+d)

2 7

5 19

Flags; S,Z, H, N, C,P/V

S: set if result is negative; reset otherwise
Z: set if result if 0; reset otherwise
H: set
N: reset
C; reset

P/V; set if parity even; reset otherwise

56 THE ZOO MICROPROCESSOR

Copyrighted material

CPs

A—s

The contents of the s operand are compared with the contents of the Ac¬
cumulator. If there is a true compare, a flag is set.

CP r

CP n

CP (HL)

CP (IX+d)

CP (IY+d)

Instruction Cycles States

CP r 14

CP n 2 7

CP (HL) 2 7

CP (IX+ d) 5 19

CP (IY+d) 5 19

Flags: MUHCP/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if no borrow from bit 4; reset otherwise
N: set

C: set if no borrow; reset otherwise
P/V: set if overflow; reset otherwise

THE ZSO MICROPROCESSOR 57

Copyrighted material

INC r

r — r+1

—i—i—i—i—i—i—n

0 0--r—- 1 0 0

_i_i_i_i_i_i_i_

Cycles: 1
States: 4

Flags: S,Z,H,N,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

P/V: set if r was 7FH before operation; reset otherwise

INC (HL)

(HL) - (HL) + 1

The byte contained in the address specified by the contents of the HL register
pair is incremented.

—i r i —i —iiii

0 0 110 10 0

_I_I_L_J_L_l_I_

Cycles: 3
States: 11

Flags: S,Z,H,N ( P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

P/V: set if (HL) was 7FH before operation; reset otherwise

INC (IX+d)

(IX + d) - (IX + d) + l

The contents of the Index Register IX are added to a two's complement
displacement integer d to point to an address in memory. The contents of this
address are then incremented.

Cycles:

States:

Flags:

S, Z, H, N, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

P/V: set if (IX+d) was 7FH before operation; reset otherwise

INC (IY+d)

(IY+d) - (IY+d)+l

The contents of the Index Register IY are added to a two's complement

58 THE Z80 MICROPROCESSOR

Copyrighted material

displacement integer d to point to an address in memory. The contents of this
address are then incremented.

Cycles:

States:

Flags:

S,Z,H,N,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry from bit 3; reset otherwise
N: reset

P/V: set if (IY-fd) was 7FH before operation; reset otherwise

DEC m

m — m-1

Instruction

Cycles

States

DEC r

DEC (HL)

DEC (IX+d)

DEC (IY+d)

Flags: S,Z,H,N,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if no borrow from bit 4; reset otherwise
N: set

P/V: set if m was 80H before operation; reset otherwise

THE Z80 MICROPROCESSOR 59

Copyrighted material

GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS

CPL _

A — A

Contents of the Accumulator are inverted (l's complement).

Cycles: 1
States: 4
Flags: H, N

H: set
N: set

NEG

A - 0—A

The contents of the Accumulator are negated (two's complement). This is the
same as subtracting the contents of the Accumulator from 0.

Cycles: 2
States: 8
Flags: S,Z, H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if no borrow from bit 4; reset otherwise
N: set

C: set if Accumulator was not 00H before operation; reset other¬
wise

P/V: set if Accumulator was 80H before operation; reset otherwise

CCF _

CY - CY

The C flag in the F register is inverted.

Cycles: 1
States: 4
Flags: H,N,C

H: previous carry will be copied
N: reset

C: set if CY was 0 before operation; reset otherwise

SCF

CY - 1

The C flag in the F register is set.

Cycles: 1
States: 4
Flags: H,N,C

60THEZ80 MICROPROCESSOR

Copyrighted material

NOP

H: reset
N: reset
C: set

The central processor performs no operation during this machine cycle.

-1—l—l—i— i i i |

00000000
_I_I_I I I _ I _ I _

Cycles: 1
States: 4
Flags: none

DAA

This instruction conditionally adjusts the Accumulator for BCD addition and
subtraction operations. For addition (ADD, ADC, INC) or subtraction (SUB,
SBC, DEC, NEG), the following table indicates the operation performed:

OPERATION

BEFORE

DAA

HEX

VALUE

UPPER

DIGIT

(bit

7-4)

BEFORE

DAA

HEX

VALUE

LOWER

DIGIT

(bit

3-0)

NUMBER

ADDED

BYTE

AFTER

DAA

0-9

0-8

A-F

0-9

0-3

ADD

A-F

0-9

ADC

9-F

A-F

INC

A-F

0-3

0-2

0-9

0-2

A-F

0-3

SUB

0-9

SBC

0-8

6-F

DEC

7-F

0-9

NEG

6-F

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: 1.00

Cycles: 1
States: 4

Flags: S,Z,H,C,P/V

S: set if most significant bit of Accumulator is 1 after operation;
reset otherwise

Z: set if Accumulator is 0 after operation; reset otherwise
H: see instruction
C: see instruction

P/V: set if Accumulator is even parity after operation; reset other
wise

THE ZSO MICROPROCESSOR 61

Copyrighted material

62 THE Z60 MICROPROCESSOR

HALT

The HALT instruction suspends the central processor operation until a subse¬
quent interrupt or reset is received. While in the halt state, the processor will
execute NOPs to maintain memory refresh logic.

0 1110 110

-1-1-1_I-1_I_!_I

Cycles: 1
States: 4
Flags: none

IFF - 0

DI disables the maskable interrupt by resetting the interrupt enable flip-flops
(1FF1 and IFF2). Note: this instruction disables the maskable interrupt during
its execution.

- 1 -1- 1 -1— l — I — l -

11110 0 11
_i_I_l_i—i—i—i—

Cycles: 1
States: 4
Flags: none

IFF - 1

El enables the maskable interrupt by setting the interrupt enable flip-flops
(IFF1 and IFF2). Note: this instruction disables the maskable interrupt during
its execution.

—i—i—i—i—i—i—i—

111110 11

—i—i—i—i_i i. i

Cycles: 1

States: 4
Flags: none

1M0

The IM 0 instruction sets interrupt mode 0. In this mode the interrupting
device can insert any instruction on the data bus and allow the central pro¬
cessor to execute it.

Cycles: 2
States: 8
Flags: none

IM 1

The IM 1 instruction sets interrupt mode 1. In this mode the processor will
respond to an interrupt by executing a restart of location 0038H.

Copyrighted material

Cycles:

States:

Flags:

none

IM 2

The IM 2 instruction sets interrupt mode 2. This mode allows an indirect call
to any location in memory. With this mode, the central processor forms a
16-bit memory address. The upper 8 bits are the contents of the Interrupt

States: 8
Flags: none

SIXTEEN-BIT ARITHMETIC GROUP

ADD HL, ss

HL - HL+ss

The contents of register pair ss are added to the contents of register pair HL
and the result is stored in HL.

—I—l—l-1—l—l—l—

0 0 s s 1 0 0 1

_ i . j _i .. i .j _i i

Cycles: 3
States: 11
Flags: H,N,C

H: set if carry out of bit 11; reset otherwise
N: reset

C: set if carry from bit 15; reset otherwise

ADC HL, ss

HL - HL+ss+CY

The contents of register pair ss are added with the Carry Flag to the contents
of the register pair HL, and the result is stored in HL.

Cycles:

States:

Flags:

—r

1 1

—r

- r

1 0

_1_L

i r

s s

_1_L

S, Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if carry out of bit 11; reset otherwise
N: reset

C: set if carry from bit 15; reset otherwise
P/V: set if overflow; reset otherwise

THE Z80 MICROPROCESSOR 63

Copyrighted material

SBC HL, ss

HL - HL-ss-CY

The contents of the register pair ss and the Carry Flag are subtracted from the
contents of register pair HL, and the result is stored in HL.

Cycles:

States:

Flags:

S, Z, H, N, C, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: set if no borrow from bit 12; reset otherwise
N: set

C: set if no borrow; reset otherwise
P/V: set if overflow; reset otherwise

ADD IX, pp

IX - IX+pp

The contents of register pair pp are added to the contents of the Index
Register IX, and the results are stored in IX.

Cycles:

States:

Flags:

H,N,C

H: set if carry out of bit 11; reset otherwise
N: reset

C: set if carry from bit 15; reset otherwise

ADD IY, it

IY - IY+rr

The contents of register pair rr are added to the contents of Index Register IY,
and the result is stored in IY,

Cycles:

States:

Flags:

H,N,C

H: set if carry out of bit 11; reset otherwise
N: reset

C: set if carry from bit 15; reset otherwise

INC ss

ss — ss+1

The contents of register pair ss are incremented.

0 0 S S 0 0 1 1

64 THE Z60 MICROPROCESSOR

Copyrighted material

Cycles: 1
States: 6
Flags: none

INC IX

IX *- IX + 1

The contents of the Index Register IX are incremented.

-1—I—I-1-1-1-1—

110 1110 1
_i_i_i_i_i_« i

Cycles: 2
States: 10
Flags: none

—I-1-1-1-I-1-1—

0 0 1 0 0 0 1 1
—i—i—i—i—i_i_i_

INC IY

IY - IY+1

Flags: none

DEC ss

ss — ss—1

The contents of register pair ss are decremented.

- 1 - 1 - 1 - 1 - 1 - 1 - 1 —

0 0 S S 1 0 1 1

—i-1—i—i_i_i_i

Cycles: 1
States: 6
Flags: none

DEC IX

IX - IX-1

The contents of the Index Register IX are decremented.

Cycles: 2
States: 10
Flags: none

—r

-T

—r

DEC IY

IY - IY—1

The contents of the Index Register IY are decremented.

- r — t “i" i—i i i-

1111110 1
—I—I—l_I_l_l_I_

—r — r n —i— r —i —i—i

0 0 10 10 11

— i — i —i - j.... j_ i _ i _ I

THE ZSO MICROPROCESSOR 65

Copyrighted material

Cycles:

States:

Flags:

none

ROTATE AND SHIFT GROUP

RLCA

The contents of the Accumulator are rotated left. The content of bit 7 is
copied into the Carry Flag, and also into bit 0.

- 1 - 1 - 1 - 1 - 1 - 1 — i —

0 0 0 0 0 1 1 1

i ■_i_i_i_i_i_

Cycles: 1
States: 4
Flags: H, N, C

H: reset

N: reset

C: data from bit 7 of Accumulator

RLA

The contents of the Accumulator are rotated left. The content of bit 7
copied into the Carry Flag, and the previous content of the Carry Flag
copied into bit 0.

-1—i-1-1—i-1-1-

0 0 0 1 0 1 1 1

_1— - I_I_I_L_J_I_

Cycles: 1
States: 4
Flags: H, N, C

H: reset
N: reset

C: data from bit 7 of Accumulator.

RRCA

The contents of the Accumulator are rotated right. The content of bit 0 is
copied into bit 7 and also into the Carry Flag.

-1-1-1-1-1- 1 - 1 -

0 0 0 0 1 1 1 1

_i_i_i-1-1-1- 1 —

Cycles: 1
States: 4
Flags: H, N, C

H: reset
N: reset

C: data from bit 0 of Accumulator.

RRA

The contents of the Accumulator are rotated right. The content of bit 0 is
copied into the Carry Flag, and the previous content of the Carry Flag is

66 THE ZdO MICROPROCESSOR

Copyrighted material

5>- sr

copied into bit 7.

Cycles: 1
States: 4
Flags: H,N,C

H: reset
N: reset

C: data from bit 0 of Accumulator.

RLCr

The 8-bit contents of register r are rotated left. The content of bit 7 is copied
into the Carry Flag and also into bit 0.

Cycles: 2
States: 8
Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 7 of source register
P/V: set if parity even; reset otherwise

RLC (HL)

(HL)

The contents of the memory address specified by the contents of register pair
HL are rotated left. The content of bit 7 is copied into the Carry Flag and also
into bit 0.

Cycles: 4
States: 15
Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 7 of source register
P/V: set if parity even; reset otherwise

RLC (IX+d)

(IX+d)

The contents of the memory address, specified by the sum of the contents of
the Index Register IX and a two's complement displacement integer d, are
rotated left. The content of bit 7 is copied into the Carry Flag and also into bit
0 .

THE Z60 MICROPROCESSOR 67

Copyrighted material

Cycles:

States:

Flags:

S, Z, H, N, C, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 7 of source register
P/V: set if parity even; reset otherwise

RLC (IY+d)

(lY+d)

The contents of the memory address, specified by the sum of the contents of
the Index Register IY and a two's complement displacement integer d, are
rotated left. The content of bit 7 is copied into the Carry Flag and also into bit
0 .

Cycles:

States:

Flags:

S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 7 of source register
P/V: set if parity even; reset otherwise

RL m

The contents of the m operand are rotated left. The content of bit 7 is copied
into the Carry Flag and the previous content of the Carry Flag is copied into
bit 0.

68 THE Z80 MICROPROCESSOR

Copyrighted material

RRCm

RLr

RL (HL)

RL (IX+d)

RL (IY+d)

Instruction

Cycles

States

RLr

RL (HL)

RL (IX+d)

RL (IY+d)

Flags: S, Z, H, N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 7 of source register
P/V: set if parity even; reset otherwise

The contents of the operand m are rotated right. The content of bit 0 is copied

THE Z80 MICROPROCESSOR 69

Copyrighted material

RRC (IY + d)

Instruction

Cycles

States

RRC r

RRC (HL)

RRC (IX+d)

RRC (IY + d)

Flags: S,Z,H,N,C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 0 of source register

P/V: set if parity even; reset otherwise

RR m

The contents of operand m are rotated right. The content of bit 0 is copied in¬
to the Carry Flag, and the previous content of the Carry Flag is copied into
bit 7.

RR r

RR(HL)

RR (IX+d)

70 THE ZSO MICROPROCESSOR

Copyrighted material

RR (IY+d)

SLA m

Instruction

Cycles

States

RR r

RR (HL)

RR (IX+d)

RR (IY+d)

Flags; S, Z, H, N, C, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 0 of source register
P/V: set if parity even; reset otherwise

An arithmetic shift left is performed on the contents of operand m. Bit 0 is
reset. The content of bit 7 is copied into the Carry Flag.

SLAr

SLA (HL)

SLA (IX+d)

THE Z80 MICROPROCESSOR 71

Copyrighted material

SLA (IY+d)

Instruction

Cycles

States

SLAr

SLA (HL)

SLA (IX+d)

SLA (IY+d)

Flags: S,Z,H,N, C,P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 7

P/V: set if parity even; reset otherwise

SRA m

An arithmetic shift right is performed on the contents of operand m. The con¬
tent of bit 0 is copied into the Carry Flag, and the previous content of bit 7 is
unchanged.

SRA r

SRA (HL)

SRA (IX+d)

72 THE 260 MICROPROCESSOR

Copyrighted material

SRA (IY+d)

Instruction

Cycles

States

SRA r

SRA (HL)

SRA (IX+d)

SRA (IY+d)

Flags: S, Z, H, N, C, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H; reset
N: reset

C: data from bit 0 of source register
P/V: set if parity even; reset otherwise

SRL m

The contents of operand m are shifted right. The content of bit 0 is copied in¬
to the Carry Flag and bit 7 is reset.

SRL r

SRL (HL)

SRL (IX+d)

THE ZSO MICROPROCESSOR 73

Copyrighted material

SRL (IY+d)

Instruction

Cycles

States

SRL r

SRL (HL)

SRL (IX+d)

SRL (IY+d)

RLD

Flags: S, Z, H, N, C, P/V

S: set if result is negative; reset otherwise
Z: set if result is 0; reset otherwise
H: reset
N: reset

C: data from bit 0 of source register
P/V: set if parity even; reset otherwise

a[ 7^H I? <l| 3 0|(HL)

TiJrczr

The contents of the low-order 4 bits of memory location (HL) are copied into
the high-order 4 bits of that same memory location. The previous contents of
those high-order 4 bits are copied into the low-order 4 bits of the Ac¬
cumulator, and the previous contents of the low-order 4 bits of the Ac¬
cumulator are copied into the low-order 4 bits of the memory location (HL).
The contents of the high-order 4 bits of the Accumulator are unaffected.

|—1 -1—1-1-1—l l 1

1110 110 1
_ 1—1—1—1—1—1—1 —

I 1 1— r — 1—1 i 1—

c 0 110 1111

^ —1—1—1—1—1_1_1_

S,Z,H,N,P/V

S: set if Accumulator is negative after operation; reset otherwise
Z: set if Accumulator is 0 after operation; reset otherwise
H: reset
N: reset

P/V: set if parity of Accumulator is even after operation; reset
otherwise

Cycles:

States:

Flags:

74 THE Z80 MICROPROCESSOR

Copyrighted material

RRD

nOtt

A17 413 0 |7 413 0|(HU

nizr

The contents of the low-order 4 bits of memory location (HL) are copied into
the low-order 4 bits of the Accumulator. The previous contents of the low-
order 4 bits of the Accumulator are copied into the high-order 4 bits of loca¬
tion (HL), and the previous contents of the high-order 4 bits of (HL) are
copied into the low-order 4 bits of (HL). The contents of the high-order 4 bits
of the Accumulator are unaffected.

Cycles:

States:

Flags:

—r

—L

S,Z,H,N,P/V

S: set if Accumulator is negative after operation; reset otherwise
Z: set if Accumulator is 0 after operation; reset otherwise
H: reset
N: reset

P/V: set if parity of Accumulator is even after operation; reset
otherwise

BIT SET, RESET AND TEST GROUP

BIT b, r

z - t;

After execution of this instruction, the Z flag in the F register will contain the

Flags: S,Z,H,N,P/V

S: unknown

Z: set if specified bit is 0; reset otherwise

H: set
N: reset
P/V: unknown

BIT b, (HL)

Z - (HL)*

After the execution of this instruction, the Z flag in the F register will contain

Flags: S,Z, H,N,P/V

S: unknown

Z: set if specified bit is 0; reset otherwise
H: set
N: reset
P/V: unknown

THE 280 MICROPROCESSOR 75

Copyrighted material

BIT b, (IX+d)

Z - QX-fd)*

After the execution of this instruction, the Z flag in the F register will contain
the complement of the indicated bit within the contents of the memory loca¬
tion pointed to by the sum of the contents of register pair IX and the two's
complement displacement integer d.

Cycles:

States:

Flags:

S,Z,H,N,P/V

S: unknown

Z: set if specified bit is 0; reset otherwise
H: set
N: reset
P/V: unknown

BIT b, (IY+d)

Z - (IY+d) 6

Cycles: 5
States: 20

Flags: S,Z,H,N,P/V

S: unknown

Z: set if specified bit is 0; reset otherwise
H: set
N: reset
P/V: unknown

SET b, r

r* — 1

Bit b (any bit, 7 thru 0) in register r is set.

Cycles: 2
States: 8
Flags: none

76 THE Z80 MICROPROCESSOR

Copyrighted material

SET b, (HL)

(HU - 1

Bit b in the memory location addressed by the contents of register pair HL is
set.

.iiiii i l—|

110 0 10 11
_I_I_I—I_I_I_l 1

T—l—l—l—I—l—l—

1 1 —b--1 1 0

_L_l_I_I-1_I_I_

Cycles: 4
States: 15
Flags: none

SET b, (IX+d)

(IX+d) 6 - 1

Bit b in the memory location addressed by the sum of the contents of the IX
register pair and the two's complement displacement integer d is set.

Cycles: 6
States: 23
Flags: none

SET b, (IY+d)

(IY+d)* - 1

Bit b in the memory location addressed by the sum of the contents of the IY
register pair and the two's complement displacement integer d is set.

Cycles: 6
States: 23
Flags: none

THE 280 MICROPROCESSOR 77

Copyrighted material

RES b, m

s» — 0

Bit b in operand m is reset.

RES b, r

RES b, (HL)

RES b, (IX+d)

RES b, (IY + d)

Instruction

Cycles

States

RES b, r

RES b, (HL)

RES b, (IX+ d)

RES b, (IY+d)

Flags: none

JUMP GROUP
JP nn

PC - nn

Operand nn is loaded into register pair PC (program counter) and points to
the address of the next program instruction to be executed.

78 THE ZBO MICROPROCESSOR

Copyrighted material

Cycles: 3
States: 10
Flags: none

JP cc, nn

IF cc TRUE, PC - nn

If condition cc is true, the instruction loads operand nn into register pair PC,
and the program continues with the instruction beginning at address nn. If
condition cc is false, the program counter is incremented as usual, and the
program continues with the next sequential instruction.

Cycles: 3
States: 10
Flags: none

JRe

PC - PC+e

This instruction provides for unconditional branching to other segments of a
program. The value of the displacement e is added to the PC and the next in¬
struction is fetched from the location designated by the new contents of the
PC. This jump is measured from the address of the instruction opcode and
has a range of —126 to +129 bytes.

—,-,- 1 —|—|—|—|- 1

0 0 0 1 1 0 0 0
_ I _ I _ I _L II. .1—J

—i—i—i—i—i—i—r

--e-2-

L_J_i_L_i_i_i_l

Cycles: 3
States: 12
Flags: none

THE Z80 MICROPROCESSOR 79

Copyrighted material

JR C,e

If 0=0, continue
If C-l, PC - PC+e

This instruction provides for conditional branching to other segments of a
program depending on the results of a test on the Carry Flag. If the flag is set,
the value of the displacement e is added to the PC, and the next instruction is
fetched from the location designated by the new contents of the PC. If the
flag is reset the next instruction is taken from the location following this in¬
struction.

If the condition is met:

Cycles: 3
States: 12

If the condition is not met:

Cycles: 2
States: 7

Flags: none

JR NC, e

If C=l, continue
If C=0, PC - PC + e

This instruction provides for conditional branching to other segments of a
program depending on the results of a test on the Carry Flag. If the flag is
reset, the value of the displacement e is added to the PC, and the next instruc¬
tion is fetched from the location designed by the new contents of the PC. If
the flag is set, the next instruction to be executed is taken from the location
following this instruction.

If the condition is met:

Cycles: 3
States: 12

If the condition is not met:

Cycles: 2
States: 7

Flags: none

JR Z, e

If Z=0, continue
If Z-l, PC - PC+e

If the Zero Flag is set, the value of the displacement e is added to the PC and
the next instruction is fetched from the location designated by the new con¬
tents of the PC. If the Zero Flag is reset, the next instruction to be executed is

taken from the location following this instruction.

80 THE Z30 MICROPROCESSOR

Copyrighted material

—I—I—I—I—I—I—I—
0 0 1 0 1 0 0 0
—I_I_I_I_I_I_I_

- T~

“i—i

_e_2—

"~r —

_L-

" U L

-J_L_

If the condition is met:

Cycles: 3
States: 12

If the condition is not met:

Cycles: 2
States: 7

Flags: none

JR NZ, e

If Z = l, continue
If Z=0, PC - PC+e

If the Zero Flag is reset, the value of the displacement e is added to the PC,
and the next instruction is fetched from the location designated by the new
contents of the PC. If the Zero Flag is set, the next instruction to be executed
is taken from the location following this instruction.

-1-I-I-1 I I I I

0 0 1 0 0 0 0 0
_I_I_I_I_I_I_I_

—i—

nr"T

-e-2—

-nr-

~ r ~

-J_

If the condition is met:

Cycles: 3
States: 12

If the condition is not met:

Cycles: 2
States: 7

Flags: none

JP (HL)

PC - HL

The PC is loaded with the contents of the HL register pair. The next instruc¬
tion is fetched from the location designated by the new contents of the PC.

—i—i—i—i—i—i— r~l
1110 10 0 1
_L- J—J_I_I_I_I_

Cycles: 1
States: 4
Flags: none

JP (IX)

PC - IX

The PC is loaded with the contents of the IX Register Pair. The next instruc¬
tion is fetched from the location designated by the new contents of the PC.

THE Z80 MICROPROCESSOR 81

Copyrighted material

Cycles:

States:

Flags:

none

1—

i —

i —r

—r

i —r

J_L

i r

J_L

JP (1Y)

PC - IY

The PC is loaded with the contents of the 1Y Register Pair. The next instruc¬
tion is fetched from the location designated by the new contents of the PC.

I II | | I I”

1111110 1
_ l_I_I_l_I_I_I_

—i—i—i—i—i—i—i—

1110 10 0 1

„ I_I_111_I l.-l

none

Cycles:

States:

Flags:

DJNZ, e

The B register is decremented, and if a non 0 value remains, the value of the
displacement e is added to the PC. The next instruction is fetched from the
location designated by the new contents of the PC. If the result of decrement¬
ing leaves B with a 0 value, the next instruction to be executed is taken from
the location following this instruction.

- 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1

0 0 0 1 0 0 0 0
—I—I—I_I_I_l_L

—I—i—i—i—i—i—r

- ■■ - ■ 1 e-2-

—i—i—i—i—i—i_i

If B*0:

Cycles: 3
States: 13

If B=0:

Cycles: 2
States: 8

Flags: none

CALL AND RETURN CROUP
CALL nn

(SP-1) - PC„, (SP-2) - PC Lt PC - nn

After pushing the current contents of the PC onto the top of the external
memory stack, the operands nn are loaded into PC to point to the address in
memory where the first opcode of a subroutine is to be fetched. Note:
because this is a 3-byte instruction, the PC will have been incremented by
three before the push is executed.

82 THE Z80 MICROPROCESSOR

Copyrighted material

Cycles: 5
States: 17
Flags: none

CALL cc, nn

If cc TRUE: (SP-1) - PC„, (SP-2) - PC*, PC - nn

If condition cc is true, this instruction pushes the current contents of the PC
onto the top of the external memory stack, then loads the operands nn into
PC to point to the address in memory where the first opcode of a subroutine
is to be fetched.

If cc is true:

Cycles: 5
States: 17

If cc is false:

Cycles: 3
States: 10

Flags: none

RET

PC t - (SP), PC„ - (SP+l)

Control is returned to the original program flow by popping the previous
contents of the PC off the top of the external memory stack, where they were
pushed by the CALL instruction. On the following machine cycle, the central
processor will fetch the next program opcode from the location in memory
now pointed to by the PC.

- 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1

1 1 0 0 1 0 0 1

I I_I_1 1_I_L_1

Cycles: 3
States: 10
Flags: none

RET cc

If cc TRUE: PC t - (SP), PC„ - (SP + l)

If condition cc is true, control is returned to the original program flow by
popping the previous contents of the PC off the top of the external memory
stack where they were pushed by the CALL instruction. On the following
machine cycle, the central processor will fetch the next program opcode from

THE ZSO MICROPROCESSOR 83

Copyrighted material

the location in memory now pointed to by the PC. If condition cc if false, the
PC is simply incremented as usual, and the program continues with the next
sequential instruction.

r—r—i—i—i—i—i—i—

1 1 ^—cc—►o 0 0

. i .1 i,-, l— j— i—i—

If cc is true:

Cycles: 3
States: 11

If cc is false:

Cycles: 1
States: 5

Flags: none

RETI

Return from interrupt

This instruction is used at the end of an interrupt service routine to

1. Restore the contents of the PC.

2. Signal an I/O device that the interrupt routine has been completed.

The RETI instruction facilitates the nesting of interrupts allowing higher
priority devices to suspend service of lower priority service routines. This in¬
struction also resets the IFFl and IFF2 flip-flops.

Cycles: 4
States: 14
Flags: none

RETN

Return from nonmaskable interrupt

Used at the end of a service routine for a nonmaskable interrupt, the instruc¬
tion executes an unconditional return which functions identically to the RET
instruction. Control is now returned to the original program flow; on the
following machine cycle the central processor will fetch the next opcode from
the location in memory now pointed to by the PC. Also, the state of IFF2 is
copied back into IFFl to the state it had prior to the acceptance of the NMI.

Cycles: 4
States: 14
Flags: none

RSTp

(SP-1) - PC„, (SP-2) - PC*, PC„ - 0, PC* - p

The current PC contents are pushed onto the external memory stack, and the

S4 THE Z60 MICROPROCESSOR

Copyrighted material

page zero memory location given by operand p is loaded into the PC. Pro¬
gram execution then begins with the opcode in the address now pointed to by
PC. The restart instruction allows for a jump to one of 8 addresses as shown
in the table below. The operand p is assembled into the object code using the
corresponding t state.

COH

000

08H

001

10H

010

18H

011

20H

100

28H

101

30H

iio

38H

Cycles:

States:

Flags:

none

INPUT AND OUTPUT GROUP
IN A, (n)

A — (n)

The operand n is placed on the bottom half of the address bus to select the
I/O device at one of 256 possible ports. The contents of the Accumulator also
appear on the top half of the address bus at this time. One byte from the
selected port is then placed on the data bus and written into the Accumulator
in the central processor.

Cycles: 3
States: 11
Flags: none

IN r, (C)

r — (C)

The contents of register C are placed on the bottom half of the address bus to
select the I/O device at one of 256 possible ports. The contents of register B
are placed on the top half of the address bus at this time. One byte from the

selected port is then placed on the data bus and written into register r in the
central processor.

Cycles: 3
States: 12

Flags: S, Z, H, N, P/V

THE Z60 MICROPROCESSOR 85

Copyrighted material

S: set if input data is negative; reset otherwise
Z: set if input data is 0; reset otherwise
H: reset
N: reset

P/V: set if parity is even; reset otherwise

INI

(HL) - (C), B - B-l, HL - HL+1

The contents of register C are placed on the bottom half of the address bus to
select the I/O device at one of 256 possible ports. Register B may be used as a
byte counter, and its contents are placed on the top half of the address bus.
One byte from the selected port is then placed on the data bus and written to
the central processor. The contents of the HL register pair are then placed on
the address bus, and the input byte is written into the corresponding location
of memory. Finally, the byte counter is decremented, and register pair HL is
decremented.

Cycles; 4
States: 16
Flags: S,Z,H,N,P/V

S: unknown

Z: set if B —1 = 0; reset otherwise
H: unknown
N: set

P/V: unknown

INIR

(HL) - (C), B - B-l, HL - HL+1

The contents of register C are placed on the bottom half of the address bus
to select the I/O device at one of 256 possible ports. Register B is used as
a byte counter, and its contents are placed on the top half of the address
bus. One byte is selected and is placed on the data bus and written into the
central processor. The contents of the HL register pair are placed on the
address, and the input byte is written into the corresponding memory loca¬
tion. The byte counter is then decremented and the HL register pair is in¬
cremented. If decrementing causes B to go to 0, the instruction is ter¬
minated. If B is not 0, the PC is decremented by two and the instruction
repeated. Interrupts will be recognized after each data transfer.

If B*0:

Cycles: 5

States: 21

If B=0:

Cycles: 4
States: 16

Flags: S, Z,H,N,P/V

86 THE Z80 MICROPROCESSOR

Copyrighted material

S: unknown
Z: set

H: unknown
N: set

P/V: unknown

IND

(HL) - (C), B - B—1, HL - HL-1

The contents of register C are placed on the bottom half of the address bus
to select the I/O device. Register B may be used as a byte counter, and its
contents are placed on the top half of the address bus. One byte from the
selected port is placed on the data bus and written to the central pro¬
cessor. The contents of the HL register pair are placed on the address
bus, and the input byte is written into the corresponding memory location.
Finally, the byte counter and register pair HL are decremented.

Cycles:

States:

Flags:

1—

i—

”—

1 —

1—

T-

J _

S,Z, H,N,P/V

S: unknown

Z: set if B —1 = 0; reset otherwise
H: unknown
N: set

P/V: unknown

INDR

(HL) - (C), B - B —1, HL - HL-1

The contents of register C are placed on the bottom half of the address bus to
select the I/O device. Register B is used as a byte counter, and its contents are
placed on the top half of the address bus. One byte from the selected port is
placed on the data bus and written to the central processor. The contents of
the HL register pair are placed on the address bus and the input byte is writ¬
ten into the corresponding memory location. The HL register pair and the
byte counter are then decremented. If decrementing causes B to go to 0, the
instruction is terminated. If B is not 0, the PC is decremented by 2, and the in¬
struction is repeated. Interrupts will be recognized after each data transfer.

Cycles: 5
States: 21

If B=0:

Cycles: 4
States: 16

Flags: S,Z, H,N,P/V

S: unknown
Z: set

H: unknown
N: set

P/V: unknown

THE Z80 MICROPROCESSOR 87

Copyrighted material

OUT (n), A

(n) — A

The operand n is placed on the bottom half of the address bus to select the
I/O device. The contents of the Accumulator appear on the top half of the
address bus. Then the byte contained in the Accumulator is placed on the
data bus and written into the selected peripheral device.

Cycles: 3
States: 11
Flags: none

“1-1-1-1-1-1-1—

11010011
—I-1-1-1-1_I_L_

- T"

"T"

— 1 - T"

— n_

—r~

“T -

—» II 1 1,1

—i-, i -

_j_

OUT (C), r

The contents of register C are placed on the bottom half of the address bus to
select the I/O device. The contents of register B are placed on the top half of
the address bus. The byte contained in register r is placed on the data bus and
written into the selected peripheral device.

Cycles: 3
States: 12
Flags: none

OUTI

The contents of the HL register pair are placed on the address bus to select a
location in memory. The byte contained in this memory location is tem¬
porarily stored in the central processor. After the byte counter (B) is
decremented, the contents of register C are placed on the bottom half of the
address bus to select the I/O device. Register B may be used as a byte
counter, and its decremented value is placed on the top half of the address
bus. The byte to be output is placed on the data bus and written into the
selected peripheral device. Finally, the register pair HL is incremented.

S,Z,H,N,P/V

S: unknown

Z: set if B —1=0; reset otherwise
H: unknown
N: set

P/V: unknown

Cycles:

States:

Flags:

88 THE Z80 MICROPROCESSOR

Copyrighted material

OTIR

The contents of the HL register pair are placed on the address bus to select a
location in memory. The byte contained in this memory location is tem¬
porarily stored in the central processor. After the byte counter (B) is
decremented, the contents of register C are placed on the bottom half of the
address bus to select the I/O device. Register B may be used as a byte
counter, and its decremented value is placed on the top half of the address
bus at this time. The byte to be output is placed on the data bus and written
into the selected peripheral device. Then register pair HL is incremented. If
the decremented B register is not 0, the PC is decremented by two and the in¬
struction is repeated. If B is 0, the instruction is terminated. Interrupts will be
recognized after each data transfer.

If B*0:

— r

-T

—r

— r

1 1

_ L

- r

—r

_ L

Cycles: 5
States: 21

If B=0:

Cycles: 4
States: 16

Flags: S,Z,H,N,P/V

S: unknown
Z: set

H: unknown
N: set

P/V: unknown

OUTD

The contents of the HL register pair are placed on the address bus to select a
location in memory. The byte contained in this memory location is tem¬
porarily stored in the central processor. Then, after the byte counter (B) is
decremented, the contents of register C are placed on the bottom half of the
address bus to select the I/O device. Register B may be used as a byte
counter, and its decremented value is placed on the top half of the address
bus. The byte to be output is placed on the data bus written into the selected
peripheral device. Finally, the register pair HL is decremented.

Cycles:

States:

Flags:

S,Z,H,N,P/V

$: unknown

Z: set if B —1=0; reset otherwise
H: unknown
N: set

P/V: unknown

THE Z80 MICROPROCESSOR 89

Copyrighted material

OTDR

The contents of the HL register pair are placed on the address bus to select a
location in memory. The byte contained in this memory location is tem¬
porarily stored in central processors. Then, after the byte counter (B) is
decremented, the contents of register C are placed on the bottom half of the
address bus to select the I/O device. Register B may be used as a byte
counter, and its decremented value is placed on the top half of the address
bus. The byte to be output is then placed on the data bus and written into the
selected peripheral device. Register pair HL is then decremented. If the
decremented B register is not 0, the PC is decremented by 2, and the instruc¬
tion is repeated. If register B is 0, then the instruction is terminated. Inter¬
rupts will be recognized after each data transfer.

_ L

—r

_L_

— r
1

— r

—r
1

— r
1

— T

—L

If B^fcO:

Cycles: 5
States: 21

If B = 0:

Cycles: 4
States: 16

Flags: S,Z, H, N, P/V

S: unknown
Z: set

H: unknown
N: set

P/V: unknown

90 THE Z80 MICROPROCESSOR

Copyrighted material

CHAPTER 4
BUILD YOUR OWN
COMPUTER—Start With

the Basics

The computer to be built from the design described in this book is called ZAP, for
Z80 Applications Processor. Building a computer from scratch is both educational and
utilitarian (and it saves money). I explain each section of the construction process in
detail. Ideally, each step should be tested before proceeding on to the next stage. While
this is not possible in all cases, there is a beneficial side effect in taking this route. Often
good designs fail to work because the level of construction is beyond the ability of the
builder.

I've made the assumption that most hobbyists do not possess sophisticated test
equipment, such as oscilloscopes or logic analyzers, and as a result. I've kept testing
procedures as simple as possible. By dividing ZAP into logical milestones for checkout
and test (and using proven components), problems can be identified at earlier stages
and rectified more easily.

The initial implementation of ZAP will constitute a minimum operable configura¬
tion. It is important that this works before you attempt to add any of the optional pe¬
ripherals. Every effort will be made to familiarize the reader with the components of
each section and the philosophy of design. While it is necessary to assemble all the
components of this minimum configuration completely in order to check proper central
processor operation, comprehensive subassembly pretesting should (I hope) correct
any wiring errors.

The basic ZAP is divided into four major subassemblies: Z80 busing and control,
memory and I/O chip select decoding, memory, and input/output registers. These
major divisions are further divided at the component level. Schematics include a com¬
plete explanation of their logical function, and test procedures are outlined after each
construction presentation.

The Processor

Figure 4.1 is a detailed block diagram of the basic ZAP computer.

I. Z80 Busing and Control Logic
A. Clock Generation

The ZAP computer runs on a 2.5 MHz TTL clock. Unlike the 8080A, the
Z80 requires only a single-phase clock and can be driven from DC to
2.5 MHz (the Z80A runs to 4 MHz). Figure 4.2 illustrates the basic timing
cycle of the computer. >

Each basic operation (M*) of the computer is completed in three or six
clock periods. Figure 4.2 shows a typical instruction cycle which consists of
three machine cycles: fetch, memory read, and memory write. After the op¬
code of the instruction is fetched during Ml, the subsequent cycles move the
data between memory and the central processor.

Figures 4.3a and 4.3b illustrate two possible clock designs for the Z80. Both
clock circuits have a 330 ohm pull-up to +5 V. This will satisfy both the AC
and DC clock signal requirements, but it is best to use a separate inverter gate

BUILD YOUR OWN COMPUTER 91

Copyrighted material

section to drive the pull-up whatever the oscillation technique.

The crystal controlled circuit of figure 4.3a is preferred if consistent execu¬
tion time is to be maintained. Thus, the circuit of figure 4.3b, though other¬
wise acceptable, should be avoided if the computer is to be used as an event
timer. It can serve a very useful purpose in the development stages, however,
by allowing the user to slow the clock down (by increasing the values of R
and C) to a rate where it is possible to directly monitor the central processor
operation. Should it ever be necessary to single-step the clock, the circuit in
figure 4.4 should be used. Given the multiple clock cycles necessary to ex¬
ecute a single instruction, it would take a lot of button pushes to follow a pro¬
gram through execution.

A much easier diagnostic method would be to use an instruction single¬
stepping circuit. The circuit, shown in figure 4.5, is not part of the finished
schematic of ZAP because it is necessary only if the builder has a problem
and needs to follow the execution of a program instruction by instruction.
This single-stepping function is accomplished by using the control signals
generated by t he Z8 0 du ring program execution. The t wo parti cular signals
of concern are Ml an d WA IT. Ml is an output, and WAIT is an input.
As shown in figure 4.6 , Ml goes to a logic 0 level at the beginning of every
instruction fetch cycle. Ml signifies that the computer has completed one in¬
struction and is starting on the next. The objective is to stop the microproces¬
sor before it executes this next instruction.

The WAIT input to the Z80 does just that. A logic 0 level applied to this in¬
put will suspe nd the program execution of the computer and indefi nitely h old
it in the Ml cycle. During T 2 , the central processor samples the WA IT in¬
put line with the trailing edge of the clock. If, at this time, WAIT is at a
logic 0 level, an additional wait state will be entered, and the li ne will be
sampled again. The central processor will hang in this mode until WAIT is
raised to a logic 1. It should be noted that this is not a computer halt com¬
mand.

The real purpose behind these signals is to allow the relatively slow mem¬
ory and peripherals to be used with a very fast central processor. Extra wait
states should be inserted only when necessary for the central processor to ac¬
cess these devices. The effect is to synchronize the timing between the central
pro cessor a nd its I/O devices. The circuit of figure 4.5 allows us to control
the WAIT state and to execute only one ins truction with each press of the
button. The output at IC1, pin 8 (the WAIT input) is normally low, causing
an indefinite wait. When the button is pushed, a single debounced pulse
clocks IC 2, which is a D-type flip-flop. The duration of this pulse (the time
you hold the button down) is irrelevant, because the flip-flop is edge trig¬
gered and is only c oncerne d with the leading edge. Pressing the button sets
IC 2 and raises the WAIT line. No longer told to wait, the central processor
executes the instructio n at f ull clock speed. As it is about to start the next in¬
struction fetch cycle. Ml goes low as before, and triggers the one-shot.
When it fires, IC 3 resets IC 2 and returns the central processor to a wait con¬
dition until the next time the button is pushed.

The single-step feature isn't of much use in a computer unless there is some
way to monitor the contents of all the registers and to determine what the
computer is trying to do at any one time. To accomplish this, ZAP must be
completely operational and be running a breakpoint-monitor program which
allows the user to single-step with a software routine. We'll discuss such pro¬
grams later.

This fact is of small consolation to a person with a partially debugged com¬
puter or hardware error that keeps side-tracking large programs. While it
would be nice to see all the register contents, it is virtually impossible to do so
without having a central processor that can run a dump and display routine.
This cannot be done using the hardware stepping circuit of figure 4.5. It is
possible, however, to look at the contents of the address and data buses while
the central processor is stopped. This should give a good indication as to

92 BUILD YOUR OWN COMPUTER

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whether the computer is operating properly.

Many instruments can be used to read the TTL levels on the buses. A scope
or high-impedance voltmeter can be used, but a visible display of the bus
contents is a better idea. The circuits in figure 4.7 show simple methods to
display the contents of the address and data buses. The circuits are included
as aids and are not necessary for the operation of ZAP.

Basically, the circuit of figure 4.7a is a simple LED driver that is duplicated
16 times for the address bus and 8 times for the data bus. Because the Z80
should drive only one TTL load from each output pin (bus driver inputs are
already attached), any display drivers of this type must be attached on the
output side of the bus drivers. This circuit will serve as a rudimentary front
panel for any builders who feel a computer isn't complete without flashing
lights.

Sometimes the need arises to monitor a single point in a circuit and watch
for level changes. While the LED driver of figure 4.7a would detect a slowly
changing level, it would miss short pulses such as Ml. To monitor the occur¬
rence of such events, especially if no oscilloscope is available for testing pur¬
poses, it is advisable to build the circuit in figure 4.7b. This simple logic
probe is adequate for most applications, but care must be taken in its use. It
cannot detect an open circuit and the pulse detector only triggers on the
negative edge of any transition. Should that present any problems, add the
optional circuit using the 7486; that will allow it to detect either edge.

The logic probe or similar logic level detector (scope, DVM, VOM, etc.) is
necessary to statically test the subassemblies.

Figure 4.1 A block diagram of a minimum ZAP system.

Figure 4.2 An example of timing during a typical instruction cycle.

BUILD YOUR OWN COMPUTER 93

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CRYSTAL

2.5MHz

VALUES Of R AND C
SET OUTPUT FREQUENCY

♦ 5V

CLOCK

Figure 4.3 Typical 2.5 MHz clock circuits for the Z80.

a) With crystal control.

b) With a variable-frequency oscillator.

Figure 4.4 A single-cycle clock-generator circuit.

94 BUILD YOUR OWN COMPUTER

Copyrighted material

♦ 5V
A

WAIT

2 80 PIN 24

Figure 4.5 An instruction single-stepping circuit.

*1 CYCLE

«_D_ V V .■ / \

Figure 4.6 Instruction operation-code fetch (Ml) timing.

BUILD YOUR OWN COMPUTER 95

Copyrighted material

INPUT>

+ 5V
A

♦ 5V

330ft

LEO

INPUT

0 LIGHT OFF
1 LIGHT ON

♦ 5V

330ft

LEO

2N2222
OR EQUAL

INPUT>

♦ 5V
A

390ft

LOGIC T

♦ 5V

39Cft

♦ 5V

33K

/ 1 ♦

• w w

Jii

IC2

74121

0.1 SEC

FROM
IC1 PIN 2

♦ 5V
A

390ft

"PULSE'

+ 5V EDGE DE7ECTOR FOR SLOW PULSES

INSEPT AT POSITION 'A' ABOVE (OPTIONAL)

3 4

IC2 PIN3

Figure 4.7 Typical LED drivers and a simple logic probe to monitor logic level changes.

a) Visible logic level indicators that can be attached to the address and data buses to provide
a display.

b) A simple logic probe.

96 BUILD YOUR OWN COMPUTER

Copyrighted material

B. Reset Circuit

Often ignored, the reset function is one of the most necessary controls of a
computer. Its importance is immediately recognized when running an incor¬
rectly executing program. The reset command on the Z80 stops execution and
loads the program counter with 00 hexadecimal (the lowest memory
address). This allows the programmer to restart the program. When com¬
bined with the instruction single-stepping circuit previously outlined, pro¬
grams may be started, stopped, and started again at any time.

A reset input can be manual, automatic, or a combination of both. Figure
4.8a is a standard push-to-reset circuit. Its output is normally high until the
button is pushed, and then it goes low. The Z80 will remain reset for as long
as the button is held and will only begin to execute again when released.
Manual reset is a necessity for initial program checkout, and this circuit is
employed in the basic ZAP.

When computers are used in applications where no human attendant is
present, such as a traffic light controller, the manual reset cannot be used; an
automatic reset must be employed instead. Figure 4.8b is the circuit of a total¬
ly automatic power-on reset. When power is first applied to the computer,
the 10 mF capacitor will be completely discharged. The resultant logic 0 level
on the input of the 7404 pin 1 will be maintained for approximately 50 ms,
long after the +5 V supply has powered up the rest of the computer. The
long charging rate of the capacitor will, in turn, generate a logic 0 (a reset
condition) to the computer until the input level rises to approximately 2 V (a
TTL logic 1). Once full power is applied, the time it tak es the reset circuit to
reach 2 V will constitute about a 35 ms power-on Reset pulse. Resetting the
machine would require turning the power off.

Manual and automatic reset are combined in figure 4.9. This circuit allows
the computer to start program execution immediately after power is turned
on. The program can be stopped and restarted by pressing the reset button.
Slightly different components and additional functions are included in this
diagram. Schmitt-triggered inverters (7414s) increase the reliability of the de¬
sign. When the power is turned off, the use of a diode to discharge the capaci¬
tor quickly assures that a pulse will be generated if power is suddenly reap¬
plied. Because power line glitches are usually short in duration, the discharge
rate of the capacitor has to be fast enough not to miss generating a reset pulse
once power is restored.

While this reset circuit is not necessary for initial computer check-out, it
should eventually be employed if ZAP is to be expanded to include any of the
options outlined later. To synchronize the central processor and peripherals,
they should be tied into the reset signal from this circuit.

a) A manual reset circuit.

b) An automatic power-in reset circuit. b)

BUILD YOUR OWN COMPUTER 97

Copyrighted material

♦ 5V

RESET
TO OTHER

peripherals

RESET

TO 280 PIN 26

TO OTHER PERIPHERALS

Figure 4.9 A circuit to combine manual and automatic reset functions.

C. Address Bus and Control Output Buffering

The Z80 has the ability to directly address 65,536 (often called 64 K) indi¬
vidual bytes of program memory and 256 individual input and output ports.
Because the microprocessor is a binary device, it is only natural that this ad¬
dress be binary. There are 16 binary address lines labeled AO thru A15. AO is
the LSB (least significant bit), and A15 is the MSB (most significant bit).

The logic levels on this bus are not arbitrary. The control section of the
central processor sets the program counter to the next instruction to be ex¬
ecuted, and on the fetch cycle, it places the program counter contents on the
address bus. During I/O instructions, additional timing cycles place the I/O
device address on the 8 least significant bits (AO thru A7). Because this bus
has to drive the inputs of many parallel devices, all of which draw some input
power, the address bus must have an output current that will meet the load
demand. The Z80 by itself can sink 1.8 mA maximum or one TTL load on
each pin. This is no problem if the designer uses low power memories and pe¬
ripheral interface chips. These are expensive devices, and their use would not
necessarily serve to educate the builder in the same way as configurations of
less complex circuits.

Using lower density ICs and TTL devices for decoding functions is less ex¬
pensive but requires considerably more power from the bus. The following
table lists the input loading of various devices:

Device

Worst case input current

Standard TTL (7404,7442, etc)

1.6 mA

Low-power Schottky TTL (74LS04,etc)

0.18 mA

2708 (1KX8 EPROM)

10 nA

2114 (1KX4 programmable memory)

10 /xA

2716 (2KX8 EPROM)

10 nA

2102 (1KX1 programmable memory)

10 nA

8212 (8-bit latch)

0.25 mA

8T97 (6-bit driver)

1.0 mA

It is easy to see that the real power eaters are TTL devices. Low-power
Schottky TTL (LSTTL) devices can be substituted throughout the ZAP com¬
puter. They save power at slightly additional cost, but the circuit has suffi¬
cient power to support straight TTL. If LSTTL is substituted, it must be sub¬
stituted throughout.

The loading caused by memory, especially with only 2 K bytes in the basic
ZAP unit, is insignificant. With 1.8 mA drive current available from the Z80,
we could use LSTTL for the I/O and memory address decoding but would
have to limit the fanout (total input connections) on each address line to 9
LSTTL inputs. This is sufficient for the basic ZAP and would probably be an

98 BUILD YOUR OWN COMPUTER

Copyrighted material

acceptable procedure, but it is not recommended.

The first time a user attaches the logic probe (figure 4.7b) to an unbuffered
address line, the computer may die. The load presented by the probe, as well
as by the other circuitry, will exceed the drive capability of the bus. It's im¬
portant that the monitoring devices not impede circuit operation.

Rather than try to optimize the design to a degree that forces the user to be
aware of every /xA (microampere) consumed by test probes and LED drivers,
it's easier to add buffering that increases the bus output power to a point
where loading is not an important factor. This is the philosophy behind ZAP
busing, and as a side benefit, it will provide enough power to expand ZAP to
64 K should the user ever desire to do so. It also allows the user to add his
own TTL circuitry without becoming overly concerned with bus loading.

To achieve high power output from the address bus, a buffering device
(called a non-inverting bus driver) is used. The AO thru A15 outputs of the
Z80 make only one connection: to the drivers' input. All other devices that
use the address are attached to the output of the drivers.

Figure 4.10 is the diagram and truth table of the 8T97 bus driver. (An
equivalent bus driver is the 74367.) This three-state device is capable of sink¬
ing 48 mA and can accommodate any combination of TTL, LSTTL, and
memory connections a user would want to make. The final address bus con¬
figuration is shown in figure 4.11.

The three-state function of the 8T97 is controlled by the BUSAK signal.
This signal turns over control of the address bus to an exter nal device during
direct memory access operations. In a non-DMA situation, BUSAK is high
and the 8T9 7 passes a ll outputs from the Z80. When a DMA request is ac¬
knowledged, BUSAK goes low, putting the 8T97 in a high impedance output
mode. This facility allows memory to be written into or read by an external
device and is usually reserved for high-speed operations that are faster than
the central processor can achieve.

CONTROL INPUT
0I$4

DATA IN

CONTROL INPUT
0I$ 2

♦ 5V

v cc I

ots 4

8T97 |

74367

'"1

OUT] I

in 2

out 2 I

° ut 3

IN 3

IN 4

0UT 4

*"•

OUTj

ourJ

,n 6

0IS 2

CND |

.BUTTERED
• DATA OUT

TRUTH TABLE

OIS 4

0 is 2

data

INPUT

OUTPUT

HIGH Z

X • OON’T CARE

HIGH Z IS A TRISTATE OUTPUT

CONDITION

Figure 4.10 The pinout and truth table of an 8T97/74367 bus driver.

BUILD YOUR OWN COMPUTER 99

Copyrighted material

16-BIT BUFFERED
TRISTATE ADDRESS BUS

'OUT TYPICAL 48mA

Figure 4.11 The final buffered address bus configuration.

D. Data and Control Bus

The fourth and last area of direct central processor connections is the data
bus and the remaining lines of the control bus. The reason for buffering the
data bus is similar to the argument for the address bus with one exception—
the data bus is bi-directional.

A bi-directional bus means, of course, that data flows in both directions.
When the Z80 is writing a byte of data into a memory location, the data
flows from the central processor to memory. When the central processor is
reading a memory byte, data flows from memory to the central processor.
The bi-directional nature of the data bus requires that the bus drivers be
either bi-directional internally, or attached in such a way that the same func¬
tion is performed.

One way of making this bi-directional driver is to use two 8212s. The 8212
(figure 4.12) was originally conceived and produced by Intel as an 8-bit
latched input or output port. The 8212 can be latched continuously so that
data flows through it, or it can be turned off to block the flow. It is well
suited to this application because it has a three-state output.

Two 8212s (figure 4.13) are wired in opposite directions. IC 6 directs data
from the central processor toward memory, while IC 7 channels data into the
Z80. Control is exercised through a single line connected to the RD control
signal of the central processor. RD is normally low except during write oper¬
ations. This causes IC 6 to be off, in a three-state mode, and IC 7 on, which
allows jdata from memory or I/O devices to reach the central processor.
When RD goes high during a write operation, the process is reversed; IC 6
turns on and IC 7 turns off. It is only necessary to use the RD line to control
data direction. We're assuming, of course, that when the central processor
isn't writing data, it must be reading it. While not exactly true, the concept

100 BUILD YOUR OWN COMPUTER

Copyrighted material

works well enough in practice, and the two 8212s are connected schemati¬
cally as in figure 4.14.

It is not absolutely necessary to use 8212s to perform this function. Either
8T97s or 74367s work equally well but take 4 IC packages. If you don't mind
the extra wiring and have a source for 8T97s, they can be wired as illustrated
in figure 4.15.

The final connections to the central processor to be discussed are the con¬
trol bus signals, shown in figure 4.16. They coordinate peripherals and chan¬
nel data and addresses into and out of the central processor at the proper
times. Each was briefly explained on the 280 pinout. Exact timing will be
detailed when we discuss attachments of memory, I/O, and enhancements to
ZAP. For the time being, unused control inputs are tied high (through
resistors) to inhibit false triggering.

The output lines are buffered for the same reasons as was the address bus.
Furthermore, because this is a development computer, with expansion in
mind, both the inverted and noninverted control signals are brought out to
the user.

The areas discussed thus far are combined into a single diagram (figure

62/2

LOGIC DIAGRAM

4.17) called the Z80 bus and control diagram.

PINOUT

♦ 5V

MQ MOOE
STB STROBE
OSl DEVICE SELECT l
DS2 0EVICE SELECT 2
INT INTERRUPT

CLR CLEAR

Figure 4.12 The pinout and logic diagram of the
8212 8-bit input/output port.

BUILD YOUR OWN COMPUTER 101

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♦ 5V

Figure 4.14 A schematic diagram of two 8212 8-hit latches configured as bi-directional data bus
drivers.

102 BUILD YOUR OWN COMPUTER

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• 5V

T,«

Figure 4.16 Control input connections and output
buffering of the basic ZAP design.

BUILD YOUR OWN COMPUTER 103

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104 BUILD YOUR OWN COMPUTER

Copyrighted material

MREQ MREQ IOREQ l/OREQ

E. Testing

Insert all ICs except the Z80 and turn on the power. Each section is then in¬
dividually tested as follows:

Clock — Testing the 2.5 MHz clock of figure 4.3a will require an oscilloscope
or frequency counter to register the exact clock rate. Using the logic
probe from figure 4.7b to monitor this clock rate would light all three
LEDs. This indicates that the clock functions, but it will not indicate the
rate. A similar test can be performed on figure 4.3b.

Single Cycle — The logic probe (without the addition of the 7486 edge
detector) is perfect for checking the single-cycle circuit of figure 4.4.
With the probe on section C pin 8, the indication should be low. Press¬
ing and holding the button down should change the indication to a high
level and cause the "pulse" LED to flash once. Releasing the button
should not flash the pulse indicator as it returns to its initial logic condi¬
tion.

Single Step — With the switch in the single-step mode position (figure 4.5),
take a clip lead and momentarily ground IC 3, pin 3. The output at
IC 1, pin 8 should be low. Pressing the single-step button will cause this
output to go high. It will stay high until IC 3, pin 3 is momentarily
grounded again. Check out the pushbutton debouncing circuit (which
consists of IC 1 sections a and b) in the same manner as you did the
single-cycle test. Finally, with the switch on the run mode, IC 1, pin 8
should always be high.

Power-on Reset — The circuits of figures 4.8a and 4.8b should have a nor¬
mally high output. When power is first applied to figure 4.8b, or the
button pressed in figure 4.8a, the output should go low. Either situation
will cause a logic low level to occur from the circuit of figure 4.9.

Address Bus Drivers — The Z80 should not be inserted! With IC 9, pin 5
grounded, all outputs of ICs 3, 4, and 5 on schematic figure 4.11 should
appear high. In actuality, this will be the three-state output mode and
the proper test equipment will register them as open circuits. Tying
IC 9, pin 5 to +5 V through a 2.2 K resistor will turn on all the bus
drivers. Their outputs will all be iogic high levels. Successively ground¬
ing the AO thru A15 lines at the Z80 connector should result in a low-
level indication on the respective buffered output line. When all 16 lines
can do this successfully, the address bus checks out.

Bi-directional Data Bus — The data bus is tested in a similar manner except
that the procedure is done twice—for data flow in either direction.
Grounding IC 8, pin 1 (figure 4.14) simulates a read condition. Data
should flow from right to left. Applying ground and +5 V (through a
2.2 K resistor) alternately to the data input pins of IC 6 should produce
similar levels on DOl thru D08 of IC 6. Raising IC 8, pin 1 to +5 V
allows similar data transfer, but only from left to right this time.

Control Bus — Referring to the schematic of figure 4.16, testing is simply a
case of applying a known logic level to the input side of the series in¬
verters and noting the output levels one gate at a time. For example, if
Z80 pin 19 was a logic low, IC 9, pin 2 would be a logic high and con¬
versely, IC 9, pin 4 would be low. Each inverter section which the
signal passes through inverts the signal.

II. Memory and I/O Decoding

Before we can utilize the memory or I/O devices we must learn how the Z80 address¬
ing works. Remember, the address FF hexadecimal could refer to memory, or an input
or an output port. The computer must have the ability to differentiate among the three

BUILD YOUR OWN COMPUTER 105

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possible meanings.

The control outputs of the Z80 contain the necessary routing information, and by
properly gating them together, the correct signals are obtaine d. For b a sic I/O and m em¬
ory o perations, the four signals of particular interest are MREQ, IORQ, RD, and
WR. Their definitions are as follows:

A. MREQ

Memory Request. Wh enever a transaction occurs between the central proces¬
sor and memory, the MREQ line goes to a logic 0.

B. iORQ

Input/Output Request. Whenever a transaction occurs betwee n the central
processor and either an input port or an output port, the IORQ line goes to a
logic 0.

C. “RD

Read Request. Whenever the centra l processor reads input data from either
memory or an input port, the RD line goes to a logic 0.

D. WR

Write Request. Whenever the centra l processor is writing data to either mem¬
ory or to an output port, the WR line goes to a logic 0.

_To dif feren tiate between input and output ports during I/O instructions, IORQ ,

RD, and WR are gated together as shown in figure 4.18. In a similar manner, MREQ,
RD and WR are gated during memory transfers as shown in figure 4.19. Unlike the
I/O decoding, but similar to the address bus driver discussed earlier, a memory-read
condition does not have to be decoded. It is assumed that when the memory is not in a
write mode, it is in the read state. _

The resulting thre e decode d strobes define the op erations of Input Port Read (IORD),
Output Port Write (IOWR), and Memory Write (MEMWR). If only three functions
were required in your particular computer configuration, then no other decoding
would be necessary. Such a computer would have one input port, one output port, and
one bank of memory. To alleviate this problem, additional decoding of I/O and
memory is necessary so that these control strobes can serve more than a single device.
With the extra circuitry, the Z80 can independently address 256 input and output ports
and 64 K bytes of memory.

During an I/O request (either input or output), the 8-bit binary address of the par¬
ticular I/O port appears on lines AO thru A7 of the address bus. An explanation of ad¬
dress coding is shown in figure 4.20. Additional examples are illustrated in figure 4.21.

Using this information, if an instruction were to designate output port 7 as its
destination, then the circuitry of figure 4.22 could be used. When a code of 0 07 octal
(07 hexadecimal or 00000111 binary) appears on the address lines with an IOWR
strobe, the signals present on the data bus would be stored in an 8-bit register as output
data.

f _

iORQ
WR

CPU ,

SIGNALS \

iORQ GOES TO LOGIC 0 ON AN INPUT/OUTPUT OPERATION

WR GOES TO LOGIC 0 WHEN THE CPU ATTEMPTS TO WRITE DATA TO AN
OUTPUT OR MEMORY

RD GOES TO LOGIC 0 WHEN THE CPU ATTEMPTS TO READ DATA FROM
MEMORY OR AN INPUT DEVICE

Figure 4.18 Input/output read and write decoding.

106 BUILD YOUR OWN COMPUTER

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Figure 4.19 Memory read and write decoding.

BINARY WEIGHTING

TYPICAL PORT CODE

HARDWARE DECODER

A 7
A 6
A 5

A 4
A3
A 2
A 1

2 7 X N • 128 X \

2 6 x ti . 64 x 1

2*XN • 32 X 0

2 * XN • 16X0

23 KN • 8X0

22 XN • 4X1

2* XN • 2X0

2° XN • 1X1

N » *0“ OR 'I* LOGIC LEVEL

Figure 4.20 An explanation of input/output address codes.

OECODEO
“LT
STROBE

Figure 4.21 Address decoding logic.

a) For address FF lt .

b) For address 00 t ♦.

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NOTE: DA TA F LOW IS FROM THE CPU TO THE OUTPUT PORT
OURING IOWR OPERATIONS.

Figure 4.22 A possible method for decoding a single 8-bit output port address. The circuit Is for a 007,
device code.

I/O Decoding

Of course, ZAP needs more than 1 port, even as a basic system. In fact, if it is ex¬
panded to include some of the optional peripherals, it will require 6 or 8 ports.
Decoding these additional ports need not require 8 separate circuits like figures 4.20 or
4.21. By incorporating a 4 to 10 line demultiplexer into the design, 8 port strobes can be
derived. Th e circu it of fig ure 4.23 can be used for either input or output port decoding
(by selecting RD or WR) and is addressed for 000 octal to 007 octal. It works by select¬
ing either of the two unconnected outputs (IC 3, pin 9 or 10) when an undecodable ad¬
dress is presented on the address bus. A3 thru A7 still must be treated in the same man¬
ner as that presented in figure 4.20, but A0 thru A2 serve as the 7442 address inputs.
These 3 bits will designate 1 of 8 possible lines when IC l's output goes low.

Duplicating this circuit to provide 8 separate input and output stobes (addressed 000
thru 007) would require a total of 7 chips. The number of chips can be reduced to 3 if
we take a little poetic license with the design. So far, we have decoded all 8 bits of the
I/O portion of the address bus, making our decoder select 1 of 256 or, as in the
previous circuit, 8 of 256. In either case, only the designated addresses are of any im¬
portance; all others are meaningless. For all practical purposes we could decode lines
A0 thru A2 and ignore the rest. A circuit that does just that is shown in figure 4.24.

4 The difference between this circuit and those previously described, besides having
fewer chips, is that this one requires an intelligent user to recognize the advantages and
disadvantages of taking such liberties. As in figure 4.23, this circuit decodes ports 000
octal thru 007 octal. What the user should realize, however, is that it also decodes 010
thru 017 and 020 thru 027, etc. The 3 LSB (least significant bits) repeat every 8 ad-

108 BUILD YOUR OWN COMPUTER

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dresses. This is not a problem as long as the user is aware of repetitive addressing and
watches his programming. Should more than 8 stobes be required, the 7442 can be re¬
placed with a 74154 (4 to 16 decoders). This will give 16 I/O port strobes that repeat
every 16 addresses.

IC 2

PORT 7 IT
PORT 6 If
PORT S *lf
PORT 4 U
PORT 3 IT
PORT 2 IT
PORT 1 U
PORTO IT

Figure 4.23 A formal input/output port address decoding method that decodes all 8 address lines.

♦ 5V

I/O READ

INPUT

STROBES

I/O WRITE

OUTPUT

STROBES

Figure 4.24 >4 method for decoding input/output strobes with a reduced amount of circuitry.

BUILD YOUR OWN COMPUTER 109

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Memory Decoding

Decoding the memory address bus is accomplished in a similar manner. It is inadvis¬
able to take the same tack and allow repetitive memory addressing because there is
more likelihood of error. Even though 16 lines are involved, in actual application,
memory decoding turns out to be less complicated. ZAP uses 1 K X 8-bit banks of
programmable memory and 1 K-byte erasable read-only memory. Both of these de¬
vices require 10 address lines to define the 1 of 1024 locations in each bank. This leaves
only 6 lines that have to be individually decoded to define any 1 K block of memory.
Figure 4.25 illustrates how this can be accomplished. A 7442 (4- to 10-line decoder) is
used to generate 8 separate chip-select lines. Because the address lines of the 7442 are
tied to A10 thru A12, each strobe pulse will have a boundary of 1 K. It is not by chance
that 1 K X 8 was chosen as the memory capacity of each bank.

♦ 5V

Figure 4.25 Memory bank decoding for 8 K of memory.

While the basic configuration of ZAP provides decoding for 8 K of memory and 8 in¬
put and output ports, not all of these chip selects and port strobes are used. The extra
lines are left for expansion. Figure 4.26 is a completed schematic of the I/O and mem¬
ory decoder for the builder to add to the circuit in figure 4.17.

120 BUILD YOUR OWN COMPUTER

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Testing

After you have added the components of figure 4.26 to figure 4.17, you are ready to
test the memory and I/O decoding. Insert lCs 10,11, 12,13, and 14, but don't insert
IC 20 yet. ICs 1, 3, and 9 should remain inserted from the previous test. The Z80
should still be left out. The logic level at the D address input of each of the 7442s (ICs
12,13, and 14) should be high. Pulling out ICs 8 and 9 (with power off) will cause this
input to immediately change to a logic low level.

Next, ground pins 30, 31, and 32 and tie 23 high on the Z80 socket. With the address
bus buffers enabled, and a 000 address jumpered on A0 thru A2, a chip-select low
should appear on the lowest strobe address. In this case, pin 1 of ICs 13 and 14 should
be low and the other strobe lines high. Changing the 3 jumpers on A0 thru A2 will
enable other device chip-select strobes. The memory bank decoder works the same way
except that the jumpering should be applied to address lines A10 thru A12.

After testing, insert all chips except the Z80.

♦ 5V

vcs?

MCS6

MCS5

MCS4

MCS3 /

MCS2

MCS1

MEMORY

BANK CHIP

SELECT LINES

MCSQJ

OS7Ro')

DS6RQ
DS5RO
DS4R0
0S3R0
DS2RD
DS1RQ
DS0RDJ

I/O READ
PORT SELECT
STROBES

CS7WR

DS6WR

DS5WR

DS4WR

DS3WR

DS2WR

OS1WR

DS0WR

I/O WRITE
PORT SELECT
STROBES

Figure 4.26 The memory and input/oulput decoding section of ZAP.

a) Memory bank chip-select strobes.

b) Input/output device chip-select strobes.

BUILD YOUR OWN COMPUTER 111

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III. Memory

Of course, a major consideration for any computer system is memory. Both program
instructions and data must be stored and recalled at the appropriate time so the com¬
puter can perform its function. Even though the Z80 central processor has a quantity of
8-bit storage registers, these can be only used for temporary manipulation of data and
cannot store program instructions. Program instructions must be stored in external
memory elements.

The external memory may be divided into two broad classes: ROM (read-only mem¬
ory) and RWM (read/write memory). ROM is used to store specific, unchanging pro¬
gram steps or data. The contents of thes€ memory locations are considered permanent
and cannot be easily changed. Read/write memory, on the other hand, is used to store
data that changes while the computer is operating. Examples would be the results of
calculations or programs that change frequently. For either type of memory, the
ultimate function is still the same: to provide, on demand, either an instruction for ex¬
ecution or a location where data may be stored.

Read-Only Memory

ROM (read-only memory) is an important part of the computer system. ROM func¬
tions as a memory array whose contents, once set by special programming techniques,
cannot be altered by the central processor. There are few exceptions to this rule.

By its nature, ROM is non-volatile. When power is turned off, the program contents
are not lost. Reapplication of power allows immediate program execution.

Within this basic category of ROMs there are three subcategories — ROM, PROM,
and EPROM — which are defined more by usage and application than their names
might imply.

ROM — Read-Only Memory

This is storage which can be written into only once. The information is fixed and
cannot be changed. A ROM is usually mask programmed by the manufacturer
and is bought with a preset bit pattern. These types of ROMs are considered to be
custom programmed.

PROM — (User) Programmable Read-Only Memory

This storage can also be written into only once and the information is fixed.
These devices are typically bipolar fusable link PROMs, which are programmed
by the user rather than the manufacturer. ROMs and PROMs do not generally
use the same semiconductor construction technology. Storage is much denser on
a ROM than on a PROM, and cost-per-bit is generally lower on a ROM.

EPROM — Erasable-Programmable Read-Only Memory
This device combines the best parts of a ROM and a PROM. When received from
a manufacturer, all storage locations are unprogrammed. Using a special inter¬
face, the EPROM can be programmed by the user as a PROM would be, with the
result utilized as a ROM. If the EPROM content must be changed, it can be erased
and reprogrammed. Depending upon the particular device, an EPROM can be
either electronically alterable (often differentiated by the separate abbreviation
EAROM) or ultraviolet erasable. The latter is sometimes called a UVEPROM, but
is more often just called an EPROM. They are easily recognizable because they
have a quartz window over the integrated circuit. This window is transparent to
ultraviolet light and facilitates erasure.

While there can be considerable discussion as to the merits of each option, all ROMs
perform the same ultimate function. For each independently addressable location,
there is specific stored-bit pattern. Only the processor can determine whether this is
data or an instruction. The method of storage is the same in either case. Figure 4.27
details the block diagram of a ROM.

A ROM is simply a logical block which, under program control, provides a preset

112 BUILD YOUR OWN COMPUTER

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pattern. Figure 4.28 is a 3-bit read-only memory. When switch SWl is closed (the posi¬
tion it would take when the central processor wanted the stored information), the 3-bit
code of “101" would appear at the outputs. The diode grounds the input signals to the
7404 inverters when SWl is closed. Expanding to more than 3 bits is simply a matter of
adding more diodes, resistors and buffer stages. Such a circuit is referred to as a diode-
matrix ROM and in this case would be a 1-line by n-bit ROM.

A 3-bit memory is not much use. This concept can easily be expanded to 16 bytes by
adding an address decoder as diagrammed in figure 4.29. A completed schematic with
the diodes specifically arranged to perform a simple 9-byte program is illustrated in
figure 4.30. This short test program will be used later during the checkout phase.

The diode-matrix ROM is presented for its educational value only. This is not a
method that should be employed in the ZAP computer. Realizing that there are inte¬
grated circuits that would successfully fulfill the requirements in each of three
categories, we must analyze our needs a little more closely.

The pertinent questions are: memory size, and the cost and ease of programming.
The size of a ROM is determined by the user. When power is first applied, how much
effort does the user want to expend to make the computer execute a specific program?
ZAP has no front panel and no banks of address and data switches to toggle in instruc¬
tions. This being the case, ZAP must have a program that executes immediately (when
power is applied or the reset button is pushed), and that allows the central processor to
communicate with its peripherals and set itself in a mode that is directly programmable
through these devices. Once power is applied, a simple 50- to 100-byte program can be
written, which facilitates keyboard to memory loading. But perhaps we need to enter a
large program in memory? Are we to enter it all through the keyboard?

High-speed data entry can be accommodated through a serial interface. This can be
added at the expense of another 100 or 200 bytes. Another consideration is the necessi¬
ty for some operator address and data display to ease program development.

In conclusion, to incorporate all the functions necessary for a single-board develop¬
ment system, the ROM can easily require 500 to 1,000 bytes of storage. Many comput¬
er systems use a 64- to 256-byte ROM to store a bootstrap program. A bootstrap is a
program that coordinates the minimum amount of necessary peripherals to load a
larger program into the computer. In most personal computer systems, this bootstrap
controls a cassette interface, and the program that is subsequently leaded is calied a
monitor.

A monitor (explained in Chapter 6) is a very important piece of software that re¬
quires about 1 K of program storage. Our decision is whether to make the monitor
totally resident in ROM (ready for immediate execution), or to reduce ROM to the
barest minimum and load the monitor from either a keyboard or a cassette storage sys¬
tem.

This is an important consideration for someone building a computer from scratch.
When given a choice, I feel, you should almost always opt for the solution that calls for
the fewest components and you should include the ROM monitor in the hardware. It's
like putting the cart before the horse to require that a cassette interface be used to load
all the diagnostic software. It's quite possible that the monitor program, resident in a
1 K ROM, would be required to troubleshoot and align the serial interface and cassette
modem sections. A further consideration is that the ZAP computer can be brought on
line sooner. With a ROM monitor, useful programs can be entered via the keyboard
without having to build a serial interface.

I suggest that the preferred ROM memory size for ZAP be 1 K. As previously men¬
tioned, ROM is mask-programmed by the manufacturer. However, let's not forget that
for a home-built computer, you are the manufacturer. Fusable link PROMs are an ex¬
pensive proposition when configured in a 1 K block. As a 64-byte bootstrap loader
they are ideal.

The suggested alternative for the ZAP read-only memory is to use an EPROM that is
programmed by the user. A 1 K EPROM such as the 2708 (or the 2 K 2716) is cost-
effective for the home-built computer. The Intel 2708 ultraviolet erasable read-only
memory is recommended for this application. (The 2716 is a 2 K EPROM with a single
+ 5 V power supply.)

BUILD YOUR OWN COMPUTER 113

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ADDRESS

INPUTS

OUTPUT

M OUTPUT
BITS FOR
EACH OF N
INPUTS

Figure 4.27 A block diagram of a read-only memory.

♦5V *5V *5V +5V

OATA OUTPUT

Figure 4.28 A simple 3-bit read-only memory (1x3 bits).

Figure 4.29 A block diagram of a 16 byte read only memory.

114 BUILD YOUR OWN COMPUTER

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♦ 5V

ADORESS

DECODER

MEMORY STORAGE ARRAY

2.2K (TYP FOR 8)

ADDRESS

INPUT

INSTRUCTION
STEP 1 333

INPUT PORT 0

o STEP 2 000

STEP 3 323

OUTPUT PORT 0

o STEP 4 000

o STEP 5 323

OUTPUT PORT 5

o STEP 6 005

o STEP 7 303

STEP 8 000 > JMP TO 0

o STEP 9 000 ^

o STEPS 10 THRU 16 NOT CONNECTED

IC2 a IC3
OUTPUT BUFFERS

7404

♦5V PIN 14
GNO PIN 7

8-81T DATA OUTPUT

Figure 4.30 A diode-matrix read-only memory with a test program.

EPROMs

The EPROM is a read-mostly memory. It is used as a ROM for extended periods of
time, erased occasionally and reprogrammed as necessary. Erasure is accomplished by
exposing the chip substrate, covered by a transparent quartz window, to ultraviolet
light. The EPROM memory element used by Intel in the 2708 is a stored-charge type
called a FAMOS transistor (Floating-gate Avalanche injection Metal Oxide Semicon¬
ductor storage device). It is similar to a p-channel silicon gate field-effect transistor
with the lower or ''floating” gate totally surrounded by an insulator of silicon dioxide.
The 1 or 0 storage value of the FAMOS cell is a function of the charge on the floating
gate. A charged cell will have the opposite storage output of an uncharged cell. By ap¬
plying a 25 V charging voltage to selectively addressed cells, particular bit patterns that
constitute the program can be written into the EPROM. Surrounded by insulating
material, the charge can last for years. When this silicon dioxide insulator is exposed to
intense ultraviolet light it becomes somewhat conductive and bleeds off the charge on
the floating gate. The result is erasure of all programmed information.

Appendices Cl and C2 detail the pin layout and electrical specifications of the 2708
and the 2716 respectively. Chapter 7 explores various methods to program and test the
chip.

BUILD YOUR OWN COMPUTER US

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Read/Write Memory

Read/write memory is just what its name implies. Such memory allows data to be
written into it as well as be read from it. Read/write memory for microcomputers is
generally configured from semiconductor programmable memory devices that retain
data only while the power is on.

ROMs are technically random access devices; however, read/write memory, which
is composed of semi-conductor devices and is primarily intended for use in microcom¬
puters, has come to be called RAM (random access memory). From this point on, we
shall refer to RAM as programmable memory.

There are two classes of programmable memories: static and dynamic. Static pro¬
grammable memory stores each bit of information in a bi-stable storage cell such as a
flip-flop. This information is retained as long as the power is supplied to the circuit.
Dynamic programmable memories have a simpler internal structure, smaller size, dissi¬
pate less power, and are inherently faster. They store information as an electric charge
on the gate to substrate of a MOS transistor. This charge lasts only a few milliseconds
and must be refreshed. This necessity to refresh the stored information is one of the ma¬
jor distinctions between static and dynamic programmable memories.

Refreshing dynamic memories can be bothersome, however. The process requires
that all storage cells be addressed at least once every few (usually 2) milliseconds. A
counter circuit is usually incorporated to exercise the memory address lines when the
computer is not accessing memory. In most systems, memory refresh requires addi¬
tional external circuitry. The Z80 contains this circuitry within the central processor
chip and greatly facilitates the use of dynamic memory. However, this facility is lost
when the Z80 is reset. Therefore, extra refresh circuitry is necessary.

The choice between dynamic and static programmable memory technology is
predicated on cost and convenience. Even with the expense of external refresh circuitry,
dynamic memory is less costly. In a prototype system such as ZAP, however, dynamic
memory is more trouble than it is worth. Once built and operational, dynamic memory
might well be the best answer to memory expansion. But at this point in the building
process, the inclusion of dynamic memory would over-complicate the design. This
book, which emphasizes getting a beginner on-line, deals exclusively with semiconduc¬
tor static programmable memory applications.

Static Programmable Memory

Figure 4.31 is a block diagram of a static programmable memory element typical of
the type used in the ZAP computer. There are five basic components of a program¬
mable memory: 1) address input lines, 2) data input, 3) data output, 4) chip select,
and 5) a read/write- or write-enable strobe line. The address input lines are connected
to the address bus of the computer. In the case of a N by M bit programmable memory,
where N is the number of words and M is the length of each word, there must be
enough address lines to address all N bytes. For example, in a 1 K programmable mem¬
ory it would take 10 bits to address all 1024 bytes within this memory (eg: 2 ,O "1024).
Static programmable memory chips that contain fewer bytes of data, such as a 64-byte
programmable memory, would obviously require fewer address lines. For a 64-byte
memory, only 6 bits of address are necessary.

Because the function of a static programmable memory device is to allow storage
and retrieval of data, provisions must be made for data input and data output from the
device. The data input and data output lines (shown in figure 4.31) are designated as
separate functions.

During the read function, the stored data within the addressed memory cell is avail¬
able on the data output lines. During the write function, data that is placed upon the
data input lines would be stored at the address designated by the code on the address
input lines. It is not necessary that static programmable memory devices have indepen¬
dent data input and data output lines.

In most cases, these devices are configured with three-state outputs. Data input and
data output can be attached together to a bi-directional data bus, or they can be the

116 BUILD YOUR OWN COMPUTER

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same lines and time multiplexed. Figure 4.31 illustrates a three-state method of data
busing. During a read function, the data input lines are disabled internally within the
memory device. The contents of the memory cell addressed by the address input lines
are available on data out and are fed directly to the bi-directional data bus. During a
write function, the opposite is true. The data output lines are set in the three-state mode
(which you may recall is effectively an open circuit), and draw no current from the bi¬
directional data bus. The contents of the bi-directional data bus are stored at the
designated memory cell.

All of these multiplexing functions are dependent upon the read/write and chip-
select lines. No operation can occur without the memory device being selected through
the chip-select line. To select a particular bank, as outlined earlier, it is necessary to
have decoding logic that enables these banks through the chip-select lines. Once a chip
or bank of chips has been selected, the computer determines whether data should be
read from or written into these memory locations. Under normal operation all static
programmable memory is left in the read state, and only enabled during a write com¬
mand by setting a level 0 on the write enable. This is called a write-enable strobe.

Figure 4.32 is a detailed timing diagram of the memory read and write cycles. The
write/enable is a combination of memory request and write. A read/enable is a com¬
bination of memory request and read. Proper decoding of these signals and the chip
select were discussed previously. In its basic form, ZAP has 8 chip-select lines, each ad¬
dressing alK bank of memory.

Figure 4.33 illustrates the memory map of the basic ZAP computer. As initially con¬
figured, ZAP contains 3 K bytes of memory. Location 0 thru 3FF is a 1 K EPROM.
Locations 400 thru BFF are static programmable memory locations. The 1 K EPROM is
configured to reside in locations 0 thru 3FF so that ZAP can be easily started with a
power-on reset. Programmable memory located at locations 400 and above is con¬
sidered to be user programmable memory. At least 2 K is recommended for satisfac¬
tory operation. ZAP will work with 1 K, but 2 K is recommended for basic peripheral
expansion.

Figure 4.33 also shows how memory is attached to the computer. All three banks of
memory are attached in parallel between the address and data buses. Each bank has a
separate decoded chip-select. When the EPROM is enabled and MCSO is at a logic
level 0, EPROM data is impressed upon the data bus lines. The other two banks of
memory are in the three-state mode and have no effect on the bus. When the computer
accesses programmable memory, the chip for that particular bank of memory is set to a
logic 0, and only that bank of memory has access to the data bus.

While all banks of memory would have the same address applied to them, only the
selected bank would be in the active mode. The logic flow is similar for the computer to
write into a bank of memory. You will notice that there are write-enable lines leading to
each of the 1 K static programmable memory banks, but not to the 1 K EPROM. AlK
EPROM can only be written into with a special interface. Therefore, the write-enable
strobe is only attached to the programmable memories.

If, for example, the computer were to write into location 400, the chip-select for
bank 1 and the write enable for bank 1 would both have to be at a logic 0 to allow data
on the data bus to be stored into location 400. This type of programmable memory
configuration is both multiplexed and three-state. In the read mode, data flows from
the programmable memory chip; in the write mode it flows into it, and when not se¬
lected it's three-state.

Up to this point, we have discussed block diagrams of static programmable memory.
To produce an operational computer, it's necessary to configure this memory with ac¬
tual parts. Unfortunately, single chip 1 K by 8-bit programmable memories were ex¬
tremely expensive when ZAP was designed. Therefore, these 1 K blocks are designed
from multiple components. Two relatively inexpensive and popular static program¬
mable memory chips are the Intel 2102A (Appendix C3) and the Intel 2114 program¬
mable memory (Appendix C4).

The 2102A is a 1 K X 1 static programmable memory. Configuring a 1 K X 8 block
of memory requires eight 2102s attached in parallel. By comparison, configuring a
1 K X 8 block with 2114s would require only two chips. This is because the 2114 has a
higher internal density than the 2102. Because the objective of any hand-wired comput-

BUILD YOUR OWN COMPUTER 117

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er project is to get the device on line easily, 2114s are the recommended programmable
memory devices for ZAP. While 2102s will work, the added wiring necessary to use
these devices far outweighs the additional cost of the 2114s.

Figure 4.34 illustrates how two 2114s are attached together to produce a 1 K X 8
programmable memory bank. They share a common chip-select line. The data input

lines are divided so that 4 bits of data are stored on each chip. Because each has a
1024-byte address capability, the 10-bit address lines are commonly shared. To build
the basic ZAP, two circuits of the type illustrated in figure 4.34 should be constructed.
The total memory for the basic computer is 3 K. It can be expanded to 8 K without ad¬
ditional address decoding. It is not absolutely necessary to have 2 K of programmable
memory if the user wishes only to check the operation of the system. At a minimum,
the EPROM must be wired as 1 bank of memory.

The 1 K EPROM contains the monitor which allows ZAP to function. This monitor
contains many smaller programs that are called subroutines. When the main program
calls a subroutine, it places the return address on a software stack located in program¬
mable memory. At the conclusion of the subroutine, the central processor pulls this ad¬
dress from the stack and returns to the main program. Usually the stack requires no
more than 64 bytes. However, it is no less trouble to wire two 2114s for a full 1 K X 8
bank of memory than to try to wire a 64-byte memory.

An additional bank of 1 K, designated as bank 2, could be added at the user's discre¬
tion. This bank is necessary if you plan to write programs that will occupy more than
1 K of memory including the stack. As the computer is presently configured, 1 K may
appear adequate; however, for the additional programs outlined in this book, 2 K is
recommended. This is especially true when a buffer area is required to communicate
with external peripherals. The schematic for the final memory configuration is shown
in figure 4.35. It should be added to the circuitry of figures 4.17 and 4.26.

Unlike the other sections of the computer, the memory cannot be checked except
under program control. Theoretically, the address lines can be preset and data read or
stored, but it's not worth the effort. Memory checks will occur after the input/output
section is wired. Basically, it will be checked first with EPROM alone, then with the ad¬
dition of the programmable memory. I mentioned previously that EPROM and pro¬
grammable memory are related yet operate independently. While a program is often
stored in PROM, it usually requires programmable memory for proper execution.

In a short program that loads the accumulator, writes to an output port, and jumps
back to itself again, with no subroutine calls, programmable memory is not necessary.

It can be completely located on EPROM. The exact procedure for this test will be out¬
lined at the end of the I/O section.

ADDRESS

INPUT

WRITE ENABLE

RE AD/* RiTE -

CHIP SELECT

OATA IN

BI-DIRECTIONAL DATA BUS

STATIC

RAM

MEMORY

DEVICE

N>M BIT

Figure 4.31 A block diagram of a static programmable memory element of N x M bits.

118 BUILD YOUR OWN COMPUTER

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L ... . ... i

MEMORY READ CYCLt

•

EMORY WRITE CYCU

T 2

t 4 9

T 3

f \_i

' \ ,

_ _

1 \ ,

_LI_

MEMORY

ADDR.

MEMORY

AOOR.

MREQ

DATA BUS

OATA !

OUT

(00- 07)

i ir< /

waTT

::n::

:n;;;

Figure 4.32 A timing diagram of the memory read or write cycles for the Z80. This diagram does not
include WAIT states.

BANK 0

BANK l

MCSO <►

MCS1

BANK 2
MCS2

MEMWR o-

WRlTE ENABLE

Figure 4.33 A block diagram of the memory map for the ZAP computer.

BUILD YOUR OWN COMPUTER 119

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IV. Input/Output

Thus far we have discussed the central processor control and memory decoding. The
input and output functions are equally important. For the computer to display useful
information, it must be "interfaced" to peripherals. 'Interface" is an overworked term
that refers to a capability of communicating with external devices such as keyboards,
video or LED displays, and memory storage systems. Communication can be either
data input or output.

Input data can come from keyboards, audio cassette mass storage, or special data ac¬
quisition interfaces. Similarly, output data flows from the computer to peripherals (eg:
video displays, numeric readouts, printers, and external control interfaces). The func¬
tion and format of the data communication between the central processor and the pe¬
ripherals might vary considerably, but the internal routing of the data is fundamentally
the same.

The Z80 microprocessor provides both an input and output instruction. An output
from the processor is logically the same as writing to memory, and receiving an input
from an external device is similar to a memory-read command. They are differentiated
from memory operations by gating the read and write status lines with the I/O request
control line. Logical concurrence of an I/O request and a read or write status output
designates the direction of the communication with the peripheral device. Simulta¬
neously with the control signals, the address code (1 of 256) of the subject device is
placed on the address bus. A timing diagram of these signals is shown in figure 4.36.
The decoding logic was detailed in section II of this chapter.

Wiring the I/O ports for ZAP is a two-stage process. When hand wiring a computer,
the most important consideration is to see that the input/output function works by the
least complicated method. A successful test of the ZAP I/O section also indirectly tests
memory. This is so because input and output instructions cannot be exercised except by
a program stored in memory.

Z80 input and output is handled 8 bits at a time. It does not matter whether the exter¬
nal interface configuration is serial or parallel. Data transfer between the central pro¬
cessor and I/O is 8 bits parallel and basically occurs as follows.

A0-A7

iORQ

ffo

DATA BUS

WAIT

DATA BUS

READ CYCLE

WRITE CYCLE

Figure 4.36 A timing diagram of input or output cycles for the Z80.

BUILD YOUR OWN COMPUTER 121

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Output Instruction

OUT(n), A

When this instruction is executed, the contents of the accumulator A are placed on
the data bus and written into device n. The address of device n is located on address
lines AO thru A7.

If the accumulator contains 40 hexadecimal when the instruction OUT 23, A is ex¬
ecuted, 40 hexadecimal will be written into the peripheral device (also called "port
number") decoded as 23 hexadecimal.

While there are other more complicated output instructions available in the Z80 in¬
struction set, they all pass data through the data bus to the external device. Because the
data bus is used for transfer of information between the central processor and memory
as well as I/O, the computer must be allowed to continue executing its program. Data
cannot remain on the data bus waiting for the peripheral (the central processor can be
made to do this but such abstract configurations would be confusing at this time). The
data is valid for only a few clock cycles and must be stored if needed for a longer
period.

Figure 4.37 diagrams a typical 8-bit storage register. It consists of 8 individual stor¬
age elements with a common "store enable" input. In its simplest form, the single stor¬
age cells can be D-type flip-flops such as shown in figure 4.38. Input data (ie: the data
bus) is attached to the D input lines and is only clocked onto the output lines (Q and
Q) during an I/O write strobe. Using 7474s would require 4 chips for an 8-bit word. A
better method is to use the improved circuits of figure 4.39.

Input Instruction

IN A, (n)

When this instruction is executed, the data from the selected port (n) is placed on the
data bus and loaded into the accumulator.

If the subject external device reads 10 hexadecimal when the instruction IN A, 20 is
executed, the value 10 hexadecimal read from device number 20 hexadecimal would be
loaded into the accumulator.

There are other more complicated input instructions but as was the case with output
instructions, the route for all data is still the data bus. To keep the data bus from being
dominated by a single device attached to it, all input devices (ie: the output from them)
must be three-state. This can be accomplished either by using interface logic such as
UARTs and peripheral interface adapters that are designed to be three-state, or by add¬
ing three-state input buffers such as illustrated in figure 4.40 (the block diagram of the
typical 8-bit, parallel-input port).

Whatever is on input lines B 0 thru B 7 during an I/O read instruction will be directed
to the central processor. Using these direct read instructions there is no interaction be¬
tween the central processor and the external hardware attached to the input port. Addi¬
tional logic is required to coordinate the exact timing between the computer and an ex¬
ternal peripheral. The solution is called "handshaking." Such a capability requires
either more sophisticated input port hardware, connection to the central processor, in¬
terrupt logic, or additional I/O ports to coordinate the timing.

Checking out the basic ZAP hardware is best accomplished by using the least com¬
plicated hardware. A simple input port is illustrated in figure 4.41 and consists of 2
quad three-state buffers. Should there be any brave experimenters who wish to have
full handshaking on I/O ports or need more than the 8 mA output drive capabilities of
a LSTTL device, input and output ports can easily be configured using Intel 8212s. The
specifications described in Appendix C5 demonstrate its versatility.

Input/Output Checkout

Ultimately, ZAP could have a keyboard, RS232 serial CRT terminal, audio cassette
interface, and analog, as well as digital I/O capabilities. Trying to attach all these pe¬

rn BUILD YOUR OWN COMPUTER

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ripherals together and checking everything simultaneously is a monumental undertak¬
ing. A more methodical approach is to construct the minimum hardware and software
that proves operational and then build upon it. That is the route taken thus far.

With the exception of memory, we have attempted to eliminate any potential prob¬
lems by static testing where possible. The simple I/O devices of figures 4.39 and 4.41
lend themselves easily to this situation. To test I/O fully requires one input port and
one output port. It should be wired as shown in figure 4.42. Only port 0 need be con¬
nected at this time. The additional circuitry included in this diagram can be ignored.
Only ICs 21 thru 23 are of concern presently. The other devices are enhancements to
the basic ZAP and will be discussed later.

Static Test

With power off, remove all ICs p reviously insta lled. In sert ICs 20, 21, 22, and 23.
Turn on power. Temporarily ground DSOWR and DSORD. This maneuver, impossible
under direct computer control, allows data bus access to both input port 0 and output
port 0 at the same time. With the two ports connected in this manner applied input data
should be available immediately at the output port. With the input lines of ICs 21 and
22 open and power applied, the outputs of IC 23 should be at a high level. Sequential
grounding of input lines B 0 thru B, should be refl ected on lines B 0 thru B 7 of IC 23. A
final test is to disconnect the temporary ground on DSOWR while one of the input lines
of IC 21 and 22 is grounded. The logic 0 output of IC 23 should remain low even when
the input line is no longer grounded. The result is that the data is "latched/' It will re¬
main until updated by another write strobe.

o? o-
£>6 0 -
O5 O'
0 4 °-
O3 o-
0 2 o-
Oj o-
D 0 o-

I/O WRITE STROBE
i_r

BI-DIRECTIONAL
) DATA BUS FROM
CPU

S-BIT REGISTER

TIT

87 Bg 85 84 e 3 8 2 Bj 8 q
' ■ v - y

LATCHED PARALLEL OUTPUT

LSTTL I OUT • 8mA

Figure 4.37 A block diagram of a typical latched parallel output port configured with an 8-bit storage
register.

BUILD YOUR OWN COMPUTER 123

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Figure 4.38 A block diagram of a latched parallel output port using D-lype flip-flops as a storage
register.

DATA BUS

DSXWR

0 7 d 6 d 5 d 4

0 3 D 2 D, Dq

8-BIT LATCHED
PARALLEL OUTPUT

DSXWR

f -S

O7 D$ D5 D 4 Dj D 2 Oj Oq

8-BIT LATCHED
PARALLEL OUTPUT

DATA BUS

D7 D$ D5 D 4 O3 0 2 Dj Oq

8-BIT LATCHED
PARALLEL OUTPUT

Figure 4.39 Schematic diagrams of 8-bit latched parallel output ports.

a) Using tv/o 4-bit LSTTL latches.

b) Using a traditional 8-bit TTL latch. Note that non-LSTTL devices can be substituted but
care should be taken to observe the total bus loading.

c) Using a newer 8 bit LSTTL latch.

124 BUILD YOUR OWN COMPUTER

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V-.-'

8 -8IT PARALLEL INPUT

INPUT CURRENT
WORST CASE
LSTTL l|f< • 0 . 4 mA

THREE-STATE

BUFFER

CTL

OUT

THREE-STATE

X • DON'T care

Figure 4.40 A block diagram of a typical 8-bit parallel input port.

DATA BUS

DSXRO

0 ? D 6 0 5 0 4

0 3 0 2 Oj 0 0

Figure 4.41 A schematic diagram of an 8 bit parallel input port for the ZAP computer.

BUILD YOUR OWN COMPUTER 125

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126 BUILD YOUR OWN COMPUTER

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Figure 4.42 A schematic diagram of a parallel input/output ports of the basic ZAP computer with addi¬
tional enhancements required for use with the ZAP monitor software.

V. Dynamic Checkout of the Basic Computer

All systems, with the exception of memory, should have successfully passed the
static checkout procedures. The memory wiring should be checked for continuity.
Because ZAP has no front panel or indicator (unless you wish to add one), the full sys¬
tem can only be tested by executing a program that dynamically exercises all the system

hardware. This is easier than it sounds. For the computer to output a number to a spe¬
cific port address, the central processor must be operational and have reset properly to
execute the instruction. The memory read must work or the central processor wouldn't
know what to do. The memory and I/O decoding must work for the data stored in
memory to arrive at the right output port. And finally, for the data to be read at the
port, the output port must function as well. In short, if you can execute a program, the
computer works.

We can make the process simpler by using the fewest program steps possible and by
initially eliminating the necessity for programmable memory. Remember, ZAP has
both EPROM and programmable memory. With no monitor or front panel, program¬
mable memory cannot be loaded directly to run a test program. The test program must
be already loaded in ROM (in our case EPROM). By carefully selecting the instructions
used in the test program, programmable memory can be left out entirely when we run
the first test. Why complicate matters by having more hardware than is necessary?

Few instructions are required to test the operation of the processor, reset, memory
and I/O. Usually the central processor either works or it doesn't. Central processor
failure is rarely a case of one of the instructions executing improperly. If ZAP can read
in data at port 0 and output the same value to output port 0, we can assume it all
works. For the data to reach output port 0, it must travel through the central processor
(assuming you have removed the temporary grounds on the I/O strobe lines) under
program control.

Such a test program is:

OCTAL
IN A, 0 333 000

OUT 0, A 323 000

IP NN 303 000 000

HEXADECIMAL

DB 00 read port 0 in

D3 00 write to port 0 out

C3 00 00 jump to beginning

This 7-byte program will read input port 0 data into the accumulator and then write
this same data to output port 0. The jump instruction will cause the program to repeat
this action continuously. The program requires no programmable memory to store
either intermediate data or the stack pointer. Because only the accumulator is affected,
the 7-byte program can be completely contained in ROM. In this case, ROM can be
either a 2708 EPROM programmed manually as described in Chapter 7 or a simulated
ROM as shown in figure 4.30. If you use a simulated ROM, it may be necessary to
reduce the 2.5 MHz clock rate to compensate for the capacitance of the external cir¬
cuitry. Figure 4.30 also includes an output to port 5 that tests a data display to be added
later. Rather than rewrite the EPROM or rewire the pseudo-ROM, you may wish to
add this instruction now.

The final test of the basic ZAP is to exercise a program that uses both programmable
memory and EPROM. Again, the philosophy is that if it can store and retrieve 1 byte
from programmable memory, then all 1 K of that bank should work. A slightly longer
program is used this time. The following program is stored in EPROM and the pro¬
grammable memory is used by the central processor to store the stack:

TEST

OCTAL

HEXADECIMAL

LD SP, nn

061 000 006

31 00 06

set stack pointer to
middle of bank 1

programmable memory

IN A, 0

333 000

DB 00

read port 0 input

CALL TEST

315 014 000

CD 0D 00

call program test

OUT 0, A

323 000

D3 00

write data to port 0 out

JP nn

303 000 000

C3 00 00

jump to beginning

RET

311

return to main program

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When assembled, the 14-byte program would be loaded as follows (in hexadecimal):

Location

Program

00/00

31 00 06

DB 00

CD 0D 00

D3 00

C3 00 00

The operation of this program is similar to the previous example. A byte is read from
input port 0 and then read back out to output port 0. In between these operations there
is a call to a subroutine that is just a return instruction. When the call is executed, the
location where the program is to resume operation after the call is put on the stack in
programmable memory. At the conclusion of the call (the return instruction), the ad¬
dress is popped off the stack and placed in the program counter so that the program can
resume where it left off. The only way for the input data from input port 0 to get to
output port 0 is for this call to be executed properly. Of course, this requires that pro¬
grammable memory work properly.

Many other programs that would further enhance the diagnostic checkout pro¬
cedures can be written. In my experience, however, if it executes these two programs,
you can count on everything running.

Once these milestones are reached, the experimenter has a truly operational comput¬
er. The next step is to expand this basic unit and make ZAP somewhat more versatile
by adding address and data displays, a hexadecimal keyboard, a serial interface, along
with an operating system that coordinates the activities of these peripherals. While the
present system is a computer, these additions are necessary to move beyond an ex¬
perimenter's breadboard project.

128 BUILD YOUR OWN COMPUTER

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CHAPTER 5

THE BASIC PERIPHERALS

Once the basic ZAP computer has been constructed and tested, we are ready to add a
few necessary peripherals that will greatly increase the system's utility. External periph¬
erals facilitate the input and output capabilities of the computer. They include such
items as printers, cathode-ray tubes (CRTs), tape drives, and disks. Peripherals of this
magnitude, however, are usually used on larger systems. For our Z80-based ZAP,
useful peripherals include a keyboard to ease data and program entry; a visual display
to allow the computer to indicate a logical conclusion in readable form; a serial com¬
munications interface, which allows ZAP to “talk" to another computer; and an inter¬
face to an audio cassette mass storage device. These four ingredients are the difference
between an experimental breadboard and a useful personal computer.

The keyboard can be either a small keypad for limited data entry or an alpha-numer¬
ic "typewriter"-style ASCII (American Standard Code for Information Interchange)
keyboard for text editing and high-level language programming. The visual display
could range from a hexadecimal LED readout to a full 24-line by 80-character CRT ter¬
minal. The serial port, in conjunction with the audio cassette interface, could be used
to cold start the computer and load application programs.

As with the previous circuits in this book, I've tried to provide various alternative

designs so that you, the builder, may construct a truly personal system. Each of the
four peripheral devices will be explained in detail and numerous design examples will
be provided; both limited function hexadecimal input and full ASCII keyboards will be
addressed. In the case of the visual display, we will discuss a rudimentary LED octal
and a hexadecimal readout for ZAP. For more sophisticated visual interaction, a CRT
terminal is required. Because this unit is much more complicated than a keyboard or an
LED display, an entire chapter has been dedicated to it. My basic premise is to start
with the essentials, provide a thorough understanding of their applications, then move
to more complex, more useful add-ons.

The expansion of the basic ZAP into an interactive microcomputer system requires
the addition of a software program to synchronize and exercise the new peripherals.
This software is called a monitor and is discussed in a later chapter. Peripherals merely
provide the means for added data entry and display capability.

I. KEYBOARDS

The only way the Z80 can communicate to an external device is through the input/
output bus structure previously described. (While more esoteric methods such as direct
memory access exist, they will be ignored for the present.) When the processor wishes
to signal the user that an event has occurred, it can do so by changing the output level
on one bit of a parallel-output port. For example, the end of program execution can be
designated by bit 7 on port 0 going from a logic 0 to a logic 1. Using this concept, 8
separate elements could be individually designated and controlled from the 8 bits of
output provided on the single "basic ZAP" port.

Information input is just as simple. The numbers 0 thru 7 could correspond to 8
switches on the 8 input bits of port 0. This is shown graphically in figure 5.1. When

THE BASIC PERIPHERALS 129

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bit-7 switch is pressed, grounding the input, the logic level transition can signify a nu¬
meric entry of 7 to the computer; many microprocessor applications require only these
few bits of I/O. A traffic light controller, for example, with a single red, yellow, and
green light would need only three bits of output.

The program to control the lights would have been written, assembled, and pro¬
grammed into some type of non-volatile storage. However, ZAP must interact with a
human operator in such a way that programs can be developed and tested. The major
difference between the traffic light controller and ZAP would be the peripherals and
not the microprocessor's capabilities.

In our example, we could put 8 switches on an input port. To enter information, we
have only to write a short program that reads the data on port 0 into the accumulator
and then stores or acts upon it. The chapter on monitor software will address these
manipulations, but one problem must be solved first: synchronizing peripherals to the
computer.

How does the computer know when the data on the switches is or is not valid? And,
could we make a timer in software or hardware that reads the port every second, on the
second? Can you, for example, see yourself trying to flip all the switches in time or to
make the computer wait?

8-BIT OUTPUT PORT

8-BIT INPUT PORT

67 66 B5 64 63 82 61 80

67 66 65 64 63 62 61 80

SW 0 -SW 6 AND PB ARE SPOT

Figure 5.1 A parallel input/output interlace with LED readout and switch input.

The most popular method of synchronizing a peripheral that has slow data input to a
computer with fast program execution is to use "data ready" strobe pulses. (Interrupts
may also be used but they involve complicated programming and will not be con¬
sidered here.) The program is written to read and check the logic level of one bit only.
By substituting a push button for one of the eight switches, say bit 7, we can simulate
the strobe. To accomplish this, first set data on the other seven switches; then, with the
program sitting in a loop checking bit 7, press the push button to generate a logic tran¬
sition. The program, sensing that a "data ready" strobe is present, reads in the entire
port and uses the other 7 bits of data.

Frequently, it is not practical to limit ourselves to just 7 symbolic interpretations
when using 7 bits of input. A more logical approach is to code the input and let the 7
bits represent up to 128 individual symbols. The choice between a coded versus a
straight parallel input is governed by the application. If the computer is part of a
burglar alarm, with each input bit representing a door or window switch, then it is im¬
portant to know individual and simultaneous bit transitions. In this application, it is
necessary to have parallel signal input. On the other hand, alpha-numeric entry from a
typewriter keyboard is by nature serial, one letter at a time. Therefore, nothing is
gained by using 128 parallel input bits for a 128-key keyboard. A 7-bit code is more
cost-effective.

130 THE BASIC PERIPHERALS

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The most widely used keyboard code is ASCII (American Standard Code for Infor¬
mation Interchange). Appendix B lists the code and the characters it represents. Any
homebrew keyboard should reflect this coding to be compatible with commercially
available software such as BASIC.

There are a number of methods that can be used to generate suitable key codes.
Figures 5.2 and 5.3 reflect hardware and software approaches, respectively. The block
diagram outlined in figure 5.2 is a hardware scanning system suitable for a 64-key key¬
board. A 6-bit counter progressively enables each column while scanning all rows in
each step. Should any key be pressed, a logic 0 will be routed through the 8-input
multiplexer to the scan control logic. This signal is used to generate a key-pressed
strobe (also called data-ready strobe) to the computer. The row and column address
lines from the counter are read and indicate the binary matrix address of the pressed
key. Compatibility with the ASCII code is simply a matter of placing the proper key at
the correct address within the matrix.

Another suitable encoding method is outlined in figure 5.3. This technique, which
uses software logic to scan the matrix, should be used only when computer program ex¬
ecution speed is not critical. While reducing the circuitry to one chip, the trade-off in
this approach requires both an input and output port. It functions in the same way as
figure 5.2. The computer sets a 4-bit column counter code on the decoder. Then it
searches the parallel input port for the row with the logic level 0 signifying a pressed
key. While this may seem to be an easy way to decode 128 keys, there are certain soft¬
ware considerations.

Figure 5.2 A matrix keyboard scanner for a 64-key keyboard.

THE BASIC PERIPHERALS 131

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♦ 5V

Figure 5.3 A software-driven 128-key encoder circuit.

The key-pressed or data-ready strobe in any keyboard serves two purposes: it signi¬
fies that data is present and ready, and it is timed so the strobe is not generated until
after a mechanical debounce time period has elapsed. The reason for the delay is ob¬
vious. Remember, these microprocessors can execute 200,000 instructions a second. A
program written to look for a strobe and read the data would run a hundred times on a
single keypress because of contact bounce. The mechanical making and breaking of the
contact could appear like 100 data-ready strobes if we aren't careful. A true data-ready
strobe is not generated until after a debounce time-out and then it should be fast-rise¬
time (<200 ns) pulse with a rate exceeding the cycle time of the computer. The dura¬
tion of the pulse should be long enough to allow the scanning program to catch it even
if it is off doing some other task, and short enough so that the central processor doesn't
see the same strobe twice.

There are two techniques to combat the problem of strobe duration. One is to set a
flip-flop with the rising edge of the strobe and tie the clear line of the flip-flop to an out¬
put bit. After reading in the data, the program can clear the "data-ready" condition by
resetting the flip-flop. This is usually employed in cases where the response time to a
keyboard or other device is variable. This method also guarantees that an event will be
registered and not missed due to time delays. Of course, most keyboard encoders do
not latch their output data. If a key is released, even if the strobe has been set in a flip-
flop, no data will be present when the computer reads the keyboard. There are ways to
get around this but they all involve additional hardware.

Usually the experimenter's problem is reading a strobe twice rather than not waiting
long enough to acknowledge it. Instead of using a hardware flip-flop, most program¬
mers employ a software flag, the second technique in dealing with strobe duration.
When a key-pressed strobe is sensed, the program sets a flag in a memory location,
reads the data, then checks the strobe again. If the strobe is high, the flag is checked
and the data is not read. Only when the strobe returns to a logic zero is the flag reset,
enabling data input the next time.

It's not easy to construct keyboard encoders for 64- or 128-key ASCII keyboards. It's
simpler to use a commercially available, scanning, read-only memory encoder such as
the one documented in Appendix C6.

As far as ZAP is concerned, it is important to learn to walk before we run. Most peo¬
ple would consider ZAP to be a learning tool that could be eventually expanded into a
full-blown microcomputer system. A full 128-key ASCII keyboard could prove to be as
expensive as the entire ZAP computer. To minimize expense and retain the experimen-

132 THE BASIC PERIPHERALS

Copyrighted material

tal qualities of this endeavor, a limited keyboard, suitable for hexadecimal entry, is
suggested as the first level of expansion. With a limited number of keys to encode,
hardwired TTL circuitry offers a reasonable cost advantage over expensive encoder
read-only memories.

Figure 5.4 is a hexadecimal keyboard interface designed specifically for the ZAP soft¬
ware monitor. A hexadecimal keyboard allows data and instruction entry as 2 digit
hexadecimal numbers. In addition to the 16 numeric keys, there are 3 command keys
designated "EXEC" (for execute), "NEXT," and "SHIFT." EXEC and NEXT will be ex¬
plained in the monitor section. The SHIFT is similar to a regular keyboard and is used
to double the number of key codes by allowing a SHIFT 1, SHIFT 2, etc. The particular
significance of each code will be explained later.

+ 5V

-o o-

6 >C3

7 74154

15 o c e

♦ 5V

8 9 112

0 C

B A

IC2 7493

CLOCK

R0I2) R0I1)

2.2K

*2 kHt

ICl

♦ 5V

2.2 K

♦ 5V

4.7/iF

R/C

cext

B 1
B2

4-BIT BINARY
OF

HEXADECIMAL

B4 FUNCTION *1

B5 FUNCTION #2

B6 SHIFT KEY

B7 KEYPRESSED
STROBE
SI 10m*

"EXEC"

"NEXT"

"SHIFT"

220

-VvV

+ 5V

4.7/if

ICl

4.7 fif

ICl

7414

10K

ICl

ICl 7414
IC2 7493
IC3 74154
IC4 7400
ICS 74121

Figure 5.4 A hexadecimal keyboard interface.

THE BASIC PERIPHERALS 133

Copyrighted material

The keyboard required to support the ZAP software monitor has 19 keys. The en¬
coder in figure 5.4 is a combination scanner and hard-wired parallel output. Encoding
depends upon the particular key pressed. The hexadecimal keys 0 thru F are sensed
through a multiplexed scanner, IC 2 and IC 3. As IC 2 counts, it sequentially places a
logic 0 on each of the 16 output lines of IC 3. If any key is pressed, that low level is
routed back to 1C 4 and stops the clock. The counter is then locked on the address of
the particular key being pressed. The same action that stops the clock also triggers a
one-shot IC 5 which generates a key-pressed strobe. The output lines BO thru B3 will
contain the binary value of the pressed key while bit 7 is reserved for the strobe. The
three function keys are directly tied to input bits 4, 5, and 6. Three sections of IC 1
serve to dampen contact bounce. The EXEC and NEXT are tied in so they will generate
a key-pressed strobe when activated. Because the shift key is always used in conjuction
with another key, it is not connected to the strobe circuit.

It is important to recognize that the coding of this 19-key circuit is not ASCII. An
ASCII keyboard cannot be used directly with the software monitor outlined in this
book, unless you use only those ASCII keys that correspond to the coding of figure 5.4,
or rewrite the software monitor to accept ASCII rather than binary codes for each key.

n. ADDING A VISUAL DISPLAY

Once a keyboard has been added to ZAP, we are ready for program development.
The other key ingredient is a visual display that allows the programmer to examine in¬
struction statements and data. The least costly configuration is an LED display, prefer¬
ably hexadecimal because the software monitor is written that way. For the octal die-
hards, I've also included an octal display.

Hexadecimal displays may seem a trivial addition to an expensive computer system,
but it is sometimes these little helpful add-ons that make program debugging easier. I
don't intend that it should replace a CRT, but it's a necessary tool when debugging a
program and a necessity for using the ZAP monitor. It will never replace a stepper or a
break-point-monitor program, but it's great to display keyboard or I/O data quickly
with a single output instruction.

There are many ways to display hexadecimal on a 7-segment LED. Figure 5.5 is an

134 THE BASIC PERIPHERALS

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INPUT CODE

82S23 PROGRAM

7-SEGMENT DISPLAY

DCBA D7D6D5D4D3D2D1D0

0000 01110111 0

0001 01000001 1

0010 01101110 2

0011 01101011 3

0100 01011001 4

0101 00111011 5

0110 00111111 6

0111 01100001 7

1000 01111111 8

1001 01111001 9

1010 01111101 A

1011 00011111 b

1100 00110110 C

1101 01001111 d

1110 00111110 E

1111 00111100 F

Figure 5.5 A possible method for a hexadecimal lalch/decoder/driver using a standard 7-segment
LED.

a) This entire circuit would be needed to replace one HP7340. CS on the 82S23 can perform
the blanking function.

b) The program for the 82S23 (1C 2).

example of the usual brute force method using a PROM as a hexadecimal decoder. (A
method of programming the 82S23 was described in the article in the November 1975
issue of BYTE magazine entitled "A Versatile Read-Only Memory Programmer/' if you
choose to use this circuit.)

However, this approach uses an excessive number of components and most people
would not want to program a PROM. One alternative is to allow the computer to per¬
form the decoding and drive the 7-segment display through the transistors directly
from a latched 8-bit output port. Another way puts additional logic around a standard
7-segment decoder driver for the extra requirements. The former case necessitates a
computer program while the latter can involve as many components as figure 5.5.

Fortunately, there is a product on the market that can solve the problem. It is the
HP7340 hexadecimal LED display (from Hewlett Packard; equivalent displays are
available from other manufacturers). These hexadecimal digits depart from the stan¬
dard 7-segment format by using dots instead of bars and being capable of displaying a
capital "B" and "D" in hexadecimal. This is accomplished by controlling the comer
dots, which gives the appearance of "rounding." This ability discriminates a "B" from
an "8" or a "D" from a "0." There are 16 distinctly different characters.

An additional feature of the HP7340 is that each display circuit contains a 4-bit latch
and decoder/driver. This allows the display to be attached directly to the data bus. The
result is a single 8-pin hexadecimal display that successfully accomplishes the function
of all the circuitry of figure 5.5. The specifications of the individual pins are given in
figure 5.6.

5080-7340 PIN CONNECTIONS

PIN FUNCTION

1 INPUT B

2 INPUT C

3 INPUT 0

4 BLANK CONTROL (8LANK««-5V)

5 LATCH ENABLE (LATCH *0V)

6 GROUND

7 +5 VOLTS

8 INPUT A

Figure 5.6 The pin layout and functions for the HP7340 BCD to hexadecimal display. Similar displays
are produced by Dialite and Texas Instruments.

REAR VIEW

-0-EHlH3-

USD

5082-7340

XX XX

THE BASIC PERIPHERALS 135

Copyrighted material

Figures 5.7 and 5.8 demonstrate how the HP7340 can be configured to function as a
2-digit hexadecimal output port or a 3-digit octal port. An 8-bit latch is not required
because it already contains one. The HP7340s can be attached to the data bus as simply
as any other parallel output port and are strobed from the chip-select decoder outlined
earlier in the section on I/O decoding.

To utilize the software monitor properly, 6 hexadecimal displays (separated into 3
single byte displays) are necessary. Three bytes are required to display a particular H
and L address and the data contents of that location. The 6 hexadecimal displays
should have the following decoded strobes:

Output Port #

Logic Line

Display Parameter

ic#

DS5WR

MSD address field

30, 31

DS6WR

LSD address field

28, 29

DS7WR

data field

26, 27

MSD — Most Significant Digit
LSD — Least Significant Digit

A more complete description of each display function is described within the
monitor section, and a completed schematic showing how the 6 displays are attached
to the data bus is illustrated in figure 5.9.

Figure 5.7 An HP7340 hexadecimal latch/decoder/driver display.

Figure 5.8 An HP7340 octal latch/decoder/driver display. The HP5082-7300 can be substituted for the
HP5Q82-7340 in octal display applications. The HP7300 displays numerics only.

136 THE BASIC PERIPHERALS

Copyrighted material

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THE BASIC PERIPHERALS 137

Copyrighted material

Figure 5.9 A schematic diagram of the completed hexadecimal LED display.

. SERIAL INTERFACE

A serial communication capability is not absolutely necessary to make ZAP work,
although the software monitor supplied in this book supports a serial interface.

First a word about concept before we pursue the design details. Why would ZAP

need to communicate? When we discuss the serial cassette interface, you will under¬
stand that there are more advantages to it than appear presently. If future expansion is
in mind or commercially made peripherals such as a CRT or printer are ever added,
their interface will most likely be serial.

This last sentence is significant. Realize that I said nothing about communicating
with another computer. While talking to another computer over telephone lines re¬
quires a serial link, in general, standard peripherals such as CRTs and printers also
"talk" serially. Therefore, by designing a serial port to accommodate a printer, we also
gain the ability to talk with another computer.

Communication is simply the transfer of information from one device to another. In
the case of a CRT display unit, the computer sends character information for screen
display while the keyboard relays the user's input to the computer. Each end of the full-
duplex communication line must have a transmitter and a receiver. In both cases, the
information being transferred is ASCII data probably consisting of a 7-bit code and, in
some cases, an additional parity bit for error checking. This 7-bit data (ignoring the

parity bit) will appear on the lines of a parallel port. These 7 lines plus a ground
reference and a strobe (remember we have to tell the receiver when the data is valid)
can be brought out to the CRT input. Keeping that as a dedicated line from the comput¬
er to the CRT, we now want a similar line between the keyboard output and an 8-bit
parallel port on the computer. This requires an additional 9 lines. To further com¬
plicate matters, let's separate the terminal and the computer by 300 to 400 feet, as
might happen in some commercial computer systems. The result is that 400 feet of 18
lead (17 if you combine ground references) cable will cost more than the terminal. Also
realize that the TTL parallel output should not be used to drive lines longer than 20 feet
without special buffers/drivers; otherwise data errors could occur.

The solution to this costly wiring problem is to use serial rather than parallel com¬
munication. The parallel data is converted to serial and sent one bit at a time down a
single twisted pair wire. If buffers/drivers are needed for long distances, less are re¬
quired with the serial approach. Specially encoded "start" and "stop" bits included in
the serial transmission notify the receiver that valid data is being sent. For the above
example, only two pairs of wire are needed to perform "full-duplex" interaction (see
figure 5.10). In "half-duplex" mode this can be reduced to a single twisted pair, but syn¬
chronization of the shared communication line is more complicated. All serial
transmission references I shall make will be limited to full-duplex operation.

Figure 5.10 A block diagram of a full-duplex RS-232C communication link.

138 THE BASIC PERIPHERALS

Copyrighted material

Now that we agree that the communication should be serial, how do we accomplish
the parallel to serial conversion? The answer is a device called a UART (Universal
Asynchronous Receiver/Transmitter). Appendix C7 gives the specification informa¬
tion for the SMC COM2017 UART which is equivalent in function to the AY-5-1013A
(General Instruments). To minimize power supply requirements, a single +5 V
AY-3-1015 or TR1602 (Western Digital) can be substituted as I have done. The only
change from the specification sheet is that pin #2 is no longer tied to —12 V.

A UART's internal structure consists of a separate parallel-to-serial transmitter and
serial-to-parallel receiver joined by common programming pins. This means that the
two sections of the UART can be used independently, provided they adhere to the same
bit format that is hard-wire or software selectable on the chip.

The transmission from the computer to the CRT is done asynchronously and in one
direction only. The computer likewise receives data directly from the keyboard
through a dedicated line. As far as the computer is concerned, after reconversion to
parallel in the UART, this input device is communicating parallel data.

Actual data transmission follows the asynchronous serial format illustrated in figure
5.11. Using the keyboard as an example, when no data is being transmitted, the data
line is sitting at a mark (or "1" level) waiting for a key-pressed strobe. A key-pressed
strobe is a 1 to 5 ms positive pulse (it can be as short as 200 ns) indicating that a key¬
board key has been pressed, and that an ASCII code of that key is available for
transmission. This key-pressed strobe, which is attached to the data strobe of the
UART, causes the ASCII data to be loaded into a parallel storage buffer and starts the
UART transmission cycle. The serial output will then make a transition from a 1 to a 0.
This mark-to-0 start bit is 1 clock period long and indicates the beginning of a serially
transmitted word. Following the start bit, up to 8 bits of data follow, each data bit tak¬
ing 1 clock period. At the conclusion of the data bits, parity and stop bits are output by
the UART to signify the end of transmission. If another key is pressed, the process
repeats itself.

START DATA] DATA2 DATA3 DATA4 DATAS 0ATA6 0ATA7 DATA* PARITY ST0P1 ST0P2 START

0ATA1

0 *

,- r ~■

—i—

■—r - ’

— r —

1—

—1-

• m

r— t -

! lsb i
i i

MSB j

—j_

_i_

_L„

_1_

1_L_

Figure 5.11 A single data byte as it is transmitted in asynchronous serial format.

On the receiving end, the UART is continuously monitoring the serial input line for
the start bit. Upon its occurrence, the 8 bits of data are slipped into a register and the
parity checked. At the completion of the serial entry, an output signifying data avail¬
able is set by the UART and can be used as an input strobe to the computer. The UART
will not process additional serial inputs unless the data available flag is acknowledged,
and the data available reset line is strobed. Actual transmission can include or exclude
parity, have 1 or 2 stop-bits, and data can be in 5- to 8-bit words. These options are pin
selectable.

The following is a pin function description for the AY-5-1013, COM2017, or

AY-3-1015.

Pin § NAME

SYMBOL

FUNCTION

1 Vcc Power Supply

Vcc

+5 V Supply

2 Vcc Power Supply

Vcc

—12 V Supply (not con¬
nected on AY-3-1015)

3 Ground

GND

Ground

4 Received Data Enable

RDE

A logic "0" on the receivei
enable line places the re¬
ceived data onto the output

THE BASIC PERIPHERALS 139

Copyrighted material

5 Received Data Bits
thru
12

13 Parity Error

14 Framing Error

15 Over-Run

16 Status Word Enable

17 Receiver Clock

18 Reset Data Available

19 Data Available

20 Serial Input

21 External Reset

22 Transmitter Buffer Empty

lines.

RD8 These are the eight data

thru output lines. Received char-

RDl acters are right justified; the

LSB always appears on RD1.
These lines have three-state
outputs.

PE This line goes to a logic "1"

if the received character
parity does not agree with
the selected parity. Three-
state.

FE This line goes to a logic "1"

if the received character has
no valid stop bit. Three-
state.

OR This line goes to a logic "1"

if the previously received
character is not read (DAV
line not reset) before the
present character is trans¬
ferred to the receiver hold¬
ing register. Three-state.

SWE A logic "0" on this line

places the status word bits
(PE, FE, OR, DAV, TBMT)
onto the output lines. Three-
state.

RCP This line should have as an

input a clock whose fre¬
quency is 16 times (16 X)
the desired receiver data
rate.

RDAV A logic "0" will reset the

DAV line.

DAV This line goes to a logic "1"

when an entire character
has been received and trans¬
ferred to the receiver hold¬
ing register. Three-state.

SI This line accepts the serial

bit input stream. A marking
(logic "1") to spacing (logic
"0") transition is required
for initiation of data recep¬
tion.

XR Resets shift registers. Sets

SO, EOC, and TBMT to a
logic "1." Resets DAV and
error flags to "0." Clears in¬
put data buffer. Must be
tied to logic "0" when not in
use.

TBMT The transmitter buffer

empty flag goes to logic "1"
when the data bits holding

140 THE BASIC PERIPHERALS

Copyrighted material

23 Data Strobe

24 End of Character

25 Serial Output

26 Data Bit Inputs
thru

34 Control Strobe

35 No Parity

36 Number of Stop Bits

37 Number of Bits/

38 Characters

DS A strobe on this line will

enter the data bits into the
data bits holding register.
Initial data transmission is
in itiate d by the rising edge
of DS. Data must be stable
during entire strobe.

EOC This line goes to a logic "1"

each time a full character is
transmitted. It remains at
this level until the start of
transmission of the next
character.

SO This line will serially, bit by

bit, provide the entire trans¬
mitted character. It will re¬
main at logic "1" when no
data is being transmitted.

BD1 There are up to eight data

thru bit input lines available.

BD8

CS A logic "1" on this lead will

enter the control bits (EPS,
NB1, NB2, TSB, NP) into
the control bits holding
register. This line can be
strobed or hard-wired to a
logic "1" level.

NP A logic "1" on this lead will

eliminate the parity bit
from the transmitted and
received character (no PE
indication). The stop bit(s)
will immediately follow the
last data bit. If not used,
this lead must be tied to a
logic "0."

TSB This lead will select the

number of stop bits, one or
two, to be appended im¬
mediately after the parity
bit. A logic "0" will insert 2
stop bits. A logic "1" inserts

1 stop bit.

NB2, These two leads will be in-

NBl temally decoded to select

either 5, 6, 7 or 8 data bits/
character.

NB2 NBl Bits/Character

0 0 5

0 1 6

10 7

11 8

THE BASIC PERIPHERALS 141

Copyrighted material

EPS

39 Odd/Even Parity
Select

40 Transmitter Clock

TCP

The logic level on this pin
selects the type of parity
that will be appended im¬
mediately after the data
bits. It also determines the
parity that will be checked
by the receiver. A logic "0"
will insert odd parity, and a
logic "1" will insert even
parity.

This line should have as an
input a clock whose fre¬
quency is 16 times (16 X)
the desired transmitter data
rate.

The final serial interface configuration is shown in figure 5.12. Because a UART is a
three-state device, it can be attached directly to the data bus. Data is written into or
read from it 8 bits parallel as any other I/O port manipulation. To the computer, the
UART appears as one output and two input registers: status, transmitted data, and
received data. As with all data bus manipulations, data transfers are synchronized
through decoded strobes. The ZAP software monitor uses three port addresses to coor¬
dinate the hardware and software. To be compatible, they should be wired as follows:

Port #

Logic Line

Signal

02 INPUT DS2RD

03 INPUT DS3RD

02 OUTPUT DS2WR

READ DATA
READ STATUS
WRITE DATA

The primary focus of this chapter is the hardware section of the serial interface.
When connected directly to the data bus in this manner, there is no way to operate the
UART except under program control. Explanation of the protocol and the significance
of each UART register can be found in the section on the ZAP monitor.

There are two remaining hardware considerations: data rate and transmission signal
level. Data rate can be loosely termed as bits per second and refers to the transmission
speed along the twisted pair. Keep in mind that at lower data rates, only 8 of 11 bits of
each transmitted word are data; 1 start bit and 2 stop bits are used. While any transmis¬
sion frequency can be set on a UART, by adjusting the clock rate there are eight fre¬
quently used standard asynchronous transmission rates:

110

bps

150

bps

300

bps

600

bps

1200

bps

2400

bps

4800

bps

9600

bps

Using a special data rate generator chip and switch selector network shown in figure
5.12, ZAP can accommodate any of these specific frequencies. In normal operation,
most teletypes run at 110 bps, printers such as the DECwriter II at 300 bps, acoustic
telephone modems at 300 bps, and video terminals from 1200 to 19,200 bps. As you
can see, in theory, we can communicate with them.

Transmission rate is only part of inter-communication prerequisites. A computer
could be all TTL level logic while a peripheral used 15 V CMOS. They would be com¬
pletely incompatible. Therefore, it is necessary to have one additional standard that
governs the signal level of the transmissions. The most widely accepted and generally

142 THE BASIC PERIPHERALS

Copyrighted material

THE BASIC PERIPHERALS 143

Copyrighted material

Figure 5.12 The final serial interface configuration.

used standard is EIA RS-232C.

Although TTL levels could be used for communication, they are not suitable for
carrying signals more than 10 or 20 feet. The problem stems from the fact that only 2 V
separates a logic 1 or 0 rather than speed or drive capabilities. With only 2 V immunity
to noise, communication would be susceptible to interference from motors and
switches.

An industrial committee agreed to a standard interface to solve this problem as well
as to suggest standards for the industry. Modem equipment uses EIA RS-232C. This
specification applies not only to the specific voltages assigned to logic 0 and 1, but also
to the type of plug, pin assignments, source and load impedances, as well as to a vari¬
ety of other related functions.

The signal levels of RS-232C are bipolar and use a negative voltage between —3 and
— 15 V to represent a logic 1 and a positive 3 to 15 V to represent a logic 0. The region
between —3 V and +3 V helps our noise immunity and is a dead region. Even though
+ and —15 V would provide optimum transmission, +3 V and —7 V are also accept¬
able. However, try to maintain equal bipolar levels over long distances.

The basic ZAP computer requires +12, +5, and —12 V (—5 V is necessary for the
EPROM memory and is derived from the —12 V supply) supplies for operation. We
can use the positive and negative supplies to generate RS-232C voltage levels in a num¬
ber of ways. Figure 5.13 illustrates some RS-232C drivers, and figure 5.14 shows a cou¬
ple of receiver circuits. One from each selection would have to be attached to the serial
I/O pins of the UART for it to have complete RS-232C compatibility.

♦ 5V

♦ 5 TO +12V

♦ 5V

-12V

Figure 5.13 TTL to RS-232C drivers.

a) Using two transistors as a level shifter.

b) Using an opto-isolator as a level shifter.

c) Using a standard RS-232C line driver.

PINOUT OF MCI468
TTL TO RS-232C ORIVER

TTL

144 THE BASIC PERIPHERALS

Copyrighted material

PINOUT OF MCI489
RS-232C TO TTL RECEIVER

+ 5V

TTL

Figure 5.14 RS-232C to TTL receivers.

a) Using a transistor.

b) Using a standard RS-232C line receiver.

RS-232C CTl TTL RS-232C CTL TTL

IV. CASSETTE STORAGE INTERFACE

The last but by no means least of the enhancements we should add to ZAP is a cas¬
sette interface. With the keyboard and display, an operator will be able to write some
elaborate programs but, unless they are transferred into read-only memory storage,
they will be lost when power is turned off. Of course, the computer's power can be left
on constantly. But what if you want to develop a second program that must occupy the
same memory address space? The preferable solution is to have some medium that tem¬
porarily stores large memory blocks.

In large computer systems, this capability is achieved through hard-disk and 9-track
magnetic tape systems. These high-speed, high-volume media are beyond the personal
computing budget, but their value in large systems is obvious. A low price, lower per¬
formance alternative is an audio cassette storage system.

In general, a cassette storage interface consists of three major subsystems: a serial
transmitter/receiver; a hardware assembly that converts serial TTL data so it's audio
cassette compatible, and an application program that keeps track of what's going out
to tape and can load it back into the correct place. The basic configuration is illustrated
in block diagram form in figure 5.15.

UART

CASSETTE INTERFACE

ZAP

COMPUTER

I-

PARALLEL

SERIAL

CONVERTER

SERIAL

PARALLEL

converter

jJlGURE^lZ

TTL SERIAL
OUTPUT

FIGURE 5.16

FIGURE 5.17

RECORDER

AUX INPUT

EARPHONE

Figure 5.15 A block diagram of an audio cassette storage system.

THE BASIC PERIPHERALS 145

Copyrighted material

The serial transmitter/receiver section is nothing more than the LIART serial inter¬
face which we have already added. With MC1488 and 89 converters on its serial lines,
it communicates via a RS-232C. However, if you attach a cassette interface to these
lines, it can double as a storage device. An additional benefit is that serial data gener¬
ated by the UART will offer some compatibility between personal computing systems;
standard data rates and standard serial communication protocol will promote this.

The output of the UART is TTL. Even with the RS-232C drivers, the logic output is
still a DC level. Because audio recorders cannot record DC, the UART output must be
converted in some way. The solution is FSK (frequency shift keying). The TTL output
from the UART is converted into audio tones. One frequency represents a logic 0, and
a second represents a logic 1.

Figure 5.16 shows a circuit that will produce frequency shift keyed tones. A 4800 Hz
reference frequency is derived from the MC14411 data rate generator previously in¬
stalled. IC 2A and 2B function as a programmable divider chain. With a TTL logic 1 on
the input IC 2 divides the 4800 Hz by 2, giving a 2400 Hz output. When the input level
is changed to logic 0, it divides by 4, producing a 1200 Hz output. The FSK frequencies
are generated at a serial output rate of 300 bps and connected directly to the recorder
through the microphone or auxiliary input. (These frequencies and data rate are often
referred to as the Kansas City Standard.)

♦ 5V

Figure 5.16 A 300 bps serial output driver to an audio recorder.

Getting the recorded tones off the audio tape requires the circuit shown in figure
5.17. In general, it consists of a pair of band-pass filters and a voltage comparator. The
recorder is set to an output level of approximately 1 V peak to peak. This level is not
critical because it is amplified and limited as it passes through IC 1. IC 2 and IC 3 are
band-pass filters with center frequencies of 2400 Hz and 1200 Hz, respectively. The
output of IC 1 is fed into both of them, but should be passed by only one. IC 4 com¬
pares the outputs of the two filters and generates a TTL logic 1 when a 2400 Hz tone is
received and a logic 0 with a 1200 Hz tone. Tuning the interface will be explained later.

The choice of the FSK frequencies and data rate are not left to chance. They are a
function of receiver response speed and recorder bandwidth. Most cassette recorders
have a frequency response of around 8 kHz. Less expensive units can be as low as 5 or
6 kHz. It is unwise to try to record tones at this upper limit. The center of the frequency
range offers more reliability, so the logic "1" FSK tone should be set less than 3 kHz
(2400 Hz in our case). In addition, it takes time for the receiver to recognize a particular
frequency. The circuit of figure 5.17 takes 2 or 3 cycles to respond. This means that at
the low frequency of 1200 Hz, each logic 0 bit will need 3 cycles at 1200 Hz to be recog¬
nized.

146 THE BASIC PERIPHERALS

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BANDPASS FILTER
1200 Hz

*: *-
«•> o o

THE BASIC PERIPHERALS 147

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If we consider a worst case condition of sending all zeros, the transmission rate
would have to be slower than 400 bps to be accurately received. The closest standard
data rate to this value is 300 bps. Raising the 1200 Hz tone to increase the transmission
speed only complicates the filter design the closer it is to 2400 Hz. This interface has
been tested at 600 bps but it requires precise alignment to achieve faster speeds. The
low frequencies and moderate data rate are chosen specifically to increase the prob¬
ability of successful construction rather than to compete with high speed data storage
systems.

The final point to consider is the software that runs the hardware. The ZAP monitor,
as it now stands, does not directly support a cassette interface even though it does han¬
dle all the serial housekeeping. Until you write the cassette driver into an EPROM, you
will have to type in a short "bootstrap" program. To read the cassette, the logic of the
program would follow the flow diagram in figure 5.18.

First, a pointer is set in the H and L registers to designate where the cassette data will
be stored in programmable memory and an address where it will end. Next, taking ad¬
vantage of the serial communication routine in the ZAP monitor, we simply call
"SERIAL IN" which returns with a byte of data from the UART. This byte is stored in
memory, and the HL register pair is decremented and compared to a predetermined
stop address. If not equal, it repeats the process of getting another byte of data.

Storing memory is equally straightforward and is diagrammed in figure 5.19. Again,
a pointer is set to the beginning and the memory area to be written to tape. Next, the
"SERIAL OUT" routine is called from the ZAP monitor, which sends the byte of data
to the cassette. Finally, the pointer is decremented and compared to the end address to
see if more data is to be written.

These are relatively easy routines to write and short enough that they may be
squeezed into the few empty bytes within the ZAP monitor EPROM. Whatever the
case, you will soon realize the versatility and capability that such a simple interface
adds to a computer system. The 2 K of programmable memory on the basic ZAP will
become resident program space while the cassette will be a potential megabyte file stor¬
age system for it.

Figure 5.18 A flowchart of software to read a cassette.

148 THE BASIC PERIPHERALS

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Figure 5.19 A flowchart of software to write a cassette.

TUNING THE CASSETTE INTERFACE

To test the cassette interface, it is necessary first to construct the circuit from figure
5.16. Use a frequency counter to determine that the input to IC 1, pin 5 is 4800 Hz.
With no UART installed, the frequency at pin 1 of IC 2b should be 2400 Hz. Ground¬
ing IC 2b, pin 1 should change this output to 1200 Hz. In both cases, voltages of 1 and
0.1 V should be present on the cassette auxiliary and microphone inputs respectively.

The receiver uses the frequencies generated by the output section previously de¬
scribed to set the calibration. With the output section set to 2400 Hz, attach a jumper
from the output interface to the input of the receiver circuit (figure 5.17). Using an
oscilloscope, check that the waveform at IC 1, pin 6 is a square wave of 2400 Hz. Next,
with the scope attached to IC 2, pin 6, adjust R1 until the voltage at that point is max¬
imum. Moving the scope probe to IC 3, pin 6, and changing the input frequency to
1200 Hz, repeat the procedure by adjusting R2 until the voltage peaks.

R3 sets the point at which the comparator switches between logic levels when the in¬
put frequencies change. The proper way to set this is to use a function generator on the
input and set R3 to switch at exactly 1800 Hz. The result should be clean logic level
switching at IC 4, pin 6, as the frequency is cycled between 1200 Hz and 2400 Hz. Gen¬
erally speaking, the comparator setting is not especially critical.

THE BASIC PERIPHERALS 149

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CHAPTER 6

THE ZAP MONITOR

SOFTWARE

The function of an operating system is to provide the programmer with a set of tools
to help him in developing, debugging and executing a program. In general, the operat¬
ing system assists the programmer by managing the resources of the computer, and by
eliminating his involvement with repetitive machine-code manipulations. Operating
systems span a broad spectrum of complexity. Small systems, for example, provide
only a rudimentary means for a programmer to enter and read 8-bit data from mem¬
ory; large systems, on the other hand, can dynamically manage the allocation of all
memory and peripherals.

Large systems allocate computer resources to more than one user in a multiprogram¬
ming, multitasking, or a time sharing environment. A system of this magnitude far ex¬
ceeds the capabilities of the computer described in this book. This being the case, what
would be a suitable operating system for the ZAP computer? As previously stated, the
objective of an operating system is to manage the resources of the computer. The ZAP
computer described in the previous chapters, and enhanced with the minimum periph¬
erals, contains the following resources:

• Z80 microprocessor

• 1024 bytes of EPROM memory

• 1024 bytes of programmable memory (2048 optional)

• Nineteen-key keyboard

• Two-character data display

• Four-character address display

• UART for serial I/O

The operating system must provide access to these resources and give the user a way
to manage them during execution of programs. The operating system designed for ZAP
will include the following facilities and functions:

1. Cold start

2. Warm start

3. Memory display and replace

4. Register display and replace

5. Execute (begin program execution at a
designated point)

6. Serial input and output

Each will be explained in detail concerning its functions and program implementa¬
tion.

I. OPERATING SYSTEM FUNCTIONS
Cold Start Operation

The operating system must be available immediately after power is applied to

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the computer. In the past, some systems provided this capability by storing, in
read-only memory, a small "bootstrap" routine. This bootstrap routine was then
used to load the operating system into memory from another device, such as a
paper-tape reader or a cassette recorder. New technology eliminates this tedious
step. The operating system for your computer resides permanently on the
EPROM (erasable-programmable read-only memory) chip and is ready to be ex¬
ecuted as soon as power is applied and the "RESET" button is pressed. The
depression and release of the "RESET" button sets the Z80 PC (program counter)
to zero.

With the next machine cycle, the processor begins execution of the instruction
located at 00,6 (location 00 hexadecimal) in memory. The operating system of the
Z80 microprocessor provides the instructions to begin execution. This particular
series of program instructions constitutes a "cold start" procedure and establishes
the required start up conditions for the operating system. The operating system
then initializes the SP (stack pointer) to an area in programmable memory for
maintaining the "push-down/pop-up" stack. This stack is required for execution
of any of the "RESTART" and "CALL" instructions provided by the Z80 instruc¬
tion set. If it were not initialized before the execution of a "CALL" or "RESTART"
instruction, the effects of the instruction would be unpredictable. In this
operating system, the stack pointer is set to programmable memory location
07C4,«.

Warm Start Operation

After initializing the SP address, the operating system enters a command
recognition module. Before discussing this feature of the operating system, some
of the other restart features should be explained. The Z80 gives the user eight
address-vectored "RESTART" instructions (see Chapter 3 for a description of the
instructions). For example, the execution of a RST 08, 6 will store the current PC
on the "STACK" and program execution will begin at location 08, 6 .

The following "RESTART" instructions are available within the operating
system:

RST 10,6
RST 18,6
RST 20,6
RST 28,6
RST 30,6
RST 38,6

The execution of any of these instructions causes the operating system to jump
to a location in programmable memory. At that location the user executes a jump
instruction to vector the computer to a new location.

RST 00,6 and RST 08, 6 have been reserved for use by the operating system for
special functions and will not result in a jump to a location in programmable
memory. These two RST instructions can be utilized in the debugging of pro¬
grams. RST 00,6 will perform the same function as pressing the "RESET" button;
or it will reinitialize the stack pointer and enter the command recognition module
through execution of the "cold start" routine.

The execution of a RST 08, 6 by the Z80 will result in the "warm start" module
being entered. This module saves the existing data in all the registers in the "regis¬
ter save area" located in programmable memory (see the listing of the ZAP oper¬
ating system in Appendix D). The module will also extract from the stack the
user's restart address and save this in the register save area. The operating system
then enters the command recognition mode to wait for the next command. The
use of this feature allows the programmer to save register, pointer, flag, and pro¬
gram counter data, prior to using any additional debugging features in the oper¬
ating system. A detailed description of the "warm start" module is provided in
section II.2 of this chapter.

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Program Development and Debugging Services

The cold start and warm start procedures exit to the command input sequence.
With these command procedures, the programmer is able to examine and replace
data in memory or registers, and to begin execution at a user-specified location.
Upon entry to the command input module, the operating system displays "FFFF"
on the address section, and "FF" on the data section of the six character hexa¬
decimal LED display. The user then implements one of the three command func¬
tions by holding down the "SHIFT" key and pressing the "0," "1," or "2" keys. A
"SHIFT 0" (the SHIFT key and 0 key are pressed simultaneously) tells the
operating system to enter the memory display and replace function; "SHIFT 1"
enters the register display and replace function, and a "SHIFT 2" enters the go ex¬
ecute module.

Memory Display and Replace

The memory display and replace function allows the user to examine the con¬
tents of both read-only memory and programmable memory. During operation
the address and the contents of that location are shown on the respective dis¬
plays.

The memory display and replace function is entered by executing a "SHIFT 0"
when the system is in the command recognition mode (address display = FFFF
and data display = FF). At this time, the operating system is waiting for the user
to enter an address of one to four hexadecimal digits from the keyboard. As
entered, these shift into the display area sequentially. If more than four digits are
entered, only the last 4-digit value (shown in the address display) will be used as
the address. Inputting of address data is terminated by pressing the "NEXT" key.
This causes the contents of the indicated address to be displayed on the two digit
hexadecimal data display. If the user wishes to display subsequent memory loca¬
tions, he need only continue pressing the "NEXT" key. This will step the memory
display program to the next higher memory location and display the new address
and memory contents. If the user wishes to change the contents of a displayed
memory location, he may enter new data by typing a two-digit value for that
location before hitting the next key. This new value is loaded into the indicated
address when the "NEXT" key is pressed. Pressing the "NEXT" key continues the
sequential display of address and data.

Termination of this function is accomplished by pressing the '"RESET" or
"EXEC" buttons. Control is returned to the command recognition portion of the
operating system.

Display Memory Example

Key

Address Display

Data Display

FFFF

SHIFT 0"

0000

0001

001A

01AF

"NEXT"

01AF

"NEXT"

01B0

"RESET"

FFFF

Memory Replace Example

Key

Address Display

Data Display

FFFF

SHIFT 0"

0000

0004

0040

0400

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"NEXT"

0400

"NEXT"

0401

"EXEC"

0401

The results will be: Address

Data

0400

0401

The register display and replace function allows the user to examine and

change the contents of the saved Z80 registers. This

is accomplished by executing

a RST 1 (warm start) during the execution of the program. During execution of

this function, the contents of the registers are shown

on the address display.

Eight-bit registers will be displayed on the lower two digits of the address display.

(The upper two digits will be

zeros during the display of 8-bit registers.) A code

that indicates which register

is being displayed is

shown on the data display.

Table 6.1 describes the codes that have been assigned to the register display and

replace function, as well as the key that initiates a

particular register display se-

quence.

Code

Z80 Register

Initiating Key

(shown on data display) (shown

on address display)

"SHIFT 0"

"SHIFT 1"

"SHIFT 2"

"SHIFT 3"

"SHIFT 4"

"SHIFT 5"

"SHIFT 6"

“SHIFT 7“

Table 6.1 Display code/Z80 register/initiating key correspondence.

The register display and replace function is entered by pressing a "SHIFT 1"
when the system is in the command recognition mode (address display = FFFF
and data display ™ FF). At this time the operating system is waiting for the pro¬
grammer to enter the one-digit register code (see table 6.1). If more than one digit
is entered, only the last code indicated on the data display will be used as the reg-

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ister identifier. When the central processor detects that the "NEXT" key has been
depressed, the contents of the indicated register are displayed on the address dis¬
play.

If the user wishes to display subsequent registers he need only press the
'NEXT" key. This causes the next register to come up with the register code and
its contents. To change the contents of a displayed register the value is entered
and loaded when the 'NEXT" key is pressed. For 16-bit registers, the last four
hexadecimal digits will be accepted if more than four characters have been
entered. For 8-bit registers the last two hexadecimal digits will be accepted. When
replacing register data, the 'NEXT" key also causes the register code to be in¬
dexed to the next register (see table 6.1) and its contents to be displayed.

The user may terminate this function by pressing the "EXEC" key. Control is
returned to the command recognition portion of the operating system.

Display Register Example

Key

Data Display

Address Display

(register code)

(register contents)

FFFF

"SHIFT 1"

FFFF

'NEXT"

005C

'NEXT"

0063

"RESET"

FFFF

Key

Data Display

Address Display

(register code)

(register contents)

FFFF

"SHIFT 1"

FFFF

'NEXT"

043A

0004

0042

042C

'NEXT"

00FF

'NEXT"

0003

"EXEC"

Co Execute ("EXEC")

The "go execute" ("EXEC") function allows the user to change the contents of
the PC (program counter) register in order to direct execution of instructions at
the user-selected address.

The "go execute" function is entered by pressing a "SHIFT 2" when the system
is in the command recognition mode. Now the user must enter an address of one
to four hexadecimal digits. If more than four digits are entered, only the value
shown in the address display is used as the address to begin program execution.

Execution begins when the 'NEXT" or "EXEC" keys are pressed. This causes the
Z80 registers to be stored in the register save area (see the operating system listing
in Appendix D) and execution begins at the user-specified address.

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Key

GO EXECUTE Example

Address Display

Data Display

FFFF

"SHIFT 2"

0000

0001

001A

01AC

1ACF

"NEXT"

"EXEC"

Serial I/O Services

The ZAP computer includes a serial input/output capability that is imple¬
mented with a UART. This interface allows serial communication between the
computer and peripheral devices such as a printer or a CRT. To aid the user in
utilizing this capability, the operating system has a UART diagnostic module, a
serial input module, and a serial output module. The input and output modules
are set up as subroutines that can be called during program execution and that are
not necessarily keyboard and display limited.

UART Diagnostic Module

The UART diagnostic module provides a means for checking the performance
of the UART. To utilize this feature the user must first attach the serial output
and input lines together so that data output from the UART may be read by the
same device. The serial diagnostic subroutine is initiated by using the "go
execute" function. Execution starts at 032D,«.

Once started, the diagnostic module (UATST) begins by sending data to the
UART and waiting for data to become available. The status of the UART is
checked to verify that no fault conditions are present. In the event that a fault is
detected, the status of the UART is displayed on the two low-order digits of the
address display. (See table 6.2 for error codes.) If there are no errors, the data is
read and displayed on the two-digit-data display. A comparison is made between
the input and output data. If the 2 bytes are equal, the output character is incre¬
mented and another byte is sent to the UART to continue the sequence. This pro¬
cedure continues until the "RESET" button is pressed, or until an error is
detected. In the event that the input character does not equal the output charac¬
ter, a 0F,« is displayed in the two lower digits of the address display and the
diagnostic is halted. Figure 6.1 details the logic flow of this software routine.

Displayed Code

12,6 or 13,6
0A,6 or OB, 6
06,6 or 07,6
00
OF,*

Error

Parity Error
Framing Error
Overrun Error

Transmitter Buffer Not Empty
Input Character ^ Output Character

Table 6.2 UART error codes.

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Figure 6.1 A flowchart of the UART diagnostic module (UATST).

Serial Input Module

The serial input module has been included so the user can read serial data from
external devices. To utilize this capability, the user must set aside a program¬
mable memory buffer where the input data is to be stored, and designate the
number of input characters expected. The input buffer address is stored at address
07F9i6 in memory (see Appendix D), and the number of characters is stored at ad¬
dress 07FD,«. The communication reception begins when the TTYINP module is

called.

Seria

i Input Initiation Example

TTYINP

EQU

035F.6

Address of input module

BUFFER

EQU

07F9i«

Input buffer address

NCHAR

EQU

Number of characters to be received

TTYIBU

EQU

07F9i6

Operating system address constant

TTYIC

EQU

07FD i4

Operating system address constant

LD HL, BUFFER
LD (TTYIBU), HL

Set buffer for operating system

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LD A, NCHAR
LD (TTYIC), A
CALL TTYINP

Set character count for operating system
Call UART serial input routine

The data read by the serial input module will be stored in the user-specified
buffer until the input sequence is terminated. When this occurs, control is re¬
turned to the user's program at the next instruction. Termination of the input pro¬
cess may be due to any of the following conditions:

• A status error is detected

• The number of characters read equals preset count

• The receipt of a carriage return as an input
character (ASCII 0D 16 )

In the event that a status error is detected, the A register will be equal to 80, 4
when control is returned to the user. If termination results from filling the charac¬
ter buffer correctly, the A register will be equal to 00, 4 . However, if termination is
the result of a carriage return, the A register will be equal to the number of char¬
acters remaining to be input. Figure 6.2 details the logic flow of the TTYINP soft-

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Serial Output Module

The serial output module is provided to assist the user in communicating serial

output data to external devices. To use this module, the operator designates an

output data buffer address and the the number of characters (bytes) to be trans¬
mitted. The output buffer address must be stored at 07FB, 6 in memory (sec Ap¬
pendix D) and the number of characters to be sent is stored at address 07FE 16 .
Data transmission starts when TTYOUT is called.

Serial Output Initiation Example

TTYOUT

EQU

039E,6

BUFFER

EQU

07FB,6

NCHAR

EQU

TTYOBF

EQU

07FB,6

TTYOC

EQU

07FE,6

HL, BUFFER

(TTYOBF), HL

LD A, NCHAR
CALL TTYOUT

Address of output module

Output buffer address

Number of characters to be transmitted

Operating system address constant

Set buffer address for operating system

Set character count for operating system
Call UART serial output routine

Control will be returned to the user when

• The output buffer is empty

• The transmit buffer does not become available,
indicating an error

In the event that a normal termination occurs, the A register will be equal to
00,6 when control is returned to the user. However, if a premature termination
and return are required, the A register will be equal to 01, 6 . Figure 6.3 details the
logic flow of the serial output software module.

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II. Operating System Module Description
II.l Warm Start Module

The warm start module (WARMl) is responsible for saving all Z80 registers in
the register save area allocated in the reserved portion of programmable memory
(see Appendix D). Upon entry, the user's A, H, and L registers are saved to pro¬
vide working registers for the remainder of the module operation. Next, the user's
PC is removed from the stack and is saved in the memory locations reserved for
it.

The AF register pair is pushed onto the stack and popped off into the HL regis¬
ter pair. This procedure enables the flag register to be saved in the register save
area. The remainder of the user's working and alternate registers are examined
and transferred to the register save area. Upon completion of this task, the
module exits to the command recognition module. (See Appendix D for addi¬
tional details.) Figure 6.4 details the logic flow of the warm start module.

Figure 6.4 A flowchart of the warm start module (WARMl).

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II.2 Command Recognition Module

The command recognition module (WARM2) is entered after the completion of
a cold or warm start sequence. When initiated, the module clears the keyboard
input buffer and the keyboard flags. This removes ambiguity for future opera¬
tions. The module will set the data display to FF and the address display to FFFF.
When completed, the module enters the KEYIN subroutine to get an input charac¬
ter from the keyboard. Any input character is checked to see if it corresponds to
one of the three allowable functions. If so, control is transferred to the proper
function; otherwise, the input is ignored and the module waits for the next input
from the keyboard. (See Appendix D for additional details.) Figure 6.5 illustrates
the logic flow of the command recognition module.

Figure 6.5 A flowchart of the command recognition module (WARM2).

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11.3 Restart Module

The restart module (RESTRT) takes the values stored in the programmable
memory register save area. It then restores the user's 8- and 16-bit registers before
returning control to the location specified in the PC save area. This procedure
restores the alternate registers, and then the working registers. In either instance,
the flag registers are restored by pushing the data onto the stack and then popping
if off to the F register. In order to exit to the user's restart address, the saved PC is
pushed onto the stack and a "RET" (return instruction) is executed. (See Appen¬
dix D for additional details.) Figure 6.6 details the logic flow of the restart
module.

Figure 6.6 A flowchart of the restart module (RESTRT).

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II.4 Keyboard Input Module

The keyboard input module (KEYIN) provides the primary interface between
the computer and the user. Upon entry, it begins to read data from the keyboard
input port. It stays in a loop, checking the MSB (most significant bit) of the data.
The MSB is the key-pressed strobe. When it goes to a logic one level, the seven
LSBs (least significant bits) of the keyboard input port are retained as the desired
input character. The module then returns to the user's program with the key¬
board character in the accumulator. (See Appendix D for additional details.)
Figure 6.7 details the logic flow of the keyboard input module.

Figure 6.7 A flowchart of the keyboard input module (KEYIN).

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II.5 One Character Input Module

The function of this module (ONECAR) is to input one or more characters
from the keyboard. This module also indicates the last character and whether it
was accompanied by a "NEXT" or "EXEC" key.

Upon entry, the input buffer and keyboard flags are cleared. (The data display
may or may not be cleared depending on the requirements of the calling module.)
The module waits for an input character to be passed to it. When it receives a
character, it checks to see if it is a 'NEXT" "EXEC", or valid data. In the event
that the input is a "NEXT" or "EXEC", the appropriate keyboard flag is set along
with the no data flag and control returned to the user (see figure 6.8).

If an invalid data character is received, the module is reinitiated. Upon receipt
of valid data, the data is stored in a 1-byte input buffer, and the module waits for
the next input character. This character is processed in a manner similar to the
one just described with the following exception: in the event that the input char¬
acter is a "NEXT" or "EXEC", only the appropriate flag is set before returning
control to the user. (See Appendix D for additional details.) Figure 6.9 shows the
logic flow of the one character input module.

BIT 7 6

5 4

1 0

□

E | N

NEXT FLAG
EXEC FLAG
NO DATA FLAG

Figure 6.8 The configuration of the keyboard flags.

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11.6 Two Character Input Module

The function of this module (TWOCAR) is to input one or more characters
from the keyboard and transfer to the user the last two characters when a
"NEXT" or "EXEC" key is pressed. The module also notifies the user of the type
of termination that took place.

Upon entry, the input buffer and keyboard flags are cleared. (The data display
may or may not be cleared depending on the requirements of the calling module.)
This module calls the keyboard input module to obtain its input data. The first
character is checked to determine if it is a "NEXT" or "EXEC"; the appropriate
keyboard flag is set along with the no data flag, and control is returned to the user
(see figure 6.8). If an invalid character is received, the module is reinitiated.

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The receipt of valid data will cause the module to format the data as a two-digit
value in the keyboard input buffer. It then returns to the user with the ap¬
propriate flags set. (See Appendix D for additional details.) Figure 6.10 details the
logic flow of the two character input module.

Figure 6.10 A flowchart of the two character input module (TWOCAR).

11.7 Four Character Input Module

The function of this module (FORCAR) is to input one or more characters from
the keyboard and to transfer to the user the last four characters when a "NEXT"

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or "EXEC" key is pressed. In the event that less than four characters are input, the
higher order digits will be set to zero. The module also notifies the user via the
keyboard flags (see figure 6.8).

The operation of this module is very similar to the two character input module.
The main difference lies in the manner in which the new data (input from the key¬
board) is merged into previous input data from the keyboard. (See Appendix D
for additional details.) Figure 6.11 shows the logic flow of the four character in¬
put module.

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II.8 Memory Display and Replace Module

The memory display and replace function is one of the three major modules of
the operating system. Upon entry (see command recognition module), this
module (MEMORY) makes a call to FORCAR (four character input module) to
get the base memory address at which to begin displaying the memory contents.
When it returns from FORCAR, the keyboard flags are examined to determine if
the "EXEC" flag is set ( = 1). In the event that the "EXEC" flag is set, control is
transferred to the restart module (RESTRT). If the "EXEC" flag is not set (=0),
the address location and memory contents are output to the appropriate displays.
The TWOCAR (two character input module) is called to obtain new data from
the displayed memory location.

Figure 6.12 A flowchart of the memory display and replace module (MEMORY).

168 THE ZAP MONITOR SOFTWARE

Copyrighted material

When control is returned from TWOCAR, the module checks the "no data"
flag in the keyboard flag word. If this flag is set ( = 1), the "EXEC" flag is exam¬
ined. If that is set, control is transferred to the command recognition module
(WARM2). If, on the other hand, the "EXEC" flag is reset (=0), the user's
memory address is incremented, displayed on the address display, and its con¬
tents are displayed on the data display.

If, on return from TWOCAR, the "no data" flag is reset (=0), the new data is
extracted from the keyboard input buffer and stored in the displayed memory
location. At this time, the module determines if TWOCAR was exited via an
"EXEC" or "NEXT" directive. In the event that the "EXEC" flag is set ( = 1), con¬
trol is transferred to the command recognition module (WARM2). If, however,
the flag is reset (— 0), the user's memory address is incremented, displayed on the
address display, and its contents are displayed on the data display. Then the two
character input module is called to get the next directive for the memory display
and replace module. (See Appendix D for additional details.) Figure 6.12 shows
the logic flow of the memory display and replace module.

II.9 Register Display and Replace Module

The register display and replace module (REGIST) is one of the three major
modules of the operating system. This module calls the ONECAR (one character
input module) to get the initial register display code from the user (see table 6.1).
Upon return from ONECAR, the "EXEC" flag is checked. If this flag is set (=*1),
control is transferred to the command recognition module (WARM2). If the
"EXEC" flag is reset (=*0), the base register display index is calculated from the
user's register display code.

At this time, the register index is checked to see if the register request is an 8- or
16-bit register. If the user requests a 16-bit register, the appropriate register code
is displayed in the data display, and the requested register data is obtained from
the register save area and displayed in the address display. The module then
makes a call to the FORCAR (four character input module) to get new data for
the register. Upon return, the "no data" flag is checked. If this flag is set and the
"EXEC" flag is set, control is transferred to the RESTRT (restart module). If the
"no data" and "NEXT" flags are set, the register display index is incremented and
displayed in the data display. The new register data is obtained from the register
save area and displayed on the address display.

If an 8-bit register has been requested, the register code (see table 6.1) is dis¬
played in the data display, and the appropriate data is obtained from the register
save area and displayed on the address display. At this time, the module calls
TWOCAR to get new data from the displayed register. When the two character
input module returns control, the module determines the mode of execution by
examining the keyboard flags. If the "no data" and "EXEC" flags are set, control
is transferred to the command recognition module (WARM2). If the "no data"
and "NEXT" flags are set, the register index is incremented and the register con¬
tents channeled to the appropriate display.

If the "no data" flag is reset, the new register data is obtained from the key¬
board input buffer and stored in the appropriate register save location. At this
time the "EXEC" flag is checked and, if set, control is transferred to the command
recognition module (WARM2). If the "EXEC" flag is reset, the register data is dis¬
played and the user directive processed. (See Appendix D for additional details.)
Figure 6.13 details the logic flow of the register display and replace module.

THE ZAP MONITOR SOFTWARE 169

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Figure 6.13 A flowchart of the register display and replace module (REGIST).

i70 THE ZAP MONITOR SOFTWARE

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11.10 Go Execute Module

The go execute module (GOREQ) is the last of the three major functions of the
operating system. Upon entry (see command recognition module), this module
calls FORCAR to get the address where execution is to begin. Upon return from
FORCAR, the "no data" flag is examined to determine the mode of execution. If
this flag is set ( = 1), control is immediately transferred to RESTRT. This restores
the Z80 registers and resumes execution at the PC address currently contained
from the keyboard input buffer and stored in the PC save location in the register
save area. Control is then transferred to the command recognition module
(WARM2) which will restore the registers with the saved data, and begin execu¬
tion of the user's program at the specified address. (See Appendix D for addi¬
tional details.) Figure 6.14 details the logic flow of the go execute module.

Figure 6.14 A flowchart of the go execute module (GOREQ).

THE ZAP MONITOR SOFTWARE 171

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CHAPTER 7
PROGRAMMING AN

EPROM

The ZAP computer has been designed to be inexpensive, reliable, and easy to con¬
struct. To keep costs and complexity to a minimum, some computer features that could

be helpful to a beginner have been eliminated. The most visible of the missing features

are a front panel and display. While this in no way detracts from the operation of the
computer, its inclusion would make initial checkout and program development easier.

To properly test ZAP, a program must be in memory. This program does not have
to be very long—only a few instructions are necessary to determine whether the com¬
puter runs at all. The problem arises when the user wishes to run a program of 50 or
100 bytes in length. We end up with a "catch-22" situation. To effectively enter ma¬
chine code into ZAP's programmable memory, a program that coordinates this activity
must be running in EPROM. Such a program is called a monitor and is outlined in
Chapter 6. The catch is that writing the monitor software into an EPROM automatical¬
ly requires the monitor to be running the programmer. Fortunately, if one has an alter¬
nate way of writing the 1 K ZAP monitor into EPROM, this is no longer a problem.

Rather than leaving the experimenter to his own devices, this section includes infor¬
mation on programming EPROMs. To solve the startup situation. I've outlined a de¬
sign for a couple of manual EPROM programmers. Loading programs on a manual
programmer is tedious. They are primarily intended for much shorter routines such as
checking basic system operations. However, one manual unit can be modified to load
the full 1 K monitor software. When ZAP is fully operational, you can use it in con¬
junction with an automatic programmer. This will help in writing a number of
EPROMs. In the event that you do not wish to write your own EPROM, consult Ap¬
pendix A for the availability of preprogrammed EPROMs.

A Quick Review of EPROMs

It is often desirable to have the non-volatility of ROMs but the read/write capa¬
bilities of semiconductor programmable memories. An effective compromise is the
EPROM. This is a read-mostly memory. It is used as a ROM for extended periods of
time, occasionally erased and reprogrammed as necessary. Erasure is accomplished by
exposing the chip substrate, covered by a transparent quartz window, to ultraviolet
light. We'll cover erasure at the end of this chapter.

The EPROM memory element used by Intel and most other manufacturers is a stored
charge type called a FAMOS transistor (Floating-gate Avalanche injection Metal Oxide
Semiconductor) storage device. By selectively applying a 25 V charging voltage to ad¬
dressed cells, particular bit patterns that constitute the program can be written into the
EPROM. This charge, because it is surrounded by insulating material, can last for
years. Exposure to intense ultraviolet light drains the charge and results in the erasure
of all programmed information.

There are many EPROMs on the market—2708s, 2716s, and 2732s are the major
ones. For the most part, computerists have moved away from the very difficult-to-
program 1702s and have opted for the more easily programmed 2708s and 2716s. An
added benefit is their greater storage density. The newer EPROMs on the market are
considerably more expensive than the 2708. All things considered, the 2708 is the best

PROGRAMMING AN EPROM 173

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buy for the money. At slightly greater expense, you could use the 2758 for a single sup¬
ply operation. For these reasons, the EPROM programmer outlined in this chapter is
the 2708.

Figure 7.1 is the circuit for a manual 2708 programmer. IC 5 and two sections of IC 3
provide the +25 V program pulse to the EPROM. IC 5 is set for a duration of 1 ms and
is triggered by a logic 0 to 1 transition at its input. The EPROM both sources and sinks
current through programming pin 18. A combination of devic es rath er than a simple
open-collector driver is necessary. In the write mode, when CS/WE pin 20 is at
+ 12 V and between programming pulses, pin 18 has to be pulled down by an active
device because it sources a small amount of current. The programming pulse itself is
about 30 mA and cannot easily be accommodated without emitter-follower configured
Ql. This pulse should be between 25 and 27 V at pin 18. Three 9 V batteries will suf¬
fice. (An alternative is to use a commercial encapsulated 24 V, 50 mA puwer supply.
The encapsulated supply can be resistor trimmed to produce the desired 25 to 27 V.)

To write a byte into the EPROM, a 10-bit address designating which of the 1024
bytes will receive the data is preset on switches SW 1 thru SW 10. To start at location
0, all switches will be in the closed position. Next, the 8 bits that are to be stored are set
on switches SW 12 thru SW 19. This data byte should be reflected on the output dis¬
play LED 1 thru LED 8. Finally, to get the programmer in the write mode, switch
SW 11 is set open. Actual insertion of the data occurs when the write pulse pushbutton
PB 1 is pressed. This fires a 1 ms pulse of 25 V into the 2708 program pin. According to
manufacturer's specifications, no single programming pulse should be longer than
1 ms. For maximum data retention, 100 of these programming pulses are recommended
(totalling 100 ms per byte).

Unfortunately, 100 ms cannot be applied to a single address all at once. Manufac¬
turers specify that it should be done sequentially and should consist of 100 1-ms ap¬
plications. In short, it means that for a 25-byte program, each address should be writ¬
ten with one pulse and then the loop repeated up to 100 times. I have never tried to
lengthen the pulse and program a 2708 faster than called for. Experience has shown,
however, that some EPROMs are completely written with as few as 2 or 3 loops. Ob¬
viously, for full retention each address should be rewritten on an automatic program¬
mer.

Reading back the stored contents of a 2708 is easy on the same manual programmer.
First, all data input switches SW 12 thru SW 19 are opened to the "1" state and then
"read/write" switch SW 11 is set in the closed or "read" mode. No other pulsing or
clocking is necessary. The output display will show the contents of the byte pointed to
by the address input switches SW 1 thru SW 10. It will remain constant until set to
another address. Reading out the contents is simply a matter of incrementing this 10-bit
address through the range of program addresses.

A slightly more complex manual programmer is demonstrated in figure 7.2. Three
presettable counters are inserted between the address input switches and the EPROM.
Instead of changing the switch positions for each address, they are now used only to
preset the counters to some beginning address. If we want to program an EPROM start¬
ing at hexadecimal 3AA, the switches would be set to that address and the "address
preset" switch pressed. The 10 LEDs, LED A0 thru LED A9, would read 3AA as the ad¬
dress. The data to be programmed is set on SW 12 thru SW 19. Pressing the "write
data" push button PBl (the renamed "address increment") stores the data from the
switches. Successive memory locations are programmed by setting SW 12 thru SW 19
and pressing PBl. Resetting the address counter to zero is accomplished by pressing the
clear button.

It is easy to see how this manual programmer, while not greatly improving program¬
ming time, facilitates reading memory. Put all the data input switches to the logic 1
level, set the interface to the read mode, and preset and load a start address. Readout is
accomplished simply by repeated operation of the address increment button.

An Automatic Programmer

You will need an operational ZAP computer to build an automatic programmer. The

174 PROGRAMMING AN EPROM

Copyrighted material

PROGRAMMING AN EPROM 175

Copyrighted material

Figure 7.1 A schematic diagram of a manual 2708 programmer.

♦5V

0.01/iF

470 a

LED A3 - LED A9
***»

A0-A9
TYPICAL
FOR 10

• +5V

0.01/tF

♦5V

•write'

SPOT

"REAO*

TO IC5
PIN 3

IC1

* D

2708

1/4

PROG

DO -07
> CONNECTED AS SHOWN
IN FIGURE 7.1

0.01/iF

-5V

33 K

IC1 2708
IC2 7406
IC3 7406
IC4 7400
IC5 74121
IC6 74193
IC7 74193
IC8 74193

2N2222A

♦27V

(319V

BATTERIES

FROM IC3
PIN 10

Figure 7.2 A schematic diagram of a self-incrementing manual 2708 programmer. Light-emitting
diodes (LEDs) are to be connected to all 10 address-input lines of the 2708. For clarity, only one LED
(connected to address line A9) is shown in the diagram. The other LEDs are to be wired in the same
way.

176 PROGRAMMING AN EPROM

Copyrighted material

complexity of design can be reduced considerably by taking advantage of decoded, but
to this point unused, I/O strobes provided in the basic ZAP. The circuit shown in
figure 7.3 takes three less chips than the manual programmer in figure 7.2. Its opera¬
tions, while similar in operation, are quite different in detail.

Four I/O strobes (input and output port 1, and input and output port 4) synchronize
the hardware and software. Figure 7.4 shows the logic flow for writing an EPROM.
With the EPROM connected directly to the data bus, only the strobes, rather than full-
latched registers, are necessary for this interface.

To write data, the sequence should be as follows: first, an OUT 04 pulses the address
counter clear lines, setting them to 0. Next, the EPROM is set to the program mode,
and the first byte is written into the EPROM with an OUT 01 instruction.

Figure 7.5 shows how the 2708 program mode is selected. The significance of this cir¬
cuit is that its output is wired as a 2-bit digital-to-analog converter to control the chip-
select line of the 2708. _

When an OUT 04 is executed, the CS pin will see 0 volts enabling the read mode.
When an OUT 01 Js executed, this voltage will be 12 V for program mode. When no
strobe is present, CS will be at +5 V and the 2708 will be three-state.

An OUT 01 fires the 25 V program pulse for 1 ms while the pertinent data is on the
data bus. After that, an INP 01 is executed, which increments the address counter to
the next address position. We are not actually doing any input function, but instead we
are using the decoded strobe of the INP 01 instruction to mean "increment address reg¬
ister."

The hardware automatically keeps track of the address, but the software must imple¬
ment its own counters to keep track of the 0 to 1023 positions as well as the number of
times the complete 1024 bytes have been programmed. Remember, the manufacturer
suggests 100 1-ms loops.

Reading the EPROM automatically is also very simple. A flow diagram of the logic is
shown in figure 7.6. The address counter is cleared again by doing an OUT 04. Data is
read by executing an INP 04. This data can be stored and analyzed. Finally, the address
counter is incremented again with an INP 01, and the process is repeated to read the
next byte.

While discussion has centered on the Intel 2708 EPROM as the most cost-effective
choice, there are many other EPROMs on the market. Two devices of particular impor¬
tance (should their price and availability improve by the time you read this) are the
Intel 2758 and 2716. These are 1 K and 2 K single supply (+5 V) EPROMs, respective¬
ly. The significance for the experimenter is that these parts can be programmed with a
single, 50 ms, 25 V program pulse to each address rather than successive 1-ms loops.
The three programmer circuits presented are set up for 2708s but can be easily recon¬
figured for these other devices. Changing the one-shot timing pulse from 1 ms to 50 ms
and rewiring a few pins will allow complete programming with just a single run
through the addresses (they don't have to be successively programmed, either).

Erasing An EPROM

EPROMs bought directly from a manufacturer come completely erased. If you plan
on writing an EPROM program once, and you either don't want to modify it or you
don't make mistakes, forget about erasing. The majority of computerists will want to
reprogram EPROMs. It then becomes necessary to know how to erase them. We all
know that EPROMs are ultraviolet erasable. However, duration, distance from the
light source, and intensity determine the quality of the erasure.

People concerned about maintaining a manufacturer's specifications during the pro¬
gramming sequence should also be advised of the proper erasing methods. Unlike the
test read-after-write-loop method for programming, EPROMs are usually removed
from the circuit during erasing. Therefore, it is advisable to perform the procedure cor¬
rectly, or it will have to be repeated.

The typical 2708 EPROM can be erased by exposure to high intensity shortwave
ultraviolet light, with a wave length of 2537 A. The recommended integrated dose (UV
intensity X exposure time) is 12.5 watt-seconds per square centimeter (Ws/cm J ). The
time required to produce this exposure is a function of the ultraviolet light intensity.

PROGRAMMING AN EPROM 177

Copyrighted material

Cost and safety, equally emphasized, should be the guiding factors when selecting an
ultraviolet eraser. A commercial unit not only specifies its intensity (that allows com¬
putation of exposure time), but also includes important interlocks. It is conceivable
that some homebrew erasers might have improper shielding that could allow the ultra¬
violet light to escape or be accidentally turned on while being viewed. Such possibilities
can lead to permanent eye damage.

One of the more cost-effective erasers on the market is the UVS-llE by Ultra-Violet
Products, Inc, San Gabriel CA, 91776. This unit is made especially for the home com¬
puter market and includes some important safety features. The lamp will not operate
unless properly seated, and if lifted from its holding tray, it will automatically shut off.
At the standard exposure distance of 1 inch, the UVS-llE produces an intensity of
5,000 /iW per square centimeter (/xW/cm 2 ). Exposure time for the 2708 is easily calcu¬
lated.

Exposure time (T £ )

T*-J+I

Where

J = required erasure density of device
I = incident power density of eraser

For a 2708 which requires 12.5 Ws/cm 2

I - 5000 /xW/cm 2
I - 12.5 Ws/cm 2

or T c

12JL

5000X10
41.6 minutes

=* 2500 seconds
for complete erasure

178 PROGRAMMING AN EPROM

Copyrighted material

♦sv

OECOOED

1° \

I/O STROBES )

\ ,C2 }

►2.2K

FROM COMPUTER L

\ 7406 :

INP 04 v

1 -

♦5V

0.01/iF

• Cl

• C2

• C3

• C4

• C5
IC6
IC?

2708

7406

74153

74193

74123

7400

IC2

7406

our 04

‘CtEAR AOORESS V
COUNTER* 0S4 WR

"LT

IC4

74193

1NP 01

’INCREMENT N -

ADDRESS COUNTER’ DS1 RD

“LT

IC3

74193

WAIT

280 ✓_

Pin 24 >> ~LP

0 O.M» T 0 47K

♦5V

0.01 M F * ] r T

IC2

7406

• Cl

2708

PROG

*07^
■> D6
» 05
> 04
■> 03
* 02
01

> DO

TO COMPUTER
OATA BUS

OUT 01

’WRITE BYTE >
INTO EPROM* 0S1

'* ,c«*

74123

10>»S

2C R/C

• C6B

74123

2A 1 m*

Figure 7.3 A schematic diagram of an automatic 2708 programmer.

PROGRAMMING AN EPROM 179

Copyrighted material

Figure 7.4 A flowchart of an automatic EPROM programmer write cycle.

Figure 7.5 Programmable control of an EPROM CS line in an automatic EPROM programmer.

180 PROGRAMMING AN EPROM

Copyrighted material

Figure 7.6 A flowchart of an automatic EPROM programmer read cycle.

PROGRAMMING AN EPROM 181

Copyrighted material

CHAPTER 8
CONNECTING ZAP TO
THE REAL WORLD

It's now obvious that the ZAP computer can be configured in a number of ways.

Depending on your needs, you can go far beyond the basic system I have outlined. If
you want a personal computer that is the equivalent of large commercial microcomput¬
er systems, then you must add considerably more memory and peripherals. Accom¬
modations must be made for a more powerful operating system and most probably a
high-level language such as BASIC or Pascal. If you intend to use the ZAP computer as
a word processing system, then a video display and printer will be required. This, in
turn, necessitates adding more parallel and serial ports. Whatever the eventual config¬
uration, the design considerations that went into constructing the ZAP computer do
not change.

The ZAP computer is intended as a trainer. This book is structured in such a way
that you should be able to lay out a system configuration and build it. I have not
discussed what it takes to design a word processing system, or to add floppy disk stor¬
age, because it is beyond the scope of this introductory text. The support material
necessary to adequately cover such an undertaking would be enough for another book.

This does not mean, however, that everything is finished once the ZAP computer is
constructed and you learn how to write and execute a short program. Quite the con¬
trary; a more significant application of ZAP is to connect it to something considered
part of the "real world" and have it perform some constructive task. ZAP's "power to
weight" ratio makes it a natural for intelligent control applications. The real key to us¬
ing ZAP effectively is learning how to connect it to the real world.

Within the framework of the direct examples I have outlined, the ZAP computer
created from this book should be a single-board computer suitable for use in a variety
of applications. Because it includes a serial port, two parallel ports, PROM monitor,
and programmable memory, ZAP is in many respects equivalent to commercial digital
controllers costing hundreds of dollars more.

Small single-board computers are most often used in data acquisition and intelligent
control applications. Their function is usually to digest certain input parameters and
compute a result. For example, in a 100 HP electric motor control, the inputs would be
voltage, current and RPM, and the control output would be a load factor correction
voltage.

In all probability, a few of these "intelligent controllers" were used by the press that
printed this book. A likely place is the electronic control unit that monitors print densi¬
ty and automatically adjusts ink flow. The computer "reads" the print and decides
whether to increase or decrease the ink flow to the paper. This decision must take into
account various input parameters such as humidity, temperature, paper velocity, and
specific gravity of the ink. The control algorithm written in machine code and stored in
ROM shifts through all the input data and generates its conclusion in the form of a pro¬
portional output to an ink-flow valve.

In most cases, computerized functions do not stop with simple control. In any pro¬
cess where repeatability and quality control are important, significant process param¬
eters are constantly monitored for deviation from preset limits and an alarm is set if the
limits are exceeded. To aid in long-term analysis, the data acquisition function often in¬
cludes recording raw-process data from the input sensors at specific intervals and gen-

CONNECTING ZAP TO THE REAL WORLD 183

Copyrighted material

erating a permanent log.

THE REAL WORLD

I don't want to confuse you by discussing too many commercial applications of sin¬
gle-board controllers. I doubt there are many web presses hidden in closets to which
you want to add computer control. There are, however, many equally challenging and
less esoteric applications for computer controls around the home. For example, a few
that come to mind include energy management, security, and environmental monitor¬
ing. I refer to such systems as real world systems, as opposed to the TTL digital world
of computers.

Because real world is anything outside of the computer, it is generally an analog en¬
vironment. The metamorphosis of ZAP into an intelligent controller is dependent
primarily upon effective analog interfacing. For this reason, the rest of this chapter is
dedicated to the design and construction of an economical analog I/O interface.

But first let's review the basics of D/A (digital-to-analog) conversion and then
discuss a method to use a D/A to perform A/D (analog-to-digital) conversion. In data
acquisition systems, there is often a need to acquire high resolution multiple channels,
and AC as well as DC inputs. This being the case, I will also discuss a circuit which, in
effect, allows ZAP to function as an 8-channel digital voltmeter. Finally, because the
temporal relationship of so many events is significant, ZAP will be configured with a
real-time clock that defines the time at which control operations occur.

DIGITAL-TO-ANALOG CONVERTERS

The D/A (digital-to-analog) converter can be thought of as a digitally controlled
programmable potentiometer that produces an analog output. This output value (V OUT )
is the product of a digital signal (D) and an analog reference (Vm) and is expressed by
the following equation:

Vowr “ D Vref

To a large extent, no D/A or A/D converter is very useful without specifying the
type of code used to represent digital magnitude. Converters work with either unipolar
or bipolar digital codes. Unipolar includes straight binary and binary coded decimal
(BCD). Offset binary, one's or two's complement and Gray code, is usually reserved
for bipolar operation. However, we will limit our discussion to straight and offset
binary.

It is important to remember that the binary quantity presented by the computer is a
representation of a fractional value to be multiplied by a reference voltage. In binary
fractions, the MSB (most significant bit) has a value of 1/2 or 2*\ the next MSB is 1/4
or 2' 1 , and LSB (least significant bit) is 1/2* or 2"" (where n is the number of binary
places to the right of the binary point). Adding up all the bits produces a value that ap¬
proaches 1. (The more bits, the closer that value is to 1.) The algebraic difference be¬
tween the binary value that approaches 1, and 1, is the quantization error of the digital
system (to be discussed later).

Offset binary is similar to straight binary except that the binary number 0 is set to
represent the maximum negative analog quantity; the MSB is a 0 for negative analog
values, and a 1 for positive analog values.

The conversion of digital values to proportional analog values is accomplished by
either of two basic conversion techniques: the weighted-resistor D/A converter and the
R-2R D/A converter. The weighted-resistor D/A converter is by far the simplest and
most straightforward. This parallel decoder requires only one resistor per bit and
works as follows: switches are driven directly from the signals that represent the digital
number D; currents with magnitudes of 1/2, 1/4, 1/8, . . . 1/(2") are generated by
resistors with magnitudes of R, 2R, 4R, . . . 2"R, that are connected by means of
switches between a reference voltage, —V* rf , and the summing point of an operational
amplifier. The various currents are summed and converted to a voltage by an opera¬
tional amplifier (see figure 8.1).

While this may appear to be a simple answer to an otherwise complex problem, this
method has some potentially hazardous ramifications. The accuracy of this converter

184 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

is a function of the combined accuracies of the resistors, switches (all switches have
some resistance), and the output amplifier. In conversion systems of greater than
10-bits resolution, the magnitudes of the resistors become exceptionally large and the
resultant current flow is reduced to such a low value as to be lost in circuit thermal
noise.

A reasonable alternative to the weighted-resistor D/A converter is the R-2R con¬
verter. This is often referred to as a resistor-ladder D/A converter and is the most wide¬
ly used type even though it uses more components. This circuit (see figure 8.2) also
contains a reference voltage, a set of binary switches, and an output amplifier. The
basis of this converter is a ladder network constructed with two resistor values, R and
2R.

One resistor (2R) is in series with the bit switch, while the other (R) is in the summing
line, so that the combination forms a "pi" network. This suggests that the impedances
of the three branches of any node are equal, and that a current I, flowing into a node
through one branch flows out as 1/2 through the other two branches. In other words, a
current produced by closing a bit switch is cut by half as it passes through each node on
the way to the end of the ladder. Simply stated, the position of a switch, with respect to
the point where the current is measured, determines the binary significance of the par¬
ticular switch closure.

Figure 8.1 A 4-bit weighted-resistor digital-to-analog converter. A 4-bit word is used to control four
single-pole single-throw switches. Each of these switches is in series with a resistor. The resistor
values are related as povjers of 2, as shown. The other sides of the switches are connected together at
the summing point of an operational amplifier. Currents with magnitudes inversely proportional to the
resistors are generated when the switches are closed. They are summed by the op amp and converted
to a corresponding voltage.

v Rtr

V OUT

Figure 8.2 A 4-bit R-2R resistor-ladder digital-to-analog converter. This type of D/A converter makes
use of a resistor-ladder network constructed with resistors of value R and 2R. The topology of this net *
work is such that the current flowing into any branch of a 3-branch node will divide itself equally
through the two remaining branches. Because of this, the current will divide itself in half as it passes
through each node on its way to the end of the ladder. The four switches are again related as powers of
2. The position of each switch with respect to its distance from the end of the ladder determines its
binary significance.

CONNECTING ZAP TO THE REAL WORLD 185

Copyrighted material

This type of converter is easy to manufacture because only two resistor values are
needed; in fact, one value, R, will suffice if three components are used for each bit.
Keeping matched resistor values with the same temperature coefficients contributes to
a very stable design. Certain trade-offs are required between ladder resistance values
and current flow to balance accuracy and noise.

One form of the R-2R ladder circuit is the multiplying D/A converter and is avail¬
able with either a fixed or an externally variable reference. Multiplying D/A converters
that utilize external variable analog references produces outputs that are directly pro¬
portional to the product of the digital input multiplied by this variable reference. These
devices have either current or voltage output. The current output devices are much
faster because they do not have output amplifiers that limit the bandwidth; therefore,
they tend to cost less than voltage types.

An economical 8-bit multiplying D/A is the Motorola MC1408-8 (see figure 8.3). As
previously mentioned, this monolithic converter contains an R-2R ladder network and
current switching logic. Each binary bit controls a switch that regulates the current
flowing through the ladder. If an 8-bit digital input of 11000000 (192 decimal) is applied
to the control lines of the illustrated converter, the output current would be equal to
(192/256)(2 mA) or 1.50 mA. Note that when binary 11111111 (255 decimal) is ap¬
plied, there is always a remainder current that is equal to the LSB. This current is
shunted to ground, and the maximum output current is 255/256 of the reference
amplifier current, or 1.992 mA for a 2.0 mA reference current. The relative accuracy
for the MC1408-8 version is ±1/2 the LSB, or 0.19% of full scale (see figure 8.4). This
is more than adequate for most home computer analog control applications.

The final circuit (figure 8.5) is an 8-bit MC1408-8 multiplying D/A converter. As
previously outlined, "multiplying" means that it uses an external variable reference
voltage. In this case, a 6.8 V zener-diode regulated voltage is passed through a resistor
that sets the current flowing into pin 14 to approximately 2 mA.

VCC(+5V)

I OUT • A [ Dl/2 ♦ 02/4 *03/8+ 04/16 *03/32+06/64 + 07/128 ♦08/256]

WHERE A S V REF/R14
AND ON * 1 FOR HIGH LOGIC LEVEL
0N«0 FOR LOW LOGIC LEVEL

Figure 8.3 A typical 8-bit current-output monolithic multiplying D/A converter. This Motorola in¬
tegrated circuit contains an R-2R network like the one in figure 82. plus additional current-switching
logic.

186 CONNECTING ZAP TO THE REAL WORLD

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ANALOG ♦
OUTPUT 1

l/~

OESIREO ANALOG
OUTPUT VALUE

1/2 LSB{ ^

/ } 1/2 LSB

7 0 i C ital OUTPUT VALUE
/ *— APPROXIMATING ANALOG
^— VALUE WITHIN ±1/2 LSB

DECREASING BINARY
VALUE

INCREASING BINARY VALUE

Figure 8.4 Output characteristics of a digital-to-analog converter showing least significant quantiza¬
tion.

ICl VC14O0-8
IC2 LV301A

♦ 5 GND *12 -12

13 7 3

7 4

130ft

PARALLEL

OUTPUT

PORT

Figure 8.5 A final 8-bit MCI408-8 multiplying digital-to-analog converter with span and offset adjust¬
ments.

CONNECTING ZAP TO THE REAL WORLD 187

Copyrighted material

An additional resistor, Rl (also in this current leg), allows the current to be varied by
a small percentage and provides the ability to adjust the full-scale range of the D/A
converter. The output is a current that is equivalent to the product of this reference cur¬
rent and the binary data on the control lines. The current is converted to a voltage
through IC 9 and can be zero offset through the use of the offset adjustment pot, R2.

Using this circuit with the ZAP computer is simply a matter of connecting the input
lines of IC 1 to a convenient parallel output port on ZAP. Any 8-bit value sent to that
port will be converted to a voltage proportioned to that output.

The digital code presented to the D/A converter must be in offset binary. A binary
value of 00 hexadecimal produces an output of —5 V while FF hexadecimal is
equivalent to +5 V. In offset binary, if the MSB is a 0, the output is negative, and if the
MSB is a 1, the output is positive. Because the converter has a range of 10 V, and is an
8-bit device, the resolution of the converter is 1/256 of 10 V, or approximately 40 mV.
This means that the smallest output increments will be in 40 mV steps. To change this
to finer increments requires a shorter range, such as +2.56 V to —2.56 V. By adjusting
the span and zero pots, any reasonable range may be chosen, but the resolution will
always be equal to the LSB or 1/256 of the range, and accuracy is estimated to be
±1/2 the LSB.

Calibration is fairly straightforward. Apply the power, and with a short program
that outputs a value from the accumulator, send a binary 10000000 to the port address
corresponding to the D/A interface board. Using a meter to monitor the output of the
LM301A, adjust the zero pot R2 until the output is 0 V. With the same program, load
in binary 11111111 to the port address and adjust the span pot Rl for a meter reading
of +5.12 V. A binary setting of 00000000 should produce —5.12 V. If you are unsuc¬
cessful at this point, turn the power off and remove the MCI408-8 and the LM301A;
then reapply power and verify that the binary output is correct on the parallel output
port. Nine times out of ten, problems like this can be attributed to choosing an incor¬
rect output code.

If the test is successful, you are now ready to generate analog outputs under program
control. A simple test is to designate a section of memory and sequentially output the
values to the D/A. If the table is 256 bytes long with the values ranging from 0 to FF
hexadecimal in 01 increments, the result will be a sawtooth-waveform output. If the
samples are sent to the output rapidly enough, and it is connected to a speaker, the
waveform will be audible. The exact frequency will be a function of the update timing
loop.

The following is a short program that exercises the D/A in such a manner:

START

EQU

0400

Memory table start HL address

END

EQU

Memory table end H address

OPORT

EQU

D/A output port number

SAMP

EQU

Sample rate time constant

HL, START

Load table start address

AGAIN

A, (HL)

Table value to accumulator

OUT

OPORT, A

Output byte to D/A

CALL

DELY

Sample time delay

INC

A,H

END

Test to see if at end of table

HALT

NZ, AGAIN

If not, output the next sample

DELY

B, SAMP

Sample rate timing loop

DCR

DEC

NZ, DCR

RET

The table can be set to any length. Values in the table can be calculated to produce
any shape waveform.

188 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

ANALOG-TO-DIGITAL CONVERTERS

It's always a good idea to discuss D/A converters first. They are rather straightfor¬
ward and there are not an overwhelming number of conversion methods. By introduc¬
ing them first, you will become aware of the process of binary conversion and ap¬
preciate the concepts of resolution and accuracy. Practically speaking, however, if you
were going to set up the ZAP computer to serve in a data acquisition mode—say,
reading and recording temperatures—you would need an A/D (analog-to-digital) con¬
verter before a D/A (digital-to-analog).

An A/D does what its name implies. It converts analog voltages into a digital repre¬
sentation compatible with the computer input. As in the case of an 8-bit D/A, an A/D
is subject to the same conversion rules. If you are trying to read a 10 V signal with an
8-bit converter, the resolution will be 1/256 of 10 V (or 40 mV) and the accuracy will
be ±1/2 the LSB.

For greater resolution more bits are necessary. The number of bits does not set the
range of a converter; it only determines how finely the value is represented. An 8-bit
converter (either A/D or D/A) can be set up just as easily to cover a range of 0 to 1 V
or 0 to 1000 V. Often the same circuitry is used, but a final amplification stage or
resistor-divider network is changed. Understand, of course, that with a range of
1000 V and an 8-bit converter, the resolution is 4 V. Such a unit would be useless on 0
to 10 V signals. The problem can be reconciled in a number of ways, but the easiest
solution is to use a converter with more bits. A 16-bit converter that has 65,536 (2 16 )
steps instead of 256 (2 s ) would cover the same 1000 V range in 15 mV increments.

For the ZAP computer, the question becomes more one of reasonable price perfor¬
mance than nth degree accuracy.

Analog-to-digital conversion is considerably more expensive than D/A—the price is
directly related to resolution and accuracy. There are many ways that A/D conversion
can be accomplished. The range varies from very slow, inexpensive techniques to ultra-
fast, expensive ones. An A/D converter can cost as little as $5 or as much as $10,000.

An A/D converter that scans thermistor probes and provides data to control the tem¬
perature in a large supermarket may cost $4.75, but it cannot encode video information
from an optical scanner.

The objective of this book, of course, is to help you to build your own computer; lit¬
tle is served by presenting designs that are beyond a reasonable budget and average
construction abilities. For those reasons, I have sifted through a multitude of tech¬
niques to select four designs that can easily be built and attached through the ZAP
computer's parallel interface. One of them should meet your basic data acquisition re¬
quirements.

1. Basic analog to pulse width converter

2. Low cost and low speed 8-bit binary-ramp counter converter

3. High speed 8-bit successive approximation converter

4. Eight-channel 3Vi-digit 0 — 200 V AC/DC interface

PULSE WIDTH AND BINARY COUNTER CONVERTERS
Analog to Pulse Width Converter

This converter is one of the most popular open-loop encoders because of its simplici¬
ty. A basic block diagram is shown in figure 8.6. This device uses a fixed oscillator in
combination with a circuit that generates a pulse width that is a linear function of the
analog input voltage.

To obtain this variable linear pulse width, designers frequently use a ramp generator
and a Schmitt-trigger circuit. A gating pulse is started at the beginning of the ramp and
a counting circuit starts incrementing at a fixed frequency. When the linear ramp
reaches the same value as the input voltage, the counting is terminated. The value left
in the register at that point is representative of the analog input.

Figure 8.7 is a schematic of a unipolar analog to pulse width converter that operates
on this principle. 1C 1 is configured as a gate controlled linear ramp generator and IC 2
is the input comparator. The process starts when the 7.5 KHz clock signal fires IC 3 (a
74121 one-shot), and starts its 35 ms period, which is the gate time. At the beginning of
this gate period, a pulse that clears the two 7493s and the ramp generator is generated.

CONNECTING ZAP TO THE REAL WORLD 189

Copyrighted material

digital

OUTPUT

2N4392

RAMP

RATE

ADJUST

♦ 5V

01 (*r

-Jh-

2N2907

2 2* ' H V*

1N960B

9.1V

V IN

R/C IC3

C A1

sample

GATE

0 74121

33mi

7408

LM301A

LINEAR

RAMP

GENERATOR

^LM301A A

COMPARATOR I

■» 5

CLOCK

RST

IC5

DiS

OUT NE5S9

7.5 kHz

THR

TRG

i_ CT sy_i

>10K fRE °

T4C8

1N914

AO J

0.1 M P

INA ISO A

[£-4

L 2

A OA

a-[

p.. n

o IC10 00

52 r

"01 0

o.. r

7495

r r\r

n r

K 02 c

IC8 o

n t

w U V

ft Aft

20 f

7495 °

0 CK2 00

CLEAR

14 i

IC7 7400

STORE

INA INS

*01

*02

IC9

7493

[ 2

i i

IC11

7495

CK2

■O 08

■O 87

TO COMPUTER
PARALLEL
INPUT
PORT

IC#

TYPE

♦ 5V

GN0

♦12V

-12V

LM301A

NOTES: l.SETRAMPTOGOrROM 0 V TO PULL SCALE

LM301A

DURING SAMPLE GATE TIME.

74121

7408

2.SET FREQ TO PROC'JCE WHATEVER COUNT

NE555

IS DESiREO TO REPRESENT INPUT VOLTAGE

7406

i.* 256 COUNTS DURING SAMPLE PERIOD

74 00

FOR 2.56 VOLTS.

7493

7495

Figure 8.7 A schematic diagram of a unipolar analog to pulse width converter.

190 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

This, in turn, enables the clock signal to the counter. The slew rate of the ramp genera¬
tor is set to be approximately 10 V per 35 ms. IC 2 continuously compares the input
and ramp voltages. When they are equal, the clock signal to the counter is stopped and
the ramp generator is reset. At the conclusion of the 35 ms gate time, whatever value is
in the counter is transferred to an 8-bit storage register. The value stored in this register
is an 8-bit number proportional to the input voltage. The entire process starts again on
the next clock pulse.

By properly selecting the gate times and the clock rate, you can change the span and
resolution of the circuit. With a gate time of 35 ms and a clock rate of approximately
7500 Hz, 256 clock pulses should be counted during the gate time. The ramp timing ad¬
justment pot should be set so that the counter reaches maximum count when 2.56 V is
applied to the input of IC 2. A 10:1 divider attached to this input will allow the same
8-bit count to represent 25.6 V.

This circuit is simple, but its accuracy depends on the stability of the individual sec¬
tions of the circuit. To use it, connect the register output to a parallel input port. Sim¬
ply read the port when you want the latest value. The circuit automatically updates 28
times a second, hence no reading is older than 35 ms.

Binary-Ramp Counter Converter

The above A/D technique is most often used in slow sampling rate, high-accuracy
measurements. Achieving these results, however, hinges on the use of precision com¬
ponents and proper construction. The next most productive approach to consider is the
binary-ramp counter method. In my opinion, this is the best type if you plan to con¬
struct an A/D for ZAP. It uses fewer components and, in practice, is much faster and
easier to build than linear-ramp circuits.

Figure 8.8 illustrates the basic block diagram for the binary-ramp counter converter.
The linear-ramp generator of the previous technique has been replaced by a D/A con¬
verter. In this case, the D/A is used to reconvert the digital output of the binary
counter back to analog for comparison against the analog input. If they are equal, then
whatever code is presently set on the D/A input is also our A/D output.

n-bit

> PARALLEL
OUTPUT

RESET

Figure 8.8 A block diagram of a basic binary-ramp counter A/D converter.

CONNECTING ZAP TO THE REAL WORLD 191

Copyrighted material

The simplest way to operate the system is to start the counter initially at 0 and to
allow it to count until the D/A equals or exceeds the analog input. The only critical
consideration in designing this circuit is that the clock rate cannot be faster than the
response of the comparator and D/A. If it takes 100 ns for these components to do
their job, then the maximum clock rate should be 10 KHz. For an 8-bit converter
(counting from 0 to 256 each sample period), the maximum sample rate is 10,000/256 or
some 39 samples a second. In practice, however, 5 /is is a more reasonable settling time,
resulting in about 750 samples per second. For still higher speeds, we use a different
kind of A/D (more on this later).

Figure 8.9 shows a schematic of a binary-ramp counter converter that uses a
MC1408-8 multiplying D/A converter chip. The counter output is connected to the
MC1408-8 to provide a direct analog feedback comparison of the value set on the
counter. Initially, ICs 4 and 5 are cleared, and the D/A output should equal the
minimum input voltage. For a 0 to 5.12 V converter, this would be 0 V. For a —2.56 to
+2.56 V unit, it would be —2.56 V. If the output of IC 1 is less than V w , the clock
pulses are allowed to reach the counter. As each pulse increments the counter, the out¬
put of the D/A keeps rising until eventually it equals or just exceeds V lN on the com¬
parator. When this happens, additional clock pulses are inhibited. At the end of the
sample period, the count value of ICs 4 and 5 is stored in a separate register. For ZAP
to read this data, it just requires connecting this register to an input port and reading it
directly.

V IN

CLOCK

»C9

7495

TO COMPUTER
PARALLEL
INPUT

IC 10

7495

VJ v.

1N4736B
6 8V

1*F

IC#

TYPE

♦ 5V

GND

♦ 12 V

-12 V

LM301A

MC1408-8

7493

7486

7400

NE555

7495

74 9 5

Figure 8.9 4 schematic diagram of an Qbit binary-ramp counter A/D converter.

192 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

Using the Computer to Replace the Counter

Figure 8.9 is a stand-alone circuit. It does not require the computer for operation.
The A/D updates itself at a preselected sample rate and loads this value into an 8-bit
latch. As far as the computer is concerned, there is a steady state reading from the con¬
verter. Every function required to perform the A/D conversion is constructed from
hardware components.

There are certain advantages to this approach. The A/D can be independently as¬
sembled and tested without a computer. For example, a voltage can be applied to the
input and the 8-bit value can be displayed on 8 LEDs. The ability to test each subsystem
independently is the way I've tried to present all the hardware in this book. If, on the
other hand, you feel you've mastered the art of programming and would rather not
build elaborate interfaces, much of the hardware of figure 8.9 can be replaced with
software subroutines.

Consider for a moment the major elements of this design. This 8-bit A/D has four
sections: D/A, analog comparator, 8-bit counter, and timing logic. The resistor ladder
and analog comparator are necessary components, but the last two sections are prime
candidates for synthesis through the computer. The combined function of these devices
is to increment an 8-bit count and check the output of the comparator.

The ZAP computer has parallel input and output ports. By incrementing a central
processor register and outputting the value after each increment, the 8 lines from the
port will have all the appearances of a standard 8-bit counter made with 7493s and so
on. By using one bit of an input port to read the status of the comparator, we can also
replace the rest of the timing logic.

The resulting interface has fewer components and is shown in figure 8.10. The D/A
remains essentially the same except that rather than being driven from two 4-bit
counters, it is connected to an 8-bit parallel output port. The analog output of the D/A
will be whatever value is sent to the output port. Instead of hardwired logic to detect
when the D/A and input voltage are equal, we attach the comparator output to bit 0 of
an available input port.

BITO

parallel

INPUT

PORT

Figure 8.10 A software-driven 8-bit analog-to-digital converter.

CONNECTING ZAP TO THE REAL WORLD 193

Copyrighted material

The conversion process is not unlike the hardware version. First, we clear a register
(B, for example) and then output the register value to the port attached to the D/A.
This will set the D/A to its minimum output. Next, we read the input port that has the
comparator attached to it and check bit 0 (a logic 1 indicates that the input and D/A
voltages are equal). If the comparator is low (the voltages are not equal), the register is

then incremented and the process is repeated. Eventually, the register will be in¬
cremented to the point where the D/A output and the unknown input voltage are
equal. The comparator will then switch. At this point the program is halted and the
value of the B register is the digital equivalent of the input voltage. The program to ac¬
complish this follows:

AGAIN

MVI

Clear B register

OUT

0,B

Output B register

INC

Increment B register

OUT

0,B

Output B register

Read comparator port

ANA

Isolate bit 0

JNZ

AGAIN

Continue if voltages not equal

HLT

A/D value is in B register

The above program should be repeated each time a new reading is needed and the
sample rate can be adjusted within broad limits. Remember, however, that we still
have to wait for the D/A circuitry to settle and it should not be incremented any faster
than 5 /xs. Using the 2.5 MHz Z80 should not present a problem. Using a 4 MHz
crystal the central processor might necessitate a few NOPs in the loop.

There are many variations on this circuit. As described, it takes up to 255 iterations
of the program to find an answer. On a computer with a 2 /xs average instruction time,
the program could take 3 /xs to finish, limiting us to about 300 samples a second. Add
the other tasks that the computer must perform and you might be limited to 100
samples a second. Executing counting routines takes time; it will not, however, be a
problem if you are merely monitoring a temperature probe that has a 30-second time
constant.

If you should want to track and record fast changing signals, such as an acoustic
waveform, then a much faster conversion algorithm is required. One method that
speeds up the process is called successive approximation (more later).

The capabilities of this circuit can be expanded in other ways. An additional CMOS
multiplexor can be connected to 3 bits of another output port to turn this simple circuit
into an 8-channel A/D. Also, because this circuit includes a D/A, its output is avail¬
able as well.

Successive Approximation Converters

More than likely one of the three converters presented thus far will suffice for non-
critical data acquisition. Slowly changing signals can be handled accurately and effi¬
ciently. However, there are occasions when the signal in question is not slow or it car¬
ries a particular transient that must be captured. For example, detecting a 100 /xs event
requires a converter with a capability of 20,000 samples per second. In such cases we
need a much faster conversion method.

Figure 8.11 is the schematic of a general purpose high-speed, 8-bit converter. It is
capable of sample rates in excess of 200,000 samples per second. To attain these speeds,
a technique called successive approximation is used. Like the binary-ramp counter con¬
verter, this A/D also incorporates a D/A in a feedback loop but replaces the counters
with a special SAR (Successive Approximation Register). The circular logic of suc¬
cessive approximation is best explained in the block diagram of figure 8.12.

Initially the output of the SAR and mutually connected D/A are at a zero level. After
a start conversion pulse, the SAR enables the bits of the D/A one at a time starting with
the MSB. As each bit is enabled, the comparator gives an output signifying that the in¬
put signal is greater or less in amplitude than the output of the D/A. If the D/A output
is greater than the input signal, a "0" is set on that particular bit. If it is less than the in¬
put signal, it will set that bit to "1". The register successively moves to the next least

194 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

07
06
OS
04
03
02
01
00 J

PARALLEL

OUTPUT

END OP
CONVERSION

1C*

TYPE

♦5V

GND

♦12V

-12V

-6V

MC1408-8

MC145S9

74100

LM301A

LM710

7400

7404

MC1408-8

LM301A

NOTES: 1.ALL RESISTORS ARE 1/4W 5% UNLESS
OTHERWISE indicated.

2 ALL CAPACITORS ARE 100 V CERAMIC
UNLESS OTHERWISE INDICATED.

3. WITH COMPONENTS SHOWN, CLOCK FREQUEN¬
CY IS 800 kHx THIS IS 100.000 CONVERSIONS
PER SECONO IN FREE RUN MODE.

4. THE FOLLOWING CIRCUIT CAN BE AODEO TO
EACH OUTPUT PIN OF IC3 IF A VISUAL INDICA¬
TOR IS DESIRED.

♦ 5V

FROM 1C 3 >

LED

♦5V SUPPLY

Figure 8.11 A schematic diagram of an 8 bit successive approximation AID converter .

CONNECTING ZAP TO THE REAL WORLD 195

Copyrighted material

ANALOG

REFERENCE

V INPUT

K 8-BIT
| PARALLEL
OUTPUT

SERIAL

OUTPUT

Figure 8.12 A block diagram of a typical 8-bit successive approximation A/D conversion system.

significant bit (retaining the setting on the previously tested bits) and performs the
same test. After all the bits of the D/A have been tried, the conversion cycle is com¬
plete. As opposed to the 256 clock pulses of the binary counter method, the entire con¬
version period takes only 8 clock cycles. Another conversion would commence on the
next clock cycle when it's in the free-run mode. To retain the 8-bit value between con¬
versions, an 8-bit storage register IC 3 has been added. To use this A/D, simply con¬
nect the output of this latch to an 8-bit input port.

The components of the D/A circuit are changed slightly from previous implementa¬
tions to increase the speed, and a faster comparator is used. With a clock rate of
800,000 Hz, the circuit will do 100,000 conversions a second. Because they are auto¬
matically loaded into the 8-bit-holding register IC 3, the update is transparent to the
computer and can be read at any speed. The sample rate is a function of the clock rate.
If it is unnecessary to have such a high sample rate, it may be reduced by increasing the
value of Cl. High speed A/D converters are susceptible to layout and component selec¬
tion. While 200,000 samples per second is attainable, 20,000 samples per second might
be more practical.

A Unique Application for a Fast A/D

When we first considered adding an A/D to ZAP, our thoughts centered on monitor¬
ing some process or turning ZAP into an intelligent controller. In most cases, this re¬
quires one of the simpler A/D converters I've outlined. However, with the addition of
a high speed A/D peripheral, a few more experiments come to mind.

Most often when we think of high speed analog, we want to capture video or other
high bandwidth phenomena that have a voltage level within the range of the A/D. Of
course, the audio frequencies, while much lower than video, may also require a high
performance A/D for proper representation.

The bandwidth of the human voice is about 4000 Hz. These analog signals, when
spoken into a microphone and fed to an A/D, can be digitized just like any other wave¬
form. And, if our voice samples are taken quickly enough and stored, the accumulated
data can be used to reconstruct the same voice. This reconstructed voice is called
digitized speech.

In essence, digitized speech is simply the result of a standard data acquisition tech¬
nique When speaking into a microphone and amplifier, your voice results in a fluctu-

196 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

ating waveform, whose frequency rate varies. If this signal is applied to the input of a
high speed A/D, and the conversions stored in memory, the computer couldn't care
whether the source was speech or a nuclear reaction. The analog fluctuations would be
digitized at discrete sampling intervals and stored. If the stored samples are output to a
D/A at the same rate they were taken, speech will be reproduced. The fidelity of this
reconversion is a function of the sampling rate.

Most of the intelligence or information content of human speech occurs in the fre¬
quency region below 1500 Hz. Obviously, sampling this waveform at 25 samples per
second would be useless. It must be sampled very rapidly to retain anything of signifi¬
cance.

There is a specific law known as the "Nyquist criterion" that is used to determine the
optimal sampling rate. In theory, this law states that at the very minimum, the sample
rate must be twice the frequency of the input waveform. Thus, if the human voice ex¬
tends to 4 Hz, then the minimum rate should be 8000 samples per second. This also
presumes an ideal filter on the output, the existence of which is about as ephemeral as
perpetual motion. In actuality, the sampling rate should be 3 or 4 times the highest in¬
put frequency. To digitize voice accurately requires a sampling rate of 12 Hz to 16 Hz.
If, on the other hand, we shoot for just the lower frequencies, we can get by with 3 Hz
or 4 Hz.

The possibility of using this speech technique has to be considered in light of the
' availability of large amounts of memory. At a 4 Hz sample rate, one second of speech
takes 4000 bytes of memory. If you have added more than the 2 K of memory in the
original configuration of ZAP, then perhaps you'll want to experiment with digitized
speech. Even with just 2 K you should hear something.

A fairly simple program is needed to coordinate the digitization process and store the
data:

START

EQU

400

END

EQU

COO

TRIG

EQU

IPORT

EQU

SAMP

EQU

INP

IPORT

TRIG

NZ, INP

HL, START

AGAIN

IPORT

(HL), A

CALL

DELY

INC

A,H

END

HALT

NZ, AGAIN

DELY

B, SAMP

DCR

DEC

RET

NZ, DCR

Memory table start HL address
Memory table end H address
Input start conversion level
A/D input port
Sample-rate time constant

Read A/D input value
Compare input to trigger level

Loop again if below trigger level
Load table start address
Take a sample
Store sample in memory
Delay between samples

Test to see if at end of table
If not, take another sample

Start delay timer

When the program is executed, it will scan the A/D input port and compare the read¬
ing to A8 hexadecimal (about 65% of full scale). When speech is present, the audio
level will presumably exceed this trigger level. W r hen this happens, the program sets the
address of the storage table and starts dumping data samples into it at a rate of about
4000 per second. The rate is determined by the value of "SAMP." The higher the num¬
ber, the lower the sampling frequency. W’hen the table is filled, the program stops and
the memory will contain a digitized representation of whatever was spoken during the
sample time. For 2 K of memory, only Yi second of speech will be captured.

To hear this stored data, use the program outlined in the section on D/A converters.

CONNECTING ZAP TO THE REAL WORLD 197

Copyrighted material

Set the limits to be the area of the memory table, then choose a time constant that
results in putting out the samples at the same rate that they were taken. (It is also possi¬
ble to create a digital reverberation system using this hardware, but for decent fidelity
12- or 14-bit converters are required.)

Because digitized speech is a specialized application, the D/A circuit is modified
slightly to include a low-pass filter. This will improve the sound quality. The modified
circuit is shown in figure 8.13.

8-3IT
PARALLEL (

INPUT

v.00

♦V REF
A

♦ SV

MSB

A ^

♦V REF

1 Al IT

VW *

-V REFI

ICO

A C.

MC1408-8 |

A*D

a a

LSB

VEE COMP

47pF

-12v

SPAN
AOJ

3.3K

10K

ZERO

AOJ

♦ 3V

3.9K

LOW PASS FILTER

io m f io m f

IC9

LM301A

-12V

10K

6 SK

-Wr

IT 71

O.i^r

10K

« I

Figure 8.13 An 8-bit D/A converter with a low-pass filter.

AMPLIFIER

INPUT

Using ZAP for High Resolution Data Acquisition

Up to this point our discussion has concerned experimenting with ZAP. Some
aspects of these designs are useful in noneducational applications, but for the most part
they are intended more as teaching aids than as replacements for expensive monitoring
equipment. However, it is possible to add more specialized interfacing to ZAP which
allows it to be used in such a manner.

The 8-bit A/D converters presented thus far have limited resolution and are single¬
channel devices. They are adequate for measuring temperature in a solar heating sys¬
tem, but it is doubtful that they have the resolution to monitor the temperature gra¬
dient along a length of heating duct. The sensors used to measure such parameters
would need to have a higher resolution than ambient air temperature sensors. For a
range of —20 to 108°C, an 8-bit A/D could provide 0.5° resolution. In a solar heating
application, considering the variations in air movement, cloud cover, and general
weather patterns, this is as much resolution as you would need. Within the system,
however, there are areas that will require closer measurement.

A solar system is a typical example. After installation the next step is usually to in¬
vestigate how to increase its efficiency. Nine times out of ten this requires cutting heat
losses in the pipes and ducts. One way to determine such loss is to place temperature
sensors along the heat distribution path and look for cold spots. The measured dif¬
ferences between sensors may be very small, a few tenths of a degree or so, but the
overall losses could be significant. Measuring temperatures to tenths or hundredths of a
degree and maintaining the same dynamic range requires more than 8-bit resolution.
Something between 10 and 12 bits is needed.

The situation is further complicated by the large number of points that may need
monitoring within a system. It's rare to find only one temperature indicator in the sys¬
tem. At the very least there would be six: inside air, outside air, storage tank top, stor¬
age tank bottom, collector, and distribution air temperature.

198 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

Very few commercial data acquisition systems use a single channel. Usually they
come with either eight or 16 multiplexed channels. The input of one A/D converter is
switched (usually on a demand basis) between the channels and the results are com¬
piled and averaged by the computer. This information can be logged on recording tape,
transmitted serially to another system, or used to run a real-time display. What one
does with the data is a function of the application program.

There are various ways to configure ZAP for high-resolution data acquisition. One
is to simply to replace the 8-bit A/D with a 12-bit binary converter. When the conver¬
sion is finished, 12 bits of parallel data are available. Depending upon the converter
chosen, many outboard analog components might still be required, but the process is
straightforward. Unfortunately, these converters are not what you would call inexpen¬
sive. Although they are becoming cheaper every day, at this writing they are still con¬
siderably more expensive than 8-bit converters of similar speed.

Most 12-bit binary converters are expensive because they are designed to give the ap¬
pearance of parallel converters. Toggle the convert enable line and zip, there's 12 bits
of answer. When the computer wants this data, it scans, manipulates, and stores it in a
table for use by other programs. Making the hardware section of an A/D interface less
expensive involves doing less in parallel. Taking the alternative serial approach gener¬
ally requires more time and additional data manipulation. We can opt for the lowest
expense and let our computer do most of the work. We have already demonstrated
how to eliminate counters and timing logic by doing these functions in software.

An 8-Channel 3Va-Digit AC/DC Interface for ZAP

The solution to the high resolution versus expense question comes in the form of a
3 Vi-digit multiplexed A/D converter chip. The MC14433 CMOS integrated circuit is
intended primarily for use in digital voltmeters (DVMs) but enjoys a variety of other
applications because of its versatility. It is a single-channel 11-bit converter, but it is
called 3Vi digits. The output is BCD (binary-coded decimal) and it specifically covers a
range of —1999 to +1999 counts. Basic chip specifications are as follows:

MC14433 3 1 /i-Digit A/D Converter

Accuracy: ±0.05% of reading ±1 count

Two voltage ranges: 1.999 V and 199.9 mV

25 conversions per second

1000 Mfl input impedance

Auto zero

Auto polarity

Over, under, and auto ranging signals available

The MC14433 is a modified dual-ramp integrating A/D converter and is outlined in
figure 8.14. The conversion sequence is divided into two integration periods: unknown
and reference. During the V M (unknown input) integration sequence, the unknown
voltage is applied to an integrator with a defined integration time constant for a prede¬
termined time limit. The voltage output of the integrator then becomes a function of
the unknown input input. The more positive the input, the higher the integrator out¬
put.

During the second cycle of the integration sequence, a reference signal of 2.000 V is
connected to V w . This causes the integrator to move toward zero while the digital cir¬
cuitry of the chip keeps track of the time it takes to reach zero. The time difference be¬
tween the two integration sequences is then a function of their voltage difference. If
2.000 V were the applied V w then t 2 would equal ti. The unknown voltage is equivalent
to the ratio of the periods times the voltage reference (V*£t). This is also known as a
ratiometric converter. The full scale of the converter is determined by V*^. Changing
to 0.200 V will make the 1999 count output represent 199.9 mV instead of
1.999 V full scale.

CONNECTING ZAP TO THE REAL WORLD 199

Copyrighted material

INTEGRATOR
OUTPUT
VOLTAGE V 0

r • INTEGRATION TIME CONSTANT

V UNKNOWN VOLTAGE INTEGRATION PERIOD (CONSTANT)
^•REFERENCE VOLTAGE INTEGRATION PER 100 <VAR I ABLE)

VJN tl V_REF I,

0 r r

T MAT IS.

V IN # t*
V REF ‘ I,

V INPUT

Figure 8.14 A simplified representation of a dual-ramp A/D converter.

The output of the DVM chip is a combination of serial and parallel data. There are
digit-select and 4 BCD data lines:

BCD Output Lines

Pin 23 Q3 (MSB)
Pin 22 Q2

Pin 21 Ql

Pin 20 QO

Digit-Select Outputs

Pin 19 DSl (MSD)

Pin 18 DS2

Pin 17 DSl

Pin 16 DSO

200 CONNECTING ZAP TO THE REAL WORLD

With respect to what the computer sees through 74LS04 output buffers, the digit
select output is low when the respective digit is selected. The most significant digit (Vi
DSl) goes low immediately after an EOC (end-of-conversion) pulse and is followed by
the remaining digits in a sequence from MSD to LSD. The multiplex clock rate is the
system clock divided by 80; two clock periods are inserted between digit outputs.

During DSl, the polarity and certain status bits are available. The polarity is on Q2
and the Vi digit value is at Q3. If Q2 is a " 1 ", then the input voltage is negative, and if
Q3 is a "0", then the Yi digit is a 0.

Figure 8.15 details the schematic of the 8-channel interface board. As shown, it has
the following capabilities:

ZAP 3 1 /2-Digit DVM Interface

• 8 programmable-input channels

• AC or DC input capability

• Programmable gain of 1, 10, or 100

• Ranges of 0 - 200 mV, 0-2 V, 0-20 V, or 0 - 200 V

• Input overvoltage protection

IC 1 is the MC14433 DVM chip. It is set for approximately 25 conversions a second

and all outputs are buffered. IC 2 is a precision voltage reference chip that supplies the
Vref signal. It is nominally 2.5 V and is trimmed to 2.000 V and 0.200 V with two po¬
tentiometers. While a zener diode might provide the same voltage, the temperature
drift associated with such components makes them inadvisable in this application.

IC 5 is configured as a set/reset flip-flop. When the conversion is finished, an EOC
signal sets IC 5, indicating to the computer that data is available. When the computer
finishes reading the data, it resets this flip-flop and awaits the next conversion.

ICs 1, 2, 3, and 4 constitute a single-channel 3V2-digit converter. It has a range of
either 0.200 V or 2.000 V determined by V Rcr . To achieve multichannel operation and
AC capability, it is necessary to place an input multiplexer and AC to DC converter in
front of IC 1.

+5 VOLTS SUPPLY

1. ALL RESISTORS ARE 5% 1/4 W UNLESS OTHERWISE NOTED

2. ALL CAPACITORS ARE 100 V CERAMIC UNLESS OTHERWISE NOTED

IC#

TYPE

♦ sv

-5V

OND

MC14433

MC1403

3.4

74LS04

7474

6.7

CD4053

C04051

7445

LM324

14 * 8

CTRL

OUTPUT

I I I

CTRL Jil I |

INPUT 0

1 SPOT I

I_1

PIN DIAGRAM OF SIGMA FUNCTIONAL DESCRIPTION OF A SINGLE U OF 3)

RELAY TYPE 291TEJA2-5S SWITCHING SECTION OF A CD<053 CMOS SWITCH

1< PIN DIP PACKAGE

Figure 8.15 An 8-channel 3 lb-digit 0—200 V AC/DC DVM interface (continued on next page).

CONNECTING ZAP TO THE REAL WORLD 201

Copyrighted material

2.500V

202 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

Figure 8.15 continued

Figure 8.16 shows the voltage reference and range selection setup of this interface.
The MC14433 can cover either 0—199.9 mV or 0—1.999 V. The ranges depend upon
the level of Vw. When B5 of port 1 is low, switches 5 and 6 are in the positions shown.
This would apply 2.000 V to W REF input and set the integration time constant with an
82 kfl resistor. With B5 = 0, V REF is 0.200 V, and the integration resistor is 10 kfl.

Figure 8.17 illustrates the input subsystem in simplified terms. SWl and SW2 repre¬
sent the gain selection section. As shown, the gain is 1 and no divider network is en-
' abled. When an input relay is closed (controlled through IC 9), the input voltage of
that channel is sent directly to the input of IC 1 through a 1Mft resistor. If the interface
is set for DC and a gain of 1, a 1.400 V input signal at channel 3 would be read directly
as 1.400 V by the DVM chip. If, however, 150 V were suddenly applied, it would be
shunted through Zl and Z2, which protect IC 1. The data read by the computer will in¬
dicate an out of range condition because the input would be shunted to 4 V.

Closing SWl or SW2 forms a divider network that allows the computer to read these
higher voltages. A 10:1 divider is formed by closing SWl. The result is a divider net¬
work consisting of the 1 Mfl resistor Rl, and a 111 kfi resistor R2 to ground. An 8 V
input signal would be read as 0.800 V at the input of IC 1. The programmer should
keep in mind that a divider was used on that channel and multiply the answer by 10
when recording it.

Closing SW 2 forms a 100:1 divider. The mathematics is the same except that the
resistor (R3) is now 11.11 kQ. An 8 V input would become 0.080 V and a 150 V input
would become 1.500 V. Obviously, proper range selection is necessary to maximize
resolution.

An additional feature of this interface is the ability to accommodate AC inputs. This
is accomplished by simply converting the AC signal to DC after the divider section out¬
put. IC 6 and IC 7 function as single-pole, double-throw switches to gate the converter
in or out of the signal path. The actual AC-to-DC converter is shown in figure 8.18.

This device is known as an average RMS (Root Mean Square) converter. If you
apply a 1.0 V peak AC signal to it, it will output 0.707 VDC. This is the technique used
in most digital multimeters. This is also the way we commonly express AC voltages.
For example, household 115 VAC is 115 V average RMS. The peak is about 176 V.
The converter passes both AC and DC because there is no blocking capacitor on the in¬
put. If it is inadvertently switched into a DC signal, it will multiply the reading by
1.414.

SW5

Figure 8.16 Voltage reference and integration time-constant modification circuitry for the digital
voltmeter.

CONNECTING ZAP TO THE REAL WORLD 203

Copyrighted material

ANALOG

INPUTS

RL1

PROTECTION MULTIPLEXER

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 3

CHANNEL 6

CHANNEL 7

CHANNEL 8

Figure 8.17 DVM input conditioning sections.

INPUT BUFFER AC-TQ-OC CONVERTER RIPPLE FILTER

♦5V

OUTPUT

Figure 8.18 A schematic diagram of an AC-to-DC converter.

204 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

Exercising the Interface with a Software Driver
The interface is attached to ZAP through I/O ports. It takes 10 input bits and 8 out¬
put bits for full operation. They are arbitrarily chosen as ports 1 and 4 for this descrip¬
tion. The actual choice will depend on what addresses you wire when you are configur¬
ing ZAP. These ports are not used for anything in the original description and will re¬
quire the proper port hardware to be added. Summarizing the I/O requirements for the

DVM (digital voltmeter) interface:

Command Output Byte (port 1 output)

EOC enable or disable

Disable=1; Enable=0

AC or DC select

AC=0; DC=1

2.0 V or 0.2 V range

2.0 V=0; 0.2 V=1

B4)

0,0=X1

gam code

0,1 “X10

1,0=X100

B2 )

• channel code

channels 0—7 binary

BO J

Status Input Byte (port 4 input)

B7'

, not used

out of range

end of conversion

Data Input Byte (port

1 input)

1st digit

2nd digit

3rd digit

digit enable

4th digit

B3 )

B2 1
Bl 1

► BCD value

BO )

when 67=0 then: B6

B5 not used

B3 1/2 digit value

B2 polarity

Bl not used

BO autoranging status bit

This interface uses a software driver to reduce hardware complexity. The program is
not unlike a communications driver. To obtain data from the interface effectively, the
computer must be synchronized with the DVM chip and must perform a specific se¬
quence of operations to demultiplex the input data stream.

The actual program that interfaces to and stores the values from the DVM chip is
written as a subroutine. All the information necessary for proper execution of the
driver is provided in the DE register pair at the time of the call. Its contents will tell the
interface which channel to set, whether it should be AC or DC, and which V w and
gain to use. One channel is converted every time the driver routine is called.

The information set in the DE register pair at the time of the call is the command out-

CONNECT1NG ZAP TO THE REAL WORLD 205

Copyrighted material

put byte (port 1 output), and each bit has the designations previously listed. The only
difference is that bit 7 (the enable/disable bit to the A/D converter) is sent as a logic 0
when doing a call. The driver will set it to an enable condition after it has pulled in the
proper relay and allowed a 1.3 ms bounce delay.

Demultiplexing the output of the DVM chip is fairly straightforward. Following the
call, the outputs to the interface close the proper switches, and the central processor
hangs in a loop waiting for an end-of-conversion signal. When this happens, the pro¬
gram knows that the next 4 digits of data are what it wants. The DVM chip sets each of
the digit select lines successively, and the program records the values of the 4 BCD data
lines each time. It strips the status and polarity bits from the MSD Vi-digit byte and
reformats and stores the voltage input value in 4 bytes of memory. The 3 whole digits
are stored in BCD notation and occupy 3 of the bytes. The l /a digit, polarity, and out
of range indication are located in the fourth byte. Polarity is indicated by setting the
MSB. A positive reading is a logic 1 and a negative input is a logic 0. The Vi-digit value
can only be a 0 or 1 and occupies the LSB of the quantity. Out of range is handled with
a little program manipulation. If the driver detects that the incoming reading is not
within range, it sets the equivalent of +2 in the Vi-digit byte. Obviously, this is an il¬
legal condition for a DVM only capable of counting to 1999. The programmer using
this stored data should check the limits of the data before acting upon it.

When the driver completes its operation, it has acquired a 3Vi-digit reading and
stored it as 4 bytes in a special table in memory. The 8 channels of data constitute a
32-byte table. The location of a particular channel's data is found by a simple expres¬
sion:

The 4-byte data starts at memory location L+4(N — 1)

where L = starting address of memory table
N = channel number (1 to 8)

Figure 8.19 is the assembly listing of the program that exercises this DVM interface.
When assembled, it occupies less than a page of memory.

Note: One caution should be kept in mind when measuring AC signals with this in¬
terface. The ground on the DVM interface is the same as the computer's and a potential
short circuit exists unless either the computer power supply or the measured voltage is
isolated.

0100

0110

*** MC14433

3 1/2 DIGIT A/D CONVERTER DRIVER

0120

0125

* REV*

1*9

0130

0140

DIP

EQU

DATA INPUT PORT NUMBER

0150

SIP

EQU

STATUS INPUT PORT NUMBER

0160

COP

EQU

COMMAND OUTPUT PORT NUMBER

0170

EEOC

EQU

200

ENABLE EOC INPUT

0180

DEOC

EQU

000

DISABLE EOC INPUT

0190

0200

0210

* CONVERTED

CHANNEL

. DATA BUFFERS

0220

0230

CHANO

000000

0240

000000

0250

CHAN1

000000

0260

000000

0270

CHAN2

000000

0280

000000

0290

CHAN3

000000

0300

000000

Figure 8.19 A listing of the assembly-language

0310

CHAN4

000000

program that exercises the digital voltmeter .

0320

000000

0330

CHAN5

000000

0340

000000

206 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

0350 CHAN6 DU 000000
0360 DU 000000

0370 CHAN7 HU 000000

0380 DU 000000

0390 *

0400 * INTERMEDIATE DATA BUFFERS
0410 *

0430 CHAN DB 000 CURRENT CHANNEL NUMBER

0440 CCP DU 000000 COMMAND CHANNEL PARAMETER

0460 *

0470 *

0480 *** START A/D CONVERTER
0490 *

0550 *

0560 START L.D ArE
0570 LD (CCP)rA

0580 AND 007

0590 LD (CHAN)f A

0600 LD IXfCHANO

0910 L. D DfO

0920 LD ErA

0930 SLA E CALCULATE BUFFER OFFSET

0940 SLA E

0950 ADD IX r DE

0960 *

0970 * SELECT CHANNEL AND START CONVERSION
0980 *

0985 LD B r 3 SET CYCLE COUNT

0990 SCSC LD Af(CCP)

1000 OUT COP SELECT CHANNEL

1005 CALL DELAY

1010 OR EEOC ENABLE EOC OUTPUT

1020 OUT COP COMMAND A/D CONVERTER

1030 *

1040 * UAIT FOR EOC
1050 *

1060 UEOC IN SIP READ CONVERTER STATUS

1070 BIT OrA TEST FOR EOC

1080 JR ZrUEOC JUMP IF NOT READY

1085 DJNZ SCSC

1090 BIT If A TEST FOR OVERANGE

1100 JR NZfOVER JUMP IF TRUE

1110 *

1120 * CONVERSION DONEfPROCESS FIRST (MSD) DIGIT
1130 *

1140 MSDO LD Bf200 SELECT DIGIT 1

1150 CALL RDIG UAIT AND READ DIGIT 1

1160 CPL

1170 RRCA RIGHT JUSTIFY DIGIT VALUE

1180 RRCA

1190 RRCA

1200 AND 1 ISOLATE

1210 LD EfO INITIALIZE STATUS BYTE

1220 BIT 2rD TEST POLARITY

1230 JR NZfMSD3 JUMP IF POSITIVE

1240 LD Ef200 LOAD POLARITY SIGN

1440 *

1450 * SAVE MSD AND CURRENT POLARITY
1460 *

1470 MSD3 OR E ADD POLARITY SIGN TO MSD

1480 LD (IX+O)fA SAVE IN DATA BUFFER

1500 *

1510 * PROCESS 2ND DIGIT
1520 *

1530 RRC B SELECT DIGIT 2 Figure 8.19 continued

CONNECTING ZAP TO THE REAL WORLD 207

Copyrighted material

1540 CALL RDIG WAIT AND READ DIGIT

1550 AND 017 ISOLATE

1560 LD <IX+1)fA STORE SECOND DIGIT

1570 *

1580 * PROCESS 3RD DIGIT
1590 #

1600 RRC B SELECT 3RD DIGIT

1610 CALL RDIG WAIT AND READ DIGIT

1620 AND 017 ISOLATE

1630 LD (IX+2)fA STORE

1640 *

1650 * PROCESS 4TH DIGIT
1660 *

1670 RRC B SELECT 4TM DIGIT

16S0 CALL RDIG WAIT AND READ DIGIT

1690 AND 017 ISOLATE

1700 LD (IX+3)fA STORE

1710 RAPUP RET
1720 *

1730 * LOAD 2.000 OVERRANGE VALUE INTO DATA BUFFER
1740 *

1750 OVER

A f 2

LOAD MSD VALUE

1760

(IX+O)

1770

XOR

1780

(IX+1)

rA LOAD LSD VALUES

1790

(IX+2)

r A

1800

(IX+3)

1810

RAPUP

1870 *

1880 #

1890 * READ DIGIT ROUTINE

1900

1910

RDIG

DIP

READ DATA BYTE

1920

CPL

CONVERT TO HIGH TRUE

LOGIC

1930

Dr A

SAVE COPY

1940

AND

TEST FOR GIVEN DIGIT

READY

1950

Zf RDIG

JUMP IF NOT

1960

AfD

RESTORE A REGISTER

1970

RET

RETURN TO CALLER

1980

DELAY

Cf 377

1990

DELI

DEC

2000

RET

2010

DELI

Figure 8.19 continued

Potential Applications

I feel that data acquisition is a natural application for ZAP. The interface outlined
above can be used in a solar heating system to monitor and record pertinent data.
Using the facilities of the ZAP monitor and the DVM interface routine, an 8-channel
data logger is practical. In general, all thal would be required is a supervisory program
that calls the DVM 8 times to obtain the 8 sensor inputs. It then sets the limits of the
memory table to a serial output subroutine and stores the readings on a cassette. This
could be done continuously or at regular intervals. The ultimate system would include
a real-time clock so that these readings, as well as the times at which they were taken,
could be recorded.

Real-Time Clock

If ZAP is going to be used for critical data acquisition or control functions, consider¬
ation should be given to real-time synchronization with process events. A simple defi¬
nition of a real-time system is one that responds to the need for action in a period of

208 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

time proportional to the urgency of the need. It boils down to the fact that the comput¬
er must be capable of performing a specific action at a specific time. For this to happen,
the computer must be able to "tell time."

We can accomplish this by using either software or hardware applications. The
simplest technique is to use a clock circuit (figure 8.20) to provide a time tick to the cen¬
tral processors nonmaskable interrupt line. It can be every 60th, 10th, or 1 second, as
suggested in the schematic. When the computer acknowledges the interrupt, it first
saves all the registers from the program it was executing, and then services the real-time
interrupt. Frequently, the first action is to increment an internal counter that keeps
track of elapsed time. Usually it's a value equivalent to the total number of clock ticks,
whether in seconds or milliseconds. Once this regular interval has been established, it is
easy for the computer to perform real-time functions.

Clock resolutions down to milliseconds sound great and make interval timing ex¬
tremely accurate. However, I doubt most ZAP builders would want to use such an in¬
terface in light of the complex software involved. I much prefer an interface that is
easier to implement and more likely to be used.

Essentially, the kind of real-time system most appealing to ZAP owners has a resolu¬
tion of perhaps 1 minute rather than 1 ms. Also, it's best if it can be read directly in
hours and minutes rather than as a total clock count. A direct benefit is reduced over¬
head. The computer does not have to acknowledge the clock update or scan status flags
as often. At first glance, it may not seem like much of a saving, but some routines can
use up to 10 percent of the processor time handling a millisecond clock interrupt.

ICl

7414

Figure 8.20 A simple time-base generator for an interrupt-driven real-time clock.

An Old Clock Chip to the Rescue

The easiest way to provide an hourly and minute-by-minute input is to interface the
computer to an MOS/LSI clock chip similar to that found on most digital clocks or
watches. There are two approaches to the design of a clock interface: one method is to
let the clock circuit operate independently from the computer, attached in such a way
that the computer can monitor the output lines and extract a time value on the fly. The
software necessary for this approach would be very much like the DVM interface
described previously. The other method, which I prefer because it involves less soft¬
ware, is to give the computer complete control over the information flow of the clock
in a synchronous manner.

CONNECTING ZAP TO THE REAL WORLD 209

Copyrighted material

Figure 8.21 shows such a clock interface. This circuit, manually preset to keep it sim¬
ple, is computer directed. The basic 4-chip circuit consists of an MM5312 4-digit BCD/
7-segment output digital clock chip, an MM5369 time-base generator, and two MOS-
to-TTL buffers to send data to the processor.

Time is set on the chip by grounding the slow and fast set lines, pins 14 and 15. To
know what is being set you must read the interface at the same time, and display the
time on the 4-digit hexadecimal address display, already part of the expanded ZAP.
Time is read from the interface as 4 binary-coded decimal numbers. The 8 input lines to
the computer are attached to an 8-bit parallel input port, and are divided between 4
digit-enable lines, and 4 BCD digit-value lines. Data appear as a digit enable and an
associated BCD number. The tens of minutes data is read on BO thru B3 when B5 is
high (B4, B6, and B7 are low). Similarly, BO thru B3 will hold the tens of hours quantity
when B7 is high. The interface logic will stay on a particular digit until it is instructed to
proceed to the next digit. Sequencing is under program control and uses one output bit
of a convenient parallel port.

o* DIGIT ENABLE 8C0 VALUE

ONE BIT OP A OUTPUTS

PARALLEL PORT V_ J

TO PARALLEL INPUT PORT

1C*

TYPE

♦ 3V

♦ 12V

CNO

MM5312

MMS369

CD4049

C04049

7406

74147

C04050

FOR 12

HOUR OPERATION.

PIN 11

| IS GR0UN0E0 ON THE

MM5312.

♦ 12 TO 15V
FROM COMPUTER

1N4002

V00

IC2

MM5369

CLOCK INTERFACE
GND

*-nl

l« APPROX. 12mA
ON STAN08Y

— 12V BATTERY

Figure 8.21 A schematic diagram of a real-time clock interface.

a) Using a MOS digital clock chip.

b) With battery backup.

210 CONNECTING ZAP TO THE REAL WORLD

Copyrighted material

Figure 8.22 shows how the multiplexer line is controlled in this application. One bit
of an output port is used to pulse multiplexer input pin 22. (All that is required is a 1 ms
pulse. As an alternative, a one-shot could be triggered from a decoded strobe line of an
unwired port.) At any time, 1 of the 4 digit-enable lines will be low and a digit's value
will be on the BCD output lines. Just determine which digit it is and store the value.
Next we pulse the multiplexer input to enable the next digit and save it as well. Con¬
ceivably, it takes only 4 iterations of this procedure to obtain a complete 4-digit
reading. If you prefer a more orderly approach, you can follow the program flow out¬
lined in figure 8.23. The only difference is that it waits until the chip cycles to the begin¬
ning before storing the readings.

multiplex timing input

MINUTES (UNITS)

Figure 8.22 The multiplex timing sequence
for the display in the circuit of figure 8.21.

MINUTES (TENS)

HOURS (UNITS)

HOURS (TENS)

CONNECTING ZAP TO THE REAL WORLD 211

Copyrighted material

CHAPTER 9

BUILD A CRT TERMINAL

LOW COST VERSATILE CRT TERMINAL

This chapter describes the design of a low-cost features-oriented cathode-ray tube
(CRT) terminal. Two MOS/LSI devices from Standard Microsystems Corporation
reduce the number of parts required for a CRT terminal yet enhance its capabilities.

The two devices, the CRT 5027 video timer and controller and the CRT 8002 video
display attributes controller, provide virtually all of the circuitry for the display por¬
tion of the CRT terminal. (See Appendices C8 and C9 for specifications.)

The terminal is designed to stand alone and communicate via an RS-232C interface
with any computer system. If, in the expanded ZAP, the 6-character hexadecimal dis¬
play proves inadequate, then the experimenter has only to construct this unit and at¬
tach it to the serial port already assembled.

Device Description

The CRT 5027 contains the logic required to generate all of the timing signals (ver¬
tical and horizontal synchronization, page refresh memory address, etc.) required by a
CRT terminal. The entire display format including interlace/non-interlace, characters
per row, rows per frame, scans per row, horizontal synchronization pulse width, and
timing are user programmable for all standard and most nonstandard formats.

Although the CRT 5027 is basically structured for use with its own microprocessor,
this design describes a "dumb terminal" using a low-cost PROM and standard TTL
logic to replace the microprocessor control. While increasing the number of the parts,
this design results in a low-cost, high quality alphanumeric/graphics terminal.

The CRT 8002 provides a 7 X 11 dot matrix, 128 character generator ROM, and a
high-speed video shift register cursor. It includes logic to generate such functions as
underline, blinking, reverse video, blanking, and strike-through. Additional wide and
thin graphics modes allow the creation of line drawings, forms and unique graphic
symbols.

Terminal Description

As with most electronic designs, a CRT terminal involves a large number of perfor¬
mance and cost trade-offs. A screen format of 16 rows of 64 characters per row was se¬
lected to minimize memory requirements (1 K bytes) and keep the video frequency
within the limits of lower cost video monitors. An 80-character line would have not
only increased the video frequency beyond the bandwidth of many low-cost monitors,
but also would have increased the memory requirements. Similarly, more rows per
page would have increased the memory requirement unless the characters per line were
reduced.

In many microprocessor applications, the page memory is shared with the processor
via a data bus. In this application, the page memory is used strictly by the CRT with
data input synchronously, character-by-character, into the cursor position.

Full graphics or attributes may be selected on a character-by-character basis using

BUILD A CRT TERMINAL 213

Copyrighted material

control words on the input data bus. A block diagram of the terminal is shown in figure
9.1.

Figure 9.1 A block diagram of a lov/-cost cathode-ray tube terminal.

Character Format

The CRT 8002 requires a minimum 8 X 12 character block to form its basic 7 X 11
character and to provide line and character spacing. However, in order to allow fram¬
ing a character fully for a reverse video presentation, the horizontal character block
must be increased to 9 or 10 dots. For the same reason, allocating 13 lines per character
allows top and bottom framing as well.

With the standard TV sweep rates of 60 Hz (vertical) and 15,750 Hz (horizontal),
there are 15,750 + 60 = 262.5 lines per frame. As non-interlaced operation requires
an even number of lines, a horizontal frequency of 15,720 Hz is used. The 16 rows
X 13 scan lines per row result in 208 lines of displayed data. The remaining 54 lines
will be automatically blanked by the CRT 5027 and will provide upper and lower
margins.

To allow for left and right margins as well as for retrace time, a total 80 character
times are allocated per line. A good rule of thumb is that the total number of character

214 BUILD A CRT TERMINAL

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times is 25% greater than the actual number of displayed characters.

The video clock frequency is calculated as follows: 10 (dots per character) X 80
(character times per line) X 15,720 Hz (horizontal sweep frequency) = 12.576 MHz.
See the worksheet in table 9.1.

1. HCHARACTER MATRIX (No. of Dots):.. Z.

2. V CHARACTER MATRIX (No Of HoflZ. Scan Lines):. .. LL

3. H CHARACTER BLOCK (Step 1 + Oesired Horiz. Spacing = No. in Dots): _ !£.

4. V CHARACTER BLOCK (Step 2 + Desired Vertical Spacing = No. in Horiz.

Scan Lires):.

5. VERTICAL FRAME (REFRESH) RATE (Freq. in Hz): . ...

6. DESIRED NO. OF DATA ROWS:.

7. TOTAL NO. OF ACTIVE "VIDEO DISPLAY" SCAN LINES

(Step4x Step6 = No. in.Horlz. Scan Lines): _ .. .

8. VERT. SYNC DELAY (No. in Horiz Scan Lines):.

9. VERT. SYNC (No. in Horiz. Scan Lines; T« J!?GJL.p$*):.

10. VERT. SCAN DELAY (No. in Horiz. Scan Lines; T » f-5? ms*):....

11. TOTAL VERTICAL FRAME (Add steps 7 thru 10 * No. in Horiz. Scan Lines):

12. HORIZONTAL SCAN LINE RATE (Step 5 x Step 11 = Frcq.inKHz):.

13. DESIRED NO. OF CHARACTERS PER HORIZ ROW: .

14. HORIZ. SYNC DELAY(No.in Character Time Units;T Z2_/iS**): ...

15. HORIZ. SYNC (No In Charac'er Time Units;T = 5 57 .

16. HORIZ. SCAN DELAY (No. in Character Time Units; T =_iLl?Lr/s* •): ..

6 O
16

JOS

is.nsLO

17. TOTAL CHARACTER TIME UNITS IN (1) HORIZ. SCAN LINE

(Add Steps 13thru 16):.

18. CHARACTER RATE (Step 12 x Step 17 = Freq. in MHz): ..

19. CLOCK (DOT) RATE (Step 3 x Step 18 » Freq. in MHz):. ...

_ 80 _
10576
/a 5 7 6

’Vertical Interval
••Horizontal Interval

Table 9.1 A CRT 5027 worksheet for a 64 characters per row, 16 row, noninterlaced screen format

Programming the VTAC

The CRT 5027 VTAC (Video Timer and Controller) is user programmable for all
timing and format requirements. The programming data is stored in 9 on-chip regis¬
ters. Although a microprocessor can easily provide the programming data, a low-cost
PROM is used in this application. The 9 registers are programmed as follows (see table
9.2):

Register 0: This register contains the number of character times for one horizontal pe¬
riod, and is normally 1.25 times the number of characters per line, in this case 64 X
1.25 = 80. As the internal counters are initialized at zero, the actual number in the
register is 80 — 1 = 79.

□

1) bit 7 — one for interlace, zero for non-interlace. In this example, noninterlaced
operation is selected.

2) bits 3 thru 6 program the number of character times for the width of the horizon¬
tal synchronization pulse. This parameter is monitor dependent and is typically

BUILD A CRT TERMINAL 215

Copyrighted material

5 ns. Because there are 80 character times for a 63.6 /xs horizontal scan time
(1 + 15,720), each character time is 0.801 /xs; 7 character times will be used to
generate a 5.56 /xs pulse.

3) bits 0 thru 2 set the horizontal ''front porch." This essentially positions the data
horizontally. The monitor's specification will determine initial programming al¬
though some experimentation may be required to center the display exacdy. Six
character times were selected for the front porch.

ADDRESS

REG. *

A3 A0

FUNCTION

BIT ASSIGNMENT

HEX.

DEC.

0030

HORIZ LINE COUNT 20

1° 1 0 1 0 1 1 1 1 1 1 1 1 1

0001

INTERLACE 0

H SYNC WIDTH 7

H SYNC DELAY 6

0101111 i|i 1 1 0

0010

SCANS/DATA ROW _J3_
CHARACTERS/ ROW

X 1 i 0 0 0 1 1

£3

0011

SKEW CHARACTERS_ L

DATA ROWS /6 —

100101111

0100

SCANS/FRAME _ 262
X =

0 0 0 0,0 011

0101

VERTICAL DATA START
= 3 + VERTICAL SCAN DELAY:
SCAN DELAY —35 ,

DATA START

0 01110 0

2.8

0110

LAST DISPLAYED DATA ROW
(= DATA ROWS)

XIX001111

Table 9.2 A CRT 5027 register-programming worksheet for a 16 x 64 screen format

1) bits 3 thru 6 (bit 7 is not used) set the number of scans per character. In this case,
we have defined the character as 10 X 13, so the binary equivalent of 13 — 1 83
12 is used (all CRT 5027 counters start at zero, not one, so programming of
counters is always one less than the number).

2) bits 0 thru 2 contain a 3-bit code for the number of characters per line. From the
data sheet the code for 64 is Oil.

1) bits 6 and 7 delay the blanking cursor and synchronization timing to allow for
character generator and programmable memory propagation delays. Generally,
one character time will allow for these delays.

2) bits 0 thru 5 define the number of data rows, once again starting with binary zero
for one line. 16 — 1 = 15 will be programmed.

□

Register 4: Register 4 sets the number of raster lines per frame. For the noninterlaced
mode this is derived by the formula (N — 256) + 2 = 3.

216 BUILD A CRT TERMINAL

Copyrighted material

Register 5: This contains the number of raster lines between the start of the vertical
synchronization pulse and the start of data (vertical synchronization + back
porch). This time must be long enough to allow for the full retrace time of the
monitor and to allow vertical positioning of the display. We will use 28 here. The
front porch will be calculated by the CRT 5027 as 262 — (13 X 16) — 28 = 26.

Register 6: Register 6, the scrolling register, is programmed with the number of the last
data row to be displayed. Since we want to initialize the CRT 5027, this will be
programmed the same as Register 3 (bits 6 and 7 are not used).

Register 7 and Register 8: These registers contain the cursor character number and row
number respectively. Since the cursor is to be initially positioned at the top left
corner, both registers will be initialized with all zeros. Subsequent cursor position
changes will be entered as described under "circuit operation."

Circuit Description

Referring to figure 9.2, IC 1A, IC IB, IC 4 provide the video dot clock (12.58 MHz)
and the character clock DCC, which is the dot clock + 10 (each character is 10 dots
wide). The video dot clock determines the actual video data rate. The character clock
determines the speed each character is addressed. IC 6A buffers the dot clock input of
the CRT 8002. A pull-up resistor is used on the output to guarantee the logic one re¬
quirement of the VDC input.

The LOAD command loads the register information required for programming the
CRT 5027 from the PROM IC 7 to the CRT 5027. The "self load" capability of the CRT
5027 is used to automatically scan the PROM addresses. LOAD is automatically gener¬
ated on power-on by IC ID.

Because of the bus structure of the CRT 5027, cursor position information is loaded
on the same bus as the register data. Three-state data selectors IC 14 and IC 15 select
cursor X position data from counter IC 8 and IC 7 or cursor Y position data from
IC ID. IC 12 and IC 13 select the address mode for the CRT 5027. Three modes are
used: "nonprocessor self-load" for register loading, load cursor X position, and load
cursor Y position.

IC 16 thru IC 21 decode attribute mode and cursor controls from the ASCII data
bus. If graphics or special attributes are not desired, IC 16,17, and 21 are not required.
Similarly, if cursor controls are directly available, decoding them is not necessary.

IC 19 and IC 20 are 256 X 4 PROMs. Their exact programming can be suited to the
user needs. The programming used in this terminal is shown in table 9.3. When a key
designated as an attribute or mode key is depressed, the appropriate control word is
latched in IC 21; all subsequent data entries will have that word loaded in the upper 4
bits of programmable memory. This allows the attribute or mode to be changed on a
character-by-character basis. IC 18, a 2 to 4 decoder, is enabled when a cursor control
backspace, carriage return/line feed, or \ is decoded and provides the appropriate cur¬
sor movement.

TTL or low power TTL can be used throughout. Shottky TTL is recommended for
IC 6 due to the fast rise time requirements of the clock input.

BUILD A CRT TERMINAL 217

Copyrighted material

IC 22

IC 2 3

IC 24

tC 25

IC27

IC 28

IC 29

•C 30

IC 31

• C 32

IC 33

TO OND

ENABLE

<Al

1 C 19
7621 A

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101

102

WRITE

103

107

106

105

104

103

102

ID 1

100

♦5

!C 20

7621 *

A 8

A 6

0 ?

A 5

A 4

A 3

A 2

_ 3

107

106

105

104

103

ID 2

101

100

♦5

IC6D

IC16B

C17A

«C 6 E

ATC
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IC18

74155

CRIF

MODE AND
ATTRIBUTE

CONTROL

♦ 5

104

105

106

107

IC 11 D

ICS

8 DR

IC 178

IC 160

IC17C

MSI

MSO

00-07

PAGE MEMORY

“ o

INPUT DATA
FROM UART
OR

KEYBOARD

NUMBER

TYPE

IC1

74LS04

IC2

CRT8002

IC3

CRT5207

1C 4

74LS160

ICS

74LS20

1C 6

74LS04

1C 7

HM7603 PROM

IC8

74193

IC9

74193

ICtO

74193

ten

7408

1C 12

74LS02

IC1S

74LS74

1C 14

74LS257

IC15

741.S257

IC16

74LSC2

IC17

74LS00

acts

741 ss

IC19

HM7621A

PROM 1

IC20

HM7621

PROM 2

1C 21

74174

IC22-IC33

2102A-4

Figure 9.2 A schematic diagram of a low-cost versatile CRT terminal using the CRT 5027 and CRT
8002 chips (continued on next page).

218 BUILD A CRT TERMINAL

Copyrighted material

♦5

Figure 9.2 continued

BUILD A CRT TERMINAL 219

Copyrighted material

Operation

After power-on. Control Q should be depressed to latch the system in the "normal"
mode. Depressing the space key and the erase key simultaneously will then blank the
screen. All further character entries will be displayed normally. If other attributes or
graphics are desired, the appropriate control code is entered. This character will not be
displayed or cause cursor movement, but will latch the new command. Modes may be
changed for every character desired. Cursor movement may be decoded from the
ASCII input by the control key as indicated in table 9.3.

PROM Programming

Keyboard Entry

Function

Address

PROM 1 Output

PROM 2 Output

76543210

J?iP?PjPl-

,P.iP>P?Pl.

Return

Carriage Return

00011011

0011

1000

Line Feed

00010101

1011

1000

Control H

Cursor Left

00010001

0111

1000

Cursor Up

00111101

1111

1000

Cursor Right

00111111

1111

1010

Control Q

Normal Attribute

00100011

1111

1011

Control W

Blink

00101111

1011

Control E

Underline

00001011

0111

1011

Control R

Reverse Video

00100101

0011

1011

Control T

External Mode

00101001

1101

1011

Control Y

Wide Graphics

00110011

1100

1011

Control U

Thin Graphics

00101011

1110

1011

Balance of PROM

0011

1110

Table 9.3 PROM programming for the circuit of figure 9.2.

The Rest of the System

Figure 9.3 illustrates the balance of the circuitry required to implement a full
RS-232C compatible serial I/O terminal. Utilization of MOS/LSI reduces the package
count to a bare minimum.

A KR2376 keyboard encoder, IC 1, encodes and de-bounces the keyboard switches
and provides an ASCII data word to the COM 2017 UART (see Appendices C6 and
C7). The UART, in turn, provides the serial receive/transmit interface. The data rate is
programmable by means of the switch controlled input code to a COM 8046 data rate
generator (see Appendix CIO).

TERMINAL VARIATIONS

The terminal described can easily be modified for a wide variety of other screen for¬
mats. The following changes are required for an 80-characters per row, 24-row format:

1. Horizontal sweep rate — to allow for the increased number of displayed lines
(312), the horizontal sweep rate is increased to 20,220 Hz.

2. The video oscillator frequency is calculated as 9 (dots per character) X 100 (char¬
acter times per row) X 20,220 °* 18.198 MHz. Notice that 9 dots per character
was selected instead of 10, as 10 would have resulted in a clock frequency of
20.2 MHz, which is beyond the CRT 8002A's top frequency. IC 4, therefore,
must be set for divide by 9 rather than 10.

3. An additional 1 K bytes of page memory is required. Figure 9.4 shows the revised
address connections.

4. Register programming for the CRT 5027 follows the worksheet shown in tables
9.4 and 9.5.

220 BUILD A CRT TERMINAL

Copyrighted material

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Figure 9.3 A schematic diagram of a
RS-232C interlace for a terminal.

Figure 9.4 A memory-mapping system
for a 24 x 80 screen format.

dro

DRl

0R2

DR3

DR4

■ 1 “ l 6 1 » l 3 1 S F

4A 28 3A IB 2A 1A
74LS257

A10

E 48 38 4Y 3V 2Y 1Y
i 15 113 llO [12 i9 17 [a

BUILD A CRT TERMLNAL 221

Copyrighted material

TO RAM

1 . H CHARACTER MATRIX (No. of Dots):.

2. VCHARACTER MATRIX (No. ol Horiz. Scan Lines): .

3. H CHARACTER BLOCK (Step 1 + Oesired Horiz. Spacing = No in Dots):

±_

4. V CHARACTER BLOCK (Step 2 + Desired Vc'lical Spacing • No. in Horiz.

Scan Lines):. .. .. 1 3

5. VERTICAL FRAME (REFRESH) RATE {Freo. in Hz):..60.

6. DESIRED NO. OF DATA ROWS:.. 2M-

7. TOTAL NO. OF ACTIVE ‘ VIDEO DISPLAY" SCAN LINES

(Step4xStep6 = No. in Horiz. Scan Lines): . 3/3-

8 VERT. SYNC DELAY (No. in Horiz Scan Lines):..L_

9. VERT. SYNC (No in Horiz. Scan Lines. T=_^3 J_//s*):..L.

10 VERT. SCAN DELAY (No. in Hcriz Scan Lines; T « 890 2. ua «) : .. [8_

11. TOTAL VERTICAL FRAME (Add steps 7 thru 10 - No. in Horiz. Scan Lines): 336

12. HORIZONTAL SCANLINE RATE (StepS x Step 11 = Freq.inKHz): .. . 20220

13. DESIRED NO. OF CHARACTERS PER HORIZ ROW:. &

14. HORIZ. SYNCDELAY (No. in Character Time Umts.T s**): 3

15. HORIZ. SYNC (No. in Character Time Unils:T * V W os**): 10

16. HORIZ. SCAN DELAY (No. in Character Time Units; T ■ 3 46 •):..

17. TOTAL CHARACTER TIME UNITS IN (1) HORIZ. SCAN LINE

(AddStepsl3thrul6):..

18. CHARACTER RATE (Step 12 x Step 17 • Freq. in MHz): . .

19. CLOCK (DOT) RATE (Stop 3 x Step 18 *= Freq. in MHz): ..

too
2022 .
IS 198

'Vetiicaltnterval
*’Horizontal Interval

Table 9.4 A CRT 5027 worksheet for an 80 characters per row, 24 row, noninterlaced screen format.

ADDRESS

REG# A3 AO

FUNCTION

BIT ASSIGNMENT HEX. DEC.

ooco

0001

0010

0011

0100

HORIZ. LINE COUNT .100

INTERLACE

H SYNC WIDTH_ LO

H SYNC DELAY

SCANS/DATA ROW. JA.
CHARACTERS/ROW_ IQ.

SKEW CHARACTERS_-L

DATA ROWS -

SCANS/FRAME 336

X -

0 1 1

I 63 99

53 83

] 0 I 1 o | 1 | 0 | 0 | 1 { 1

1 65 10/

x 1 1 1 1 0 I 0 I 1 I 0 I 1

1 97 15/

o | o | 1 | o | 1

0 1 0 0 1

c 18 40

0101

VERTICAL DATA START
= 3 + VERTICAL SCAN DELAY:

SCAN DELAY _/£_

DATA START *1

0 0 10 1

0 1

0110

LAST DISPLAYED DATA ROW
(«= DATA ROWS)

X I x 101

1 0

H 1 1 n a.5

Table 9.5 A CRT 5027 register-programming worksheet for a 24 x 80 screen format.

222 BUILD A CRT TERMINAL

Copyrighted material

APPENDICES

Copyrighted material

Appendix A

Construction Techniques

CONSTRUCTION TIPS

As a result of building a project every month for my "Ciarcia's Circuit Cellar" col¬
umn in BYTE magazine and of constructing every circuit in this book, I feel I can speak
as an authority on the subject of prototype construction. A prototype is a nice term
that describes the one-of-a-kind kluge that you build from a schematic. This is opposed
to the kit or semi-assembled project that includes a printed circuit board which only re¬
quires plugging in components.

Prototyping a circuit is not easy. There are many dos and don'ts, but successful pro¬
totyping is primarily a function of experience. And experience comes only by building
something.

The text is purposely laid out with this philosophy in mind. I suggest that you start
with the power supply. Not only is the rest of the computer useless without it, but it
has built-in protective circuitry that is very forgiving if you make mistakes. Also, by
constructing the power supply first, there is less likelihood of destroying the rest of the
computer as you are testing the power supply.

In general, the cardinal rule of prototyping is: be neat. The ZAP computer has high
frequencies. Wiring should be the shortest distance between two connections. The
longer the wire, the more of an antenna it becomes. In extreme cases, the computer can
actually cease to function because of induced electrical noise. With the relatively
slower digital signals carried by the wiring attached to external input and output ports,
the situation is less critical. Short pulses and high-speed data, such as the signals on the
central processor control and address lines, are more critical. In these cases, it is always
a good idea to use additional protective circuitry such as buffers.

To a certain degree, the ZAP computer can be laid out as you see fit. Figure A.l sug¬
gests one approach: it can be wirewrapped or hand soldered. Almost any board large
enough to accommodate all the chips should suffice. A good choice is a standard S-100
prototyping card available at most computer stores. There is no particular bus other
than the standard Z80 signals designated for ZAP because it is primarily intended as a
single-board system. The 100-pin connector provides a convenient I/O and power con¬
nector. Care should be taken if you decide to split the computer schematic and assem¬
ble the computer on more than one board. The separation should be between logical
subsystems; for maximum success, all signals should be buffered in and out of the
board, e.g., all the memory could be put on a separate card. As outlined in the text, the

address and data lines necessary to this function are already properly buffered.

The question of wirewrapping versus soldering is the builder's prerogative. Personal¬
ly, I prefer point-to-point hardwiring because it's easier to modify when troubleshoot¬
ing. Wirewrapping might be easier where the ZAP circuit has already been tested and
refined.

Long power-supply daisy chains should be avoided. Rather than running a single
+5 V and ground wire, it is better to use a double-sided prototyping board so that the
top and bottom sides of the board can be set to ground and +5 V respectively. With
this approach, each chip can be plugged in (using IC sockets) and the power leads
soldered directly to the copper planes. Wirewrapping or not, it is a good idea to solder
the power leads to reduce the potential of intermittent connections. Using the ground

APPENDIX A 225

Copyrighted material

SPARE

IC9

7404/7414

IC8

7404

IC1

7400

2.0MH*

XTAL

</)

CJ
i n

—

1.8432MMI

MC14411/C0MB046

—■

XTAL

Figure A.1 A typical layout of the basic ZAP computer.

plane for wiring is one of the best ways to reduce noise in computers. If you don't have
a ground plane, then solder heavy wire around the perimeter of the circuit board and
run short jumpers to it.

Decoupling capacitors are another must for computer prototyping. Digital-inte¬
grated circuits, while being virtually burn-out proof in most applications, are unfor¬
tunately susceptible to noise carried along the power lines. Often, it will cause them to

226 APPENDIX A

Copyrighted material

go into oscillation. By placing a 0.01/*F to 0.1/iF capacitor between +5V and ground
about every third IC, the problem is eliminated. Another good idea is to place an elec¬
trolytic capacitor at the entrance of any DC power connection to the board. Generally,
capacitors are tantalum and three pieces would be required for ZAP's three supplies.

Finally, if you like the concept of ZAP but would rather spend more time applying
the finished product than testing your construction techniques, you can look into pur¬
chasing EPROMs programmed for the ZAP monitor. The monitor for the ZAP com¬
puter is available in a 2708 or single-volt 2716 EPROM for $25. Please specify the type
you want when ordering. These are available from The Micromint, Inc., 917 Midway,
Woodmere, NY 11598. Telephone (516) 374-6793.

APPENDIX A 227

Copyrighted material

Appendix B
ASCII Codes

Parity

Control

Space

Keybd.

Dec

Octal

Hex

Character

Equiv.

Alternate Code Names

000

Even

NUL

NULL, CTRL SHIFT P, TAPE LEADER

001

Odd

SOH

START OF HEADER, SOM

002

Odd

STX

START OF TEXT, EOA

003

Even

ETX

END OF TEXT, EOM

004

Odd

EOT

END OF TRANSMISSION, END

005

Even

ENQ

ENQUIRY, WRU, WHO ARE YOU

006

Even

ACK

ACKNOWLEDGE, RU, ARE YOU

007

Odd

BEL

BELL

008

010

Odd

BACKSPACE, FE0

009

011

Even

HORIZONTAL TAB, TAB

010

012

Even

LINE FEED, NEW LINE, NL

011

013

Odd

VERTICAL TAB, VTAB

012

014

Even

FORM FEED, FORM, PAGE

013

015

Odd

CARRIAGE RETURN, EOL

014

016

Odd

SHIFT OUT, RED SHIFT

015

017

Even

SHIFT IN, BLACK SHIFT

016

020

Odd

DLE

DATA LINK ESCAPE, DC0

017

021

Even

DC1

XON, READER ON

018

022

Even

DC2

TAPE, PUNCH ON

019

023

Odd

DC3

XOFF, READER OFF

020

024

Even

DC4

TAPE, PUNCH OFF

021

025

Odd

NAK

NEGATIVE ACKNOWLEDGE, ERR

022

026

Odd

SYN

SYNCHRONOUS IDLE, SYNC

023

027

Even

ETB

END OF TEXT BUFFER, LEM

024

030

Even

CAN

CANCEL, CANCL

025

031

Odd

END OF MEDIUM

026

032

Odd

SUB

SUBSTITUTE

027

033

Even

ESC

[

ESCAPE, PREFIX

028

034

Odd

FILE SEPARATOR

029

035

Even

]

GROUP SEPARATOR

030

036

Even

RECORD SEPARATOR

031

037

Odd

—

UNIT SEPARATOR

032

040

Odd

SPACE, BLANK

033

041

Even

034

042

Even

035

043

Odd

036

044

Even

037

045

Odd

038

046

Odd

039

047

Even

APOSTROPHE

040

050

Even

(

041

051

Odd

)

042

052

Odd

•

043

053

Even

044

054

Odd

COMMA

045

055

Even

—

MINUS

046

056

Even

•

047

057

Odd

APPENDIX B 229

Copyrighted material

Parity Control

Space Keybd.

Dec

Octal

Hex

Character

Equiv. Alternate Code Names

048

060

Even

NUMBER ZERO

049

061

Odd

NUMBER ONE

050

062

Odd

051

063

Even

052

064

Odd

053

065

Even

054

066

Even

055

067

Odd

056

070

Odd

057

071

Even

058

072

Even

•

059

073

Odd

•

060

074

Even

LESS THAN

061

075

Odd

062

076

Odd

GREATER THAN

063

077

Even

064

100

Odd

SHIFT P

065

101

Even

066

102

Even

067

103

Odd

068

104

Even

069

105

Odd

070

106

Odd

071

107

Even

072

110

Even

073

111

Odd

LETTER 1

074

112

Odd

075

113

Even

076

114

Odd

077

115

Even

078

116

Even

079

117

Odd

LETTER O

080

120

Even

081

121

Odd

082

122

Odd

083

123

Even

084

124

Odd

085

125

Even

086

126

Even

087

127

Odd

088

130

Odd

089

131

Even

090

132

Even

091

133

Odd

SHIFT K

092

134

Even

SHIFT L

093

135

Odd

)

SHIFT M

094

136

Odd

1, SHIFT N

095

137

Even

SHIFT O, UNDERSCORE

096

140

Even

ACCENT GRAVE

097

141

Odd

098

142

Odd

099

143

Even

100

144

Odd

101

145

Even

102

146

Even

103

147

Odd

104

150

Odd

105

151

Even

106

152

Even

107

153

Odd

108

154

Even

109

155

Odd

110

156

Odd

111

157

Even

112

160

Odd

113

161

Even

230 APPENDIX B

Copyrighted material

Parity Control

Space Keybd.

Dec

Octal

Hex

Character

Equiv. Alternate Code Names

114

162

Even

115

163

Odd

116

164

Even

117

165

Odd

118

166

Odd

119

167

Even

120

170

Even

121

171

Odd

122

172

Odd

123

173

Even

{

124

174

Odd

•

VERTICAL SLASH

125

175

Even

}

ALTMODE

126

176

Even

(ALT MODE)

127

177

Odd

DEL

DELETE, RUBOUT

APPENDIX B 231

Copyrighted material

Appendix C Manufacturers’

Specification

Sheets

Copyrighted material

Appendix Cl

intel

2708

8K (IK x8) UV ERASABLE PROM

Max. Power

Max. Access

2708

800 mW

450ns

2708L

425mW

450ns

2708-1

800 mW

350 ns

2708-6

800 mW

550ns

■ Low Power Dissipation — 425 mW
Max. (2708L)

■ Fast Access Time — 350 ns Max.

■ Data Inputs and Outputs TTL
Compatible during both Read and
Program Modes

(2708-1)

■ Static — No Clocks Required

■ Three-State Outputs — OR-Tie
Capability

The Inter* 2708 is an 6192-bit ultraviolet light erasable and electrically reprogrammable EPROM, ideally suited where
fast turnaround and pattern experimentation are important requirements. All data inputs and outputs are TTL com¬
patible during both the read and program modes. The outputs are three-state, allowing direct Interface with common
system bus structures.

The 2708L at 425mW is available for systems requiring lower power dissipation than from the 2708. A power dissipation
savings of over 50% without any sacrifice in speed is obtained with the 2708L. The 2708L has high input noise Immunity
and is specified at 10% power supply tolerance. A high-speed 2708-1 Is also available at 350ns for microprocessors
requiring fast access times.

The 2708 family is fabricated with the N-channel silicon gate FAMOS technology and Is available In a 24-pin dual In-line
package.

PIN CONFIGURATION

BLOCK DIAGRAM

J*C

□ m

*.c

S-wi — ■ -

*>C

□ cvvrt

1701 '*

3^0

*'C

<Lsei A t C

] rnOCNAM

□ <» IWJSI

p—

IL»OsC

♦

AOO«t»-

•MPUTS

*.-►

o,C

o»C

3°*

w»C

3<»

OOP XfiCCT
lOC»C

txcot**

Of COOf A

DATA OUTPUT
Oq-Oj

111!!!!!

OUTPUT

VCATtHC

MX in
AC* AftftAV

PIN CONNECTION DURING READ OR PROGRAM

PIN NAMES

*oA f

A0ORCSS INPUTS

0. 0.

DATA OUTfvT JIX4VT8

Ctwc

iS ABIC IF^Ut

WODf

PtN suvnr n

AOOR6SS

OATA I/O •SPOTS

♦ii. ;

13 17 12. 73

PR CCRAM

W&o

S*t j
20

A1AO

G UD

G*SD

♦12

V.I

-6

•5

OISC16CT j

[ HIGH iVPtOAKCf r DOWT CARt

QNO

C/4D

• 12

V,m

•6

•»

KRDGR AW

1 ■ 1

QNO

pulud

1 ^

1 ** i

•6

APPENDIX C 235

Copyrighted material

2708 FAMILY

PROGRAMMING

The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section.
Absolute Maximum Ratings*

Temperature Under Bias. -25°C to +85*C

Storage Temperature.-65* C to ♦125°C

Vqd With Respect to V BB .. +20V to -0.3V

Vqc and Vs$ With Respect to V BB . +15V to -0.3V

All Input or Output Voltages With Respect

_to V BB During Read... +15V to -0.3V

5S/WE Input With Respect to V BB

During Programming. +20Vto-0.3V

Program Input With Respect to V B b . *35V to -0 3V

•COMMENT

Stresses above those luted under "Absolute Maximum
Ratings" may cause permanent damage to the device.
Thrs is a stress rating only and functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification n not implied. Exposure to absolute
max mum rating conditions for extended periods may
affect device reliability.

Power Dissipation

1.5W

QC AND A.C. OPERATING CONDITIONS DURING READ

2708

2708-1

2708-6

2708L

Temperature Range

0*C-70*C

Vcc Power Supply

5V ± 5%

5V±5%

5V ± 10%

V 00 Power Supply

12V ±5%

12V * 10%

V BB Power Supply

-5V ± 5%

-5V±5%

-5Vdt5%

-5V*10%

READ OPERATION

D.C. AND OPERATING CHARACTERISTICS

Symbol

Paramatar

2708.2708-1. 2708-6 Umlts

2708L Limits

Units

Teat Conditions

Min. TypJ* Max.

Min. Typjfl Max.

•u

Address and Chip Select Inpul SmK
Current

1 10

V IN . 5.25V or V, M - V 1L

H.0

Output Leakage Current

1 10

VouT-^iV. CS/WE-5V

•ooPi

Voo Supply Current

50 65

21 28

Worst Case Supply Currents* 4 *

•ccw

V cc Supply Current

6 10

2 4

AM In pull High:

•bb^

V BB Supply Current

30 45

10 14

CSWE = 5V; T A a0'C

V.L

Input Low Vonage

Vjj 065

065

V,M

input High Voltage

3.0 V cc *i

22 V CC *1

V i

Vot

Output Low Voltage

0.45

0.4

lot - 1 6mA (2700. 2700-1. 270M)

1o L « 2mA (2708L)

V 0 H.

Output High Voltage

3.7

Ion - “lOO^A

V OMJ

Output Mign Volttg#

2.4

•oh - -imA

Power Dissipation

800

325

T a -70*C

425

Ta«0*C

NOTES: 1. V 8B must be applied prior to and V 00 V„ 5 must also be the last powar supply switched off.

2. Typical »a'u*s are for T A «2S*C end nominal supp y voltages.

3. The totel power dissipation is not calculated by summing the various currents (Ipg, 1 ^. and l 88 ) multiplied by their respective vet-
tapes s nee current paths exist between the various powar supplies and The log. Igc. and i aa currants stoutd be used to deter¬
mine power supply cspaclty only.

4. t Bt for I he 27C0L Is specified In the programmed state and is 18mA maximum in the unprogrammed state.

2708 FAMILY

27081

RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE

2708. 2708-1, AND 2708 6
RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE

Mi ►XJiUC 0#t•AT iNG

COW K»%

v u *»nv

™~>WW - - * A.

■ / i _

V„..*29V

ura

ACCESS TIME VS. TEMPERATURE

236 APPENDIX C

Copyrighted material

AX. CHARACTERISTICS

Symbol

Parameter

2708. 2708L Limits

2708-1 Limits

2708-6 Limits

Units

Min.

Max.

Min.

Max.

Min.

Max.

l ACC

Address to Output Delay

450

350

550

tco

Chip Select to Output Delay

120

160

*DF

Chip Deselect to Output Float

120

160

Iqh

Address to Output Hold

CAPACITANCE 111 T A - 25°C. f - 1 MHz

Symbol

Parameter

Typ.

Max.

Unit.

Conditions

C|N

Input Capacitance

Gout

Output Capacitance

V 0U T * ov

NOTE: 1. TM» is penotfcally templed and t» not 100% tested

A.C. TEST CONDITIONS:

Output Load: 1 TTL gate and Ci. • 100 pF
Input Rise and Fell Times: <20 ns
Timing Measurement Reference Levels: 0.8V and
2.8V for inputs; 0.8V and 2.4V for outputs.
Input Pulse Levels: 0.65V to 3.0V

AX. WAVEFORMS ,J >

NOTES.

2 . ALL T«UfS SHOWN in parentheses ape m n viiju and ape NSEC
UNLESS OTHERWISE SFtClFlED

3. CS MAY BE OELAVEO UP TO lACC «CO AFTER ADDRESSES ARE VAL>0
WITHOUT IMPACT ON lACC

4. «o» IS 5PECIFIE0 FPCM CS OR AOOPESS CHANGE. WHICHEVER OCCURS

first.

ERASURE CHARACTERISTICS

The erasure characteristics of the 2708 family are such that
erasure begins to occur wtien exposed to light with wave¬
lengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluores-
cont lamps have wavelengths in the 3000-4000A range.
Data show that constant exposure to room level fluores¬
cent lighting could erase the typical device in approxi¬
mately 3 years, while it would take approximately 1 week
to cause erasure when exposed to direct sunlight. If the
2708 is to be exposed to these types of limiting conditions
for extended periods of time, opaque labels are available
from Intel which should be placed over the 2708 window
to prevent unintentional erasure.

The recommended erasure procedure (see Data Catalog
PROM/ROM Programming Instructions Section) for the
2708 family is exposure to shortwave ultraviolet light
which has a wavelength of 2537 Angstroms (A). The inte¬
grated dose (i.e., UV intensity X exposure time) for erasure
should be a minimum of 15 Wsec/cm 2 3 4 . The erasure time
with this dosage is approximately 15 to 20 minutes using an
ultraviolet lamp with a 12000 n W/cm 2 power rating. The
device should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes
which should be removed before erasure.

APPENDIX C 237

Copyrighted material

Appendix C2

2716

16K (2K x 8) UV ERASABLE PROM

■ Pin Compatible to Intel® 2732 EPROM

■ Simple Programming Requirements
— Single Location Programming
— Programs with One 50 ms Pulse

■ inputs and Outputs TTL Compatible
during Read and Program

■ Completely Static

The Intel' 2716 is a 16.384 bit ultraviolet erasable and electrically programmable read only memory (EPROM). The 2716
operates from a single 5-volt power supply, has a static standby mode, and features fast single address location program¬
ming. It makes designing with EPROMs faster, easier and more economical

The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with the newer high performance
♦5V microprocessors such as Intel's 8085 and 8086. A selected 2716-5 and 2716-6 is available for slower speed applications.
The 2716 is also the first EPROM with a static standby mode which reduces the power dissipation without increasing access
time. The maximum active power dissipation is 525 mW while the maximum standby power dissipation is only 132 mW, a
75% savings.

The 2716 has the simplest and fastest method yet devised for programming EPROMs - single ou'se TTL level programming
No need for high voltage pulsing because all programming controls are handled by TTL signals. Program any location at any
time-either individually, sequentially or at random, vrth the 2716'* single address location programming. Total programming
time for all 16.384 bits is only 100 seconds.

■ Fast Access Time

— 350 ns Max. 27161

— 390 ns Max. 2716-2

— 450 ns Max. 2716

— 490 ns Max. 2716-5

— 650 ns Max. 2716-6

■ Single + 5V Power Supply

■ Low Power Dissipation

— 525 mW Max. Active Power

— 132 mW Max. Standby Power

PIN CONFIGURATION

2716

2732*

tRefer to 2732
data sheet for
specifications

PIN NAMES

G«

CAjirut

OjfHj IS

MODE SELECTION

tins

Moot

Oaom

1241

vcc

ti*

OUTHJJt
ft It. 13171

v lt

v *

•»

Ji**e>*

V|N

Do«‘iCif«

•i

hryr

v, t IO V (H

V|N

•s

Vf**S

v.t

v k>

•»

CojT

*'09

v a

V.H

•n

•i

BLOCK OIAGRAM

y tt » l - OC Of

2716

PROGRAMMING

The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section.

Absolute Maximum Ratings*

Temperature Under Bias..-10° C to♦80°C

Storage Temperature .-65° C to +125°C

All Input or Output Voltages with

Respect to Ground.+6V to -0.3V

Vpp Supply Voltage with Respect

to Ground During Program.♦26.5V to -0.3V

• COMMENT: Stresses above thole listed under "Absolute Maxi¬
mum Rating*" may cause permanem damage to the device. This is a
stress rating only and function*' operation of the device at these or
any other conditions above those indicated in the operational sec¬
tions of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.

DC and AC Operating Conditions During Read

2716

2716-1

2716-2

2716-5

2716-6

Temperature Range

0°C - 70°C

JEMm

O^C — 70° C

0°C - 70°C

Vcc Power SupplyM-2)

5V±5%

5V ±10%

5 V ±5%

5V ±5%

Vpp Power Supply^ 2 )

V CC

Vcc

READ OPERATION

D.C. and Operating Characteristics

Symbol

Parameter

Limits

Unit

Conditions

Min.

Typ. 131

Max.

’Ll

Input Load Current

V, N - 5.25V

Output Leakage Current

Vqut - 5.25V

Ipft®

Vpp Current

Vpp - 5.25V

Icci 121

Vcc Current (Standby)

CE- v, h .5£- V, l

'CCJ 121

Vcc Current (Active)

100

OT -CF- V, L

V,L

Input Low Voltage

-0.1

0.8

V |H

Input High Voltage

2.0

Vcc +1

V OL

Output Low Voltage

0.45

Iol * 2.1 mA

Vqh

Output High Voltage

2.4

•oh “ -400 pA

NOTES: 1. Vcc must be aoplied simultaneously or before Vpp and removed simultaneously or after Vpp.

2. Vpp mey be connected directly to Vcc exceot during programming. The supply current would then be the sum of Ice •PPI-

3. Typical values are for T A • 25'C and nominal supply voltages.

4. This parameter is only sampled end «$ not 100% tested.

Typical Characteristics

ICC CURRENT

Via

0 >! K K 40 W to >0 $0

TfMMAATvAt I Cl

ACCESS TIME
vs.

CAPACITANCE

0 *00 M )» 400 *» «• too

Cl if#»

ACCESS TIME
Vie

TEMPERATURE
m

0 >*203040*010**0

Vt%»t*Alvflt I C»

240 APPENDIX C

Copyrighted material

2716

A.C. Characteristics

Svmboi

Parameter

Limits (ns)

Ta*t

Conditions

2716

Min. Max.

2715-1

Min. Max.

2716-2

Mm. Max.

2716-5

1 Min. Max.

2716-6

Min. Max.

*ACC

Address to Output C* ay

450 i

390

450

ce«oT-v il

tCE

CE to Output Delay

450

350

390

490

650

0?-V, t

t 0 E

Output Enab'e to Output Oelay

120

160

200

CE-V il

'OF

Output Enable H*gh to Output Float

0 100

0 UX)

«-v, t

‘oh

Output Hold from Addresses. CE or
ST Whichever Occurred First

£T-CT-v, L

Capacitance 141 T A - 25°C. f - 1 MHz

Symbol

Parameter

Typ.

Max.

Unit

Conditions

C|N

Input Capacitance

V W * OV

CquT

Output Capacitance

Vqut * OV

A.C. Test Conditions:

Output Load: 1 TTl gate and C L * 100 pF
Input Rise and Fall Times: <20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs IV and 2V
Outputs 0.8V and 2V

A. C. Waveforms Ml

NOTE

1. Vcc must P* apoiied simultaneously or before Vpp and removed simultaneously Oi after Vpp.

2. Vpp may be connected directly to Vqc except during programming. The Supply current would then bt the sum of Ice «nd Ippi.

3. Typvcal values are for T A - 25* C and nominal supply voltages.

4. This parameter it only aam pla d and la not 100% tested.

5. OE may C« delayed up to t A cc - 'OE eher tn * 0 f CE without impact on t A cc-

6. tpp Is specified from OE or CE. whichever occur* first.

APPENDIX C 241

Copyrighted material

2716

ERASURE CHARACTERISTICS

OUTPUT OR-TIEING

The erasure characteristics of the 2716 are such that erasure
begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level fluorescent
lighting could erase the typical 2716 in approximately 3
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the 2716 is to
be exposed to these types of lighting conditions for ex¬
tended periods of time, opaque labels are available from
Intel which should be placed over the 2716 window to
prevent unintentional erasure.

The recommended erasure procedure (see Data Catalog
PROM/ROM Programming Instruction Section) for the
2716 is exposure to shortwave ultraviolet light which has
a wavelength of 2537 Angstroms (A). The integrated dose
(i.e.. UV intensity X exposure time) for erasure should be
a minimum of 15 W-sec/cm 2 . The erasure time with this
dosage is approximately 15 to 20 minutes using an ultra¬
violet lamp with a 12000 pW/cm 2 power rating. The 2716
should be placed within 1 inch of the lamp tubes during
erasure. Some lamps have a filter on their tubes which
should be removed before erasure.

DEVICE OPERATION

The five modesof operation of the 2716 are listed in Table
I. It should be noted that all inputs for thefive modesare at
TTt levels. The power supplies required are a +5V V^c and
a Vpp. The Vpp power supply must be at 25V during the
three programming modes, and must be at 5V in the other
two modes.

TABlf I MOO€ S€ LECTION

rmt

Moot

CC.tCM

CK1

vto

(111

v cc

1*41

OUTtUTft
itit.ui n

V H

•ft

•4

Coot

V IH

&»• iC*f

•S

•4

****

V| C »V| H

*|N

•6

Oi*

troy** V»<«V

VlL

vit

•ft

°Cmi

VlL

VfH

•n

•ft

* rt

READ MODE

The 2716 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output
pins, independent of device selection. Assuming that
addresses are stable, address access time (tAccI »* equal to
the delay from Cl to output (tee). Data is availablejt
the outputs 120_ns (toe) ah®' t h ® falling edge of OE.
assuming that CE has been low and addresses have been
stable for at least tACC — *OE*

STANDBY MODE

The 2716 has a standby mode which reduces the active
power dissipation by 75%. from 525 mW to 132 mW. The
2716 is placed in the standby mode by applying a TTL high
signal to the CE input. When in standby mode, the outputs
are in a high impedence state, independent of the OE input.

Because 2716*s are usually used in larger memory arrays.
Intel has provided a 2 line control function that accomo¬
dates this use of multiple memory connections. The two
line control function allows for:

a) the lowest possible memory power dissipation, and

b) complete assurance that output bus contention will
not occur.

To most efficiently use these two control lines, it is recom¬
mended that Cl (pin 18) be decoded and used as the
primary device selecting function, while 51 (pin 20) be
made a common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their
low power standby mode and that the output pins are only
active when data is desired from a particular memory
device.

PROGRAMMING

Initially, and after each erasure, all bits of the 2716 are in
the "1" state. Data is introduced by selectively program¬
ming "0's" into the desired bit locations. Although only
"0V will be programmed, both "IV and "0V can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.

The 2716 is in the programming mode when the Vpp power
supply is at 25V and OE is at V| H . The data to be pro¬
grammed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.

When the address and data are stable, a 50^msec, actrve
high, TTL program pulse is applied to the CE/PGM input.
A program pulse must be applied at each address location
to be programmed. You can program any location at any
time — either individually, sequentially, or at random.
The program pulse has a maximum width of 55 msec. The
2716 must not be programmed with a DC signal applied to
the CE/PGM input.

Programming of multiple 2716s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the paral¬
leled 2716s may be connected together when they are pro¬
grammed with the same data. A high level TTL pulse
applied to the CF/PGM input programs the paralleled
2716s.

PROGRAM INHIBIT

Programming of multiple 2716s in parallel with different
data is also easily accomplished. Except for Cl/PGM, all
like inputs (including OE) of the parallel 2716s may be
common. A TTL level program poise applied to a 2716's
CE/PGM input with Vpp at 25V will program that 2716.
A low level CE/PGM input inhibits the other 2716 from
being programmed.

PROGRAM VERIFY

A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify
may be performed wth Vpp at 25V, Except during pro¬
gramming and program verify. Vpp must be at 5V.

242 APPENDIX C

Copyrighted material

Appendix C3

iny*

2102A, 2102AL/8102A-4*
IK x 1 BIT STATIC RAM

P/N

Standby Pwr.
(mW)

Operating Pwr.
(mW)

Access

(ns)

2102AL-4

174

450

2102AL

174

350

2102AL-2

342

250

2102A-2

—

342

250

2102A

—

289

350

2102A-4

289

450

■ Single ->-5 Volts Supply Voltage

■ Directly TTL Compatible: All
Inputs and Output

■ Standby Power Mode (2102AL)

■ Three-State Output: OR-Tie
Capability

■ Inputs Protected: All Inputs
Have Protection Against Static
Charge

■ Low Cost Packaging: 16 Pin
Dual-In-Line Configuration

The Intel® 2102A is a high speed 1024 word by one bit static random access memory element using N-channel MOS devices
integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to
operate. The data is read out nondestructively and has the same polarity as the input data.

The 2102A is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing are
important design objectives. A low standby power version (2102AL) is also available. It has all the same operating
characteristics ol the 2102A with the added feature of 35m Wmaximum power dissipation in standby and 174m Win operations.

It is directly TTL compatible in all respects: Inputs, output, and a single >5 volt supply. A separate chip enable (CE) lead allows
easy selection of an individual package when outputs are OR-tied.

The Intel® 2102A is fabricated with N-channel silicon gate technology. This technology allows the design and production of
high performance easy to use MOS circuits and provides a higher functional density on a monolithic chip than either
conventional MOS technology or P-channel silicon gate technology.

CONFIGURATION LOGIC SYMBOL

BLOCK DIAGRAM

*. c

-'u

—

PIN NAMES

A i c

3 S -

OATA

*/Y* C

3S “

A**,

AOOfttSS iwnits

<hC

d n —

R£AO.*RlT£ IH*JT

a,C

I) DATA OUT

A 4

CHIMNA8U

a,C

g OATA IN _

*7 °OUT

—

®OVT

OATA OUTPUT

*. r

#*•<

3 Vcc -

A #

v ec

POffCR ••tvi

*9 C

J GVO

C£

TRUTH TABLE

ft*r

_^OUT

Moot

HIGH 2

NOTSECCCTIO

WRIT! -cr

WRlTC T

Rf AO

•All 8102A-4 ^pacification* ara Identical to th« 2102A-4 apeciilcallona.

APPENDIX C 243

Copyrighted material

2102A FAMILY

Absolute Maximum Ratings*

Ambient Temperature Under Bias -10°C to 80°C
Storage Temperature -65°C to +150°C

Voltage On Any Pin

With Respect To Ground -0.5V to +7V
Power Dissipation 1 Watt

•COMMENT:

Stresses above those listed under "Absolute Maximum Rating"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
at any other condition above those indicated in the opera*
tional sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

D. C. and Operating Characteristics

Ta ■ 0°C to 70° C, Vcc ■ 5V £5% unless otherwise specified.

Symbol

Ptnmettr

2102A, 2102A-4
2102AL. 2102AL4
Limits

Min. Typ.W Max.

2102A-2.2102AL-2
Limits

Min. Typ.ni Max.

Unit

Test Conditions

‘u

Input Load Current

1 10

V IN - 0 to 5.25V

f LOH

Output Leakage Current

1 5

£E • 2.0V.

v OVT * v 0H

•lol

Output Leakage Current

-1 -10

£5 • 2.0V,

V 0 UT " 0.4V

•cc

Power Supply Current

33 Note 2

45 65

All Inputs* 5.25V.
Oata Out Open.

T a * 0°C

V.L

Input Low Voltage

-0.5 0.8

V|H

Input High Voltage

2.0 V cc

V 0 L

Output Low Voltage

0.4

•OL * 2.1mA

Vqh

Output High Voltage

2.4

•oh ■ -100pA

Notts 1. Typical values art for Ta • 25°C and nominal supply voltage.

2. Tht maximum l^c value •* 55mA for the 2102A and 2102A-4. and 33mA for the 2102AL and 2102AL-4.

Standby Characteristics 2102AL. 2102AL 2, and 2102AL-4 (Available only in the Plastic Package)

T a - 0°C to 70°C

Symbol

Parameter

2102AL. 2102AL-4

Limits

Min. Typ.W Max.

2102AL-2

Limits

Min. Typ.Hl Max.

Unit

Test Conditions

Vpo

Vcc ' n Standby

1.5

V CES 121

CE Bias in Standby

2.0

2.0V<V PO <VccMax.

Vpo

1.5V<V P0 < 2.0V

•poi

Standby Current

15 23

20 28

All Inputs* V P01 » 1.5V

! PD2

Standby Current

20 30

25 38

All Inputs* Vp 0 2 * 2.0V

tCP

Chip Deselect to Standby Time

tR l3I

Standby Recovery Timt

tRC

STANDBY WAVEFORMS

NOTES.

1. Typical valuti are for T A ■ 25° C.

2. Consider tnt ten conditions at shown: If tht stand-
by voltage IVp^l .» between 5.25V IVcc Max.) and
2 0V. then CE mutt be h«id at 2.0V Mm. (V !H I. >»
tht ttandby voltage *s its* than 2 0V but grtattr than
1.5V iVpQ Min.), than £1 and standby voltage
mutt be at lean the tame value or. if they are dif•
ftrent. Cl mutt be th* more positive of the two.

3 tR ■ ir C «REAO CYCLE TIME).

244 APPENDIX C

Copyrighted material

2102A FAMILY

A. C. Characteristics T a * 0°C to 70°C, v cc = 5V ±5% unless otherwise specified

REAO CYCLE

Symbol

Parameter

2102A-2, 2102AL-2
Limits (ns)

Min. Max.

2102A, 2102AL
Limits (ns)

Min. Max.

2102A-4,2102AL-4
Limits (ns)

Min. Max.

tRC

Read Cycle

250

350

450

Access Time

250

350

450

too

Chip Enable to Output Time

130

180

230

tom

Previous Read Data Valid with
Respect to Address

tOH2

Previous Read Data Valid with
Respect to Chip Enable

WRITE CYCLE

twe

Write Cycle

250

350

450

tAW

Address to Write Setup Time

twp

Write Pulse Width

180

250

300

tWR

Write Recovery Time

*DW

Data Setup Time

180

250

300

<DH

Data Hold Time

*cw

Chip Enable to Write Setup

Time

180

250

300

A.C. CONDITIONS OF TEST

Input Puli* L»v#l»: 0.8 Volt to 2.0 Volt

Input Rite end Fell Times: lOnsec

Timing Measurement Inputs: 1.5 Volts

Reference Levels Output: 0.8 and 2.0 Volts

Output Load: 1 TIL Gate and Cl • 100 pF

Capacitance 121 t a -25°c, f*iMHz

SYMBOL

TEST

LIMITS (pF) |

TYP.ll)

MAX.

C IN

INPUT CAPACITANCE
(ALL INPUT PINS) V IN »0V

C OUT

OUTPUT CAPACITANCE
Vqut - 0V

Waveforms

READ CYCLE

WRITE CYCLE

S o a volts

NOTES: 1. Typical values are for T A - 25*C and nominal supply voltage.

2. This parameter is period Kelly sampled and is not 100% tested.

APPENDIX C 245

Copyrighted material

2102A FAMILY

Typical D. C. and A. C. Characteristics

POWER SUPPLY CURRENT VS.
AMBIENT TEMPERATURE

POWER SUPPLY CURRENT VS.

1 2 3 4 5 6

IVOLTSI

V, N LIMITS VS. TEMPERATURE

0 tO 20 30 40 50 40 70

T 4 <*C)

OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE

ACCESS TIME VS.
AMBIENT TEMPERATURE

ACCESS TIME VS.
LOAD CAPACITANCE

30 40

\rc>

246 APPENDIX C

Copyrighted material

Appendix C4

iny

2114A

1024 X 4 BIT STATIC RAM

2114AL-1

2114AL-2

2114AL-3

2114AL-4

2114A-4

2114A-5

Max. Access Time (ns)

100

120

150

200

250

Max. Current (mA)

■ HMOS Technology

■ Low Power, High Speed

■ Identical Cycle and Access Times

■ Single +5V Supply ±10%

■ High Density 18 Pin Package

■ Completely Static Memory - No Clock
or Timing Strobe Required

■ Directly TTL Compatible: All Inputs
and Outputs

■ Common Data Input and Output Using
Three-State Outputs

■ 2114 Upgrade

The Intel* 2114A is a 4098-bit static Random Access Memory organized as 1024 words by 4-bits using HMOS. a high per¬
formance MOS technology. It uses fully DC stable (static) circuitry throughout. In both the array and the decoding, therefore It
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
data is read out nondestructive^ and has the same polarity as the input data. Common input/output pins are provided.

The2114A is designed for memory applications where the high performance and high reliability of HMOS. low cost, large bit
storage, and simple interfacing arc important design objectives. The 2114A is placed in an 18 -pin package for the highest
possible density.

It Is directly TTL compatible In all respects: Inputs, outputs, and a single «SV supply. A separate Chip Select (£S) lead allows
easy selection of an individual package when outputs are or-tled.

PIN CONFIGURATION LOGIC SYMBOL

BLOCK DIAGRAM

PIN NAMES

A.-A, ADDRESS INPUTS

V cc POWER |*5V)

WE WRITE ENABLE

GNOGROUNO

£3 CHIP SELECT

l/0,-l/0 4 DATA INPUT ^OUTPUT

ROW

SftfCT

•

M€MORTARRAY

•

U ROWS

*4 COLUMNS

•

> i

_ 1 _ 1 _

r*#ur

OATA
CONTROL

COLUMN i/O CIRCUITS
COLUMN $4tier

GNO

O *\N MUMtCRS

APPENDIX C 247

Copyrighted material

2114A FAMILY

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias.-10°C to 80° C

Storage Temperature.-S5*C to 150®C

Voltage on any Pin

With Respect to Ground.-3.5V to +7V

Power Dissipation.1.0W

D.C. Output Current.5mA

COMMENT: Stresses above those listed under *Absolute
Maximum Ratings" may cause permanent damage to the device.
This Is a stress rating only and functional operation of the device
at these or any other conditions above those Indicated In the
operational sections of this specification is not Implied. Ex¬
posure is not Implied. Exposure to absolute maximum rating
conditions lor extended periods may affect device reliability.

D.C. AND OPERATING CHARACTERISTICS

Ta * 0*C to 70®C, Vex = 5V ± 10%. unless otherwise noted.

SYMBOL

PARAMETER

2114AL-1/L-2/L-3/L-4
Min. Typ.nl Max.

2114A-4/-5

Min. Typ.lil Max.

UNIT

CONDITIONS

Ili

Input Load Current
(All Input Pins)

V, N • 0 to 5.5V

&LOl

I/O Leakage Current

c3« V, M

V| /0 * GND to VCC

•cc

Power Supply Current

25 40

50 70

Vcc * max, l|/o ■ 0 mA,

Ta - 0°C

VlL

Input Low Voltage

-3.0 0.8

V| H

Input High Voltage

2.0 6.0

>OL

Output Low Current

21 9.0

2.1 9.0

V 0 L - 0.4V

•oh

Output High Current

-1.0 -2.5

Vqh " 2.4V

*0S« 2 I

Output Short Circuit
Current

NOTE: 1. Typical value*are for T^ • 2S*Car>d Vqc * 5.0V.
2. Duration not to excaed 30 aeconds.

CAPACITANCE
T a ■ 25* C, f - 1.0 MHz

SYMBOL

TEST

MAX

UNIT

CONDITIONS

c l/0

Input/Output Capacitance

V„o - ov

C|N

Input Capacitance

V,N " OV

NOTE: Thit paramatar it periodically ampled and not 100% testod.

A.C. CONDITIONS OF TEST

Input Pulse Levels.

Input Rise and Fall Times.

Input and Output Timing Levels ....
Output Load.

.0.8 Volt to 2.0 Volt

. 10 nsec

.1.5 Volts

1 TTL Gate and C L * 100 pF

243 APPENDIX C

Copyrighted material

2114A FAMILY

A.C. CHARACTERISTICS Ta ■ 0*C to 70°C, Vcc “ 5V ♦ 10%. unless otherwise noted.

READ CYCLE 111

SYMBOL

PARAMETER

2114AL-1

Min. Max.

2114AL-2

Min. Max.

2114AL-3

Min. Max.

2114A-4/L-4

Min. Max.

2114A-5

Min. Max.

UNIT

tec

Read Cycle Time

100

120

150

200

250

Access Time

100

120

150

200

250

tco

Chip Selection to Output Valid

tea

Chip Selection to Output Active

tOTO

Output 3-state from Deselection

tOMA

Output Hold from

Address Change

WRITE CYCLE (21

2114AL-1

2114AL-2

2114AL-3

2114A-4/L-4

2114A-5

SYMBOL

PARAMETER

Min. Max.

UNIT

twe

Write Cycle Time

too

120

150

200

250

Write Time

120

135

twR

Write Release Time

tOTW

Output 3-state from Write

tpw

Data to Write Time Overlap

120

135

ton

Data Hold from Write Time

NOTES _ _

1. A Raad occur* dunng th« overlap of • lowjCS and a hi gh W E

2 A Write occurs during tr>* ov*rl*p o< a low CS and a low WE it m#*sur#«J from |h# Utter o! C5 Or 771 go*ng low to the aarliar ot CS Of 771 going high.

WAVEFORMS

READ CYCLE®

WRITE CYCLE

* -

T- U ]

AOORCtS

a vWWWWWWWWWSv_

U . ko— U— k*o—H

r* —k»— H

•- B - dr-

NOTES:

3. 7HT u high *or * Read Cycle.

4. It the Cs low transition occurs slcroltaneously with the wl low
^transition, the output t>uff*rs remain in a high >mp«dance state.

5. wT must do high dunng an address tramitons.

ao cat is

Pout

/ J y f f T' J T7'7 7 ) Tf

11! ill / / J1 lli

BssaB B

APPENDIX C 249

Copyrighted material

Appendix C5

intel

8212

8-BIT INPUT/OUTPUT PORT

■ Fully Parallel 8-Bit Data Registerand Buffer ■ 3.65V Output High Voltage for

■ Service Request Flip-Flop for Direct Interface to 8008, 8080A, or

Interrupt Generation 8085A CPU

■ Low Input Load Current - .25mA Max. ■ Asynchronous Register Clear

■ Three State Outputs ■ Replaces Butlers, Latches and

■ Outputs Sink 15mA Multiplexers in Microcomputer Systems

■ Reduces System Package Count

The 8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection
logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor.

The device is multimode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the
principal peripheral and input/output functions of a microcomputer system can be implemented with this device.

PIN CONFIGURATION LOGIC DIAGRAM

APPENDIX C 251

Copyrighted material

8212

FUNCTIONAL DESCRIPTION
Data Latch

The 8 flip-flops that make up the data latch are of a "D"
type design. The output (Oi of the flip-flop will follow the
data input (Dl while the clock input (Cl is high. Latching
will occur when the clock (C) returns low.

The la tche d data is cleared by an asynchrono us re set
Input (CLR). (Note: Clock (C) Overrides Reset (CLR). I

Output Buffer

The outputs of the data latch |Q) are connected to3-stato,
non-inverting output buffers. These buffers have a
common control line (EN); this control line either enables
the buffer to transmit the data from the outputs of the data
latch (Q) or disables the buffer, forcing the output into a
high impedance state. (3-statel

The high-impedance state allows the designer to connect
the 8212 directly onto the microprocessor bi-directional
data bus.

Control Logic

The 8212 has control inputs DS1. OS2. MD and STB.
These inputs are used to control dovice selection, data
latching, output buffer state and service request flip-flop.

DS1, DS2 (Device Select)

These 2 inputs are used for device selection. When DS1 is
low and DS2 is high (OS1 * DS2) the device is selected. In
the selected state the output buffer is enabled and the
service request flip-flop iSR) is asynchronously set.

MD (Mode)

This input is used to control the state of the output buffer
and to determine the source of the clock input (C) to the
data latch.

When MD is high (output mode) the output buffers are
enabled and the source of dock (jC) to the data latch is
from the device selection logic <5sl * DS2).

When MD is low (Input model the output buffer state is
determined by the device selection logic (DS1 • DS2) and
the source of clock (C) to the data latch is the STB
(Strobe) input.

STB (Strobe)

This input is used as the clock (C) to the data latch for the
Input mode MD » 0) and to synchronously reset the
service request flip-flop (SR).

Note that the SR flip-flop is negative edge triggered.

Service Request Flip-Flop

The (SR> flip-flop is used to generate and control
interrupts in m icro computer systems. It is asynchron¬
ously set by the CLR input (active low). When the (SR) flip-
flop is set it is in the non-interrupting state.

The output of the (SR» flip-flop (Q) Is connected to an
inverting input of a "NOR" gate. The other input to tho
"NOR" gate is non-inverting and is connected to the
device seiectionjogic (DS1 • DS2). The output of the
"NOR" gate (INT) is active low (interrupting state) for
connection to active low input priority generating circuits.

SCRVICl RtOUtST ft

; sum*

UVSSft

l*OIM«CTO*OUtfVTSU##l*l

8212

Applications of the 8212 — For
Microcomputer Systems

I Basic Schematic Symbol

II Gated Buffer

III Bi-Directional Bus Driver

IV Interrupting Input Port

1. Basic Schematic Symbols

Two examples of ways to draw the 8212 on system
schematics — (1 > the top being the detailed view showing
pin numbers, and (2) the bottom being the symbolic view

V Interrupt Instruction Port

VI Output Port

VII 8080A Status Latch

VIII 80S5A Address Latch

showing the system input or output as a system bus (bus
containing 8 parallel lines). The output to the data bus is
symbolic in referencing 8 parallel lines.

252 APPENDIX C

Copyrighted material

BASIC SCHEMATIC SYMBOLS

INnjT DEVICE

OUTPUT DEVICE

(DETAILED)

iswaonci

II. Gated Buffer (3-State)

GATED BUFFER

The simplest use of the 8212 is that of a gated buffer. By
tying the mode signal low and the strobe Input high, the
data latch is acting as a straight through gate. The output
buffers are then enablod from the device selection logic
OS1 and DS2.

When the device selection logic is false, the outputs are 3-
state.

When the device selection logic is true, the input data from
the system is directly transferred to the output. The input
data load is 250 micro amps. The output data can sink 15
milli amps. The minimum high output is 3.65 volts.

output

DATA

(15mA)

(3 65V MIN)

8212

III. BI-DIrectlonal Bus Driver

BI-DIRECTIONAL BUS DRIVER

A pair of 8212's wired (back-to-back) can be used as a
symmetrical drive, bi-directional bus driver. The devices
are controlled by the data bus input control which is
connected to 6£i on the first 8212 and to DS2 on the
second. One device is active, and acting as a straight
through buffer the other is In 3-state modo. This is a very
useful circuit in small system design.

v ce

OATA
8 US

APPENDIX C 253

Copyrighted material

IV. Interrupting Input Port

INTERRUPTING INPUT PORT

This use of an 8212 is that of a system Input port that
accepts a strobe from the system input source, which in
turn clears the service request flip-flop and interrupts the
processor. The processor then goes through a service
routine. Identifies the port, and causes the device
selection logic to go true — enabling the system input data
onto the data bus.

DATA

TO PRIORITY CAT
I ACTIVE LOW

TO CPU

INTERRUPT INPUT

V. Interrupt Instruction Pori

The 8212 can be used to gate the interrupt Instruction,
normally RESTART instructions, onto the data bus. The
device is enabled from the interrupt acknowledge signal
from tho microprocessor and from a port selection signal.
This signal is normally tied to ground. (DS1 could be used
to multiplex a variety ot interrupt instruction ports onto a
common bus).

INTERRUPT INSTRUCTION PORT

V CC DATA

8212

VI. Output Port (With Hand-Shaking)

OUTPUT PORT (WITH HAND-SHAKING)

The 8212 can be used to transmit data from the data bus to
a system output The output strobe could be a hand¬
shaking signs! such as 'reception of data" from the device
that the system is outputting to. It in turn, can interrupt the
system signifying the reception of data. The selection of
the port comes from the device selection togic.iDSl • DS2i

DATA

BUS

SYSTEM
INTI RRUPT

OUTPUT STROBE

SYSTEM OUTPUT

SYSTEM RESET

1 PORT SELECTION
f- (LATCH CONTROL)

J idSvOW)

254 APPENDIX C

Copyrighted material

VII. 6080A Status Latch

Here the 8212 is used as the status latch for an 8080A
microcomputer system. The input to the 8212 latch is
directly from the 8080A data bus. Timing shows that when
the SYNC signal is true, which is connected to the DS2
input and the phase 1 signal is true, which is a TTL level
coming from the clock generator; then, the status data will
be latched into the 8212

Note: The mode signal is tied high so that the output on the
latch is active and enabled all the time.

It is shown that the two areas of concern are the bi¬
directional data bus of the microprocessor and the control
bus.

°o

D«

DATA BUS

INTA

WO
STACK j
HIT A
OUT
Ml
INP
MEMR

BASIC
CONTROL
BUS

SYNC

OBIS

PATA

STATUS

8212

VIII. 8085A Low-Order Address Latch

The 8085A microprocessor uses a multiplexed address/
data bus that contains me low order 8-bits of address
Information during the first part of a machine cycle The
same bus contains data at a lator time in the cycle An
address latch enable (ALE) signal is provided by the
8085A to be used by the 8212 to latch the address so that it
may be available through the whole machine cycle Note;
In this configuration, the MODE input is tied high, keeping
the 8212 s output buffers turned on at all times.

0 2

d 3

d 4

d 5

0 6

0 7

a 2

A 3

a 7

h DATA BUS

LOW ORDER
AODRESSBUS

APPENDIX C 255

Copyrighted material

ABSOLUTE MAXIMUM RATINGS

Temperature Undor Bias Plastic . 0*C to *70*C

Storage Temperature . -65°C to +160°C

All Output or Supply Voltages . -0 5 to +7 Volts

All Input Voltages . -1.0 to 5.5 Volts

Output Currents . 100mA

•comment

Svcsses abovf new luted under "Absolute Maumum Ribngi* may c ause
damage to the device TtU$ u a stress rating only and Junction*!
operation o! the device at ihese or any otner conations above those
indicated m me operational sections or IMS specification .» not implied
E*posure to absolute ma*imum rating conditions lor emended periods
may attect device reliability

D.C. CHARACTERISTICS Ta - o*c to +75*c. Vcc - +sv ±5%

Symbol

Limits

Unit

T pel CnnHillnnt

rflrimtltr

Min.

Typ.

Max.

unit

1 hi Lonaiiioni

Input Load Current. ACK. DS 2 . CR.
DI 1 -DI 9 Inputs

-.25

Vf = 45V

Input Load Current MD Input

-.75

Vf • .45V

Input Load Current OSi Input

- 1.0

Vf = 45V

Input Leakage Current. ACK. OS. CR.
Dlt-DIa Inputs

m a

Vr < Vcc

Input Leakage Current MO Input

Vr £ Vcc

Input Leakage Current OSi Input

Vr < Vcc

Input Forward Voltage Clamp

-1

lc = -5mA

VlL

Input “Low" Voltage

.85

VlH

Input "High" Voltage

2.0

VOL

Output "Low" Voltage

.45

lot = 15mA

Vom

Output "High" Voltage

3 65

4.0

low » - 1 mA

isc

Short Circuit Output Current

-15

-75

Vo = 0 V. Vcc - 5V

noi

Output Leakage Current High
Impedance State

Vo = 45V/5.25V

Icc

Power Supply Current

130

8212

TYPICAL CHARACTERISTICS

INPUT CURRENT VS. INPUT VOLTAGE

OUTPUT CURRENT VS. OUTPUT -LOW* VOLTAGE

OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE

OATA TO OUTPUT DELAY
VS. LOAO CAPACITANCE

256 APPENDIX C

Copyrighted material

DATA TO OUTPUT OELAY
VS. TEMPERATURE

TtWPfftATlM((C>

WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE

8212

A.C. CHARACTERISTICS Ta = o°C to +70*C. Vcc = +5V ± 5%

Symbol

Parameter

Limit#

Unit

Test Conditions

Min.

Typ.

Max.

tpw

Pulse Width

tPD

Data to Output Dolay

Note 1

twE

Write Enable to Output Delay

Note 1

tSET

Data Set Up Time

Data Hold Time

Reset to Output Delay

Note 1

Set to Output Delay

Note 1

t£

Output Enable/Disable Time

Note 1

Clear to Output Delay

Note 1

CAPACITANCE* F » 1 MHz. V&as b 2.5V. Vcc - +5V. Ta = 25 e C

Symbol

Te«t

Limit*

Typ. Max.

C.N

DSt MD Input Capacitance

9pF l2pF

ClN

DS2. CK. ACK. Dli-DIa

Input Capacitance

5pF 9pF

COUT

DOi-DOa Output Capacitance

8 pF 12pF

•This parameter (a sampled and not 1C0% lostcd.

SWITCHING CHARACTERISTICS

Condition* ot Teat

Input Pulse Amplitude » 2.5V

Input Rise and Fall Times 5ns

Between IV and 2V Measurements made at 1.5V

with 15mA and 30pF Test Load

Note 1:

T#*»

Cl*

tPD. twE. In. ts. tc

30pF

30on

600n

t E . ENABLE1

30 pF

10KH

iKn

IE. ENABLE l

30pF

3oon

soon

t£. DISABLE?

5pF

3oon

eoon

te. DISABLE!

5pF

iOKn

iKn

•Includes probe and jig capacitance.

Test Load

15mA & 30pF

•INCLUDING JIG & PROBE CAPACITANCE

APPENDIX C 257

Copyrighted material

258 APPENDIX C

Appendix C6

STANDARD MICROSYSTEMS
CORPORATION^

,. U|OjS&V3 Kxjcobuj? **

TW* 5*0 2& 9H9

we keep ahead of our competition so you can keep ahead of yours

KR2376-XX

Keyboard Encoder Read Only Memory

FEATURES

□ Outputs directly compatible with TTLyDTL or
MOS logic arrays.

□ External control provided for output polarity
selection.

□ External control provided for selection of odd

or even parity.

□ Two key roll-over operation.

□ N-key lockout.

□ Programmable coding with a single mask
change.

□ Self-contained oscillator circuit.

□ Externally controlled delay network provided
to eliminate the effect of contact bounce.

□ One integrated circuit required for complete
keyboard assembly.

□ Static charge protection on all input and
output terminals.

□ Entire circuit protected by a layer of glass
passivation.

PIN CONFIGURATION

VCC C

3 Frequency Control A

Fraqutncy CooifOl B C

3*o'|

F r#Qw*f>cy COAt'Ol C C

]X1

Snift input Q

3x2

Keyboard

Control Input C

3X3

Matrix

Pauly lnv*fT Input Q

3X4

Outputs

P«nlyOulput £

3*5

bait Output BB C

3*6

Data Output B* C

3 X7

Data Output 66 C

3 vo'I

Oata Output BB L

3 vi

Catj Output Ra f

3 V2

Oata Output B3 [

4 3

3V3

Data Output 0? C

3V4

Keyboard

Oata Output 0t £

3**

* Matrix

Stroba Output C

3 v «

Inputs

Grouna £

3V7

Voc. C

3 v ®

SlfOt* Control Input C

1®

3*®

Data & StroCc C

3viO;

Invert input

PACKAGE 40-Pin D.I.P.

GENERAL DESCRIPTION

The SMC KR2376-XX is a 2376-bit Read Only Memory
with all the logic necessary to encode single pole
single throw keyboard closures into a usable 9-bit
code Oata and strobe outputs are directly compatible
with TTL/DTl or MOS logic arrays without the use of

any special interface components.

The KR2376-XX is fabricated with low threshold.
P-channei technology and contains 2942 P-channel
enhancement mode transistors on a single monolithic
chip, available in a 40 pm dual-in-line package.

TYPICAL CONNECTION OF KR2376-XX

VO VI V? vs V4 vs V6 Y7 Y8 V9 Y-0

KR2JTS-XX

V*,

Vcc

1 7
1

SHIFT I^JT

COWTPC 4 INPUT
STROK

COWTPCC l* 4 =\/T 19

Vcc Vcc

CATA&STAOK »
*VfRT ISJPUT

PAPITY * 1
SWtRT I*JPUT

OCLAY

50 KM/
OSCILLATOR

parity output

1 TTLTDTljSAOS

J COMPAT^C OUTPUT c ttvens

f^T’O

14 1 is

’T

' T

M0TO6D5O4B3B2B1

✓

4 11 frT COMPARATOR l—l

CiOCK

CONTROL

| 11 STAGE RING COUNTER jl—

1 LL L 1.111 L

2376 fllT POM k—

STAGE

19 BIT i 88 KEYS » 3 UCOE>

PING

COUNTER

m— iiii— r-r-

CONTROL

t r

X 4

V10

66 SPST KEYBOARD SWTCHES
r0~ ~ Y1

* m* **

✓

TYPICAL SWfTCH

EXAMPLE

Fig. 1

DATA OUTPUTS

R1 f6*KO> Cl I COi*/l CTCNKH 1 S rm OtWy

wTicZkOi 4 !

rm 6 i

C7 «0ST) 30KK* CW IfXQu«ncy

MAXIMUM GUARANTEED RATINGS!

Operating Temperature Range.0°C to +70° C

Storage Temperature Range.-65° C to +150° C

GND and Vgg, with respect to Vcc.-20V to +0.3V

Logic Input Voltages, with respect to Vcc.-20V to +0.3V

t Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in
the operational sections of this specification is not implied.

ELECTRICAL CHARACTERISTICS

(Ta = 0° C to +70° C. Vcc = +5V ±0.5V, Vgg = -12V ±1.0V. unless otherwise noted)

Characteristics

Min

Typ

Max

Unit

Conditions

CLOCK

100

KHz

see fig.1 footnote (*•) for typical
R-C values

DATA INPUT

Logic "0" Level

+0.8

Logic "1" Level

Vcc-1.5

Input Capacitance

INPUT CURRENT

•Control. Shift &Y0
thru Y10

•Control. Shift &Y0

100

140

//A

Vin = +5.0V

thru Y10

/lA

Vin = Ground

Data Invert. Parity Invert

DATA OUTPUT & X OUTPUT

.01

Vin = -5.0V to +5.0V

Logic "0" Level

+0.4

Iol = 1.6mA (see fig. 7)

Logic "1“ Level

Vcc-10

Ioh = 100 jjA

POWER CONSUMPTION

140

200

Norn. Power Supp. Voltages
(see fig. 8)

SWITCH CHARACTERISTICS

Minimum Switch Closure

see timing diagram-fig. 2

Contact Closure Resistance
between XI and Y1

Contact Open Resistance

300

Ohm

between XI and Y1

1 xl0 r

Ohm

•Inputs with Internal Resistor to Vgg

DESCRIPTION OF OPERATION

The KR2376-XX contains (see Fig. 1). a 2376-bit
ROM. 8-stage and 11-stage ring counters, an 11-bit
comparator, an oscillator circuit, an externally
controllable delay network for eliminating theeffect
of contact bounce, and TTL/DTL/MOS compatible
output drivers.

The ROM portion of the chip is a 264 by 9-bit
memory arranged into three 88-word by 9-bit
groups. The appropriate levels on the Shift and
Control inputs selects one of the three 88-word
groups; the 88-individual word locations are
addressed by the two ring counters. Thus, the ROM

address is formed by combining the Shift and
Control Inputs with the two ring counters.

The external outputs of the 8-stage ring counter
and the external inputs to the 11-bit comparator are
wired to the keyboard to form an X-V matrix with the
88-keyboard switches as the crosspoints. In the
standby condition, when no key is depressed, the
two ring counters are clocked and sequentially
address the ROM; the absence of a Strobe Output
indicates that the Data Outputs are ‘not valid' at
this time.

260 APPENDIX C

Copyrig-itcd ratcrial

When a key is depressed, a single path is completed
between one output of the 8-stage ring counter
(XO thru X7) and one input of the 11-bit comparator
(Y0-Y10). After a number of clock cycles, a condition
will occur where a level on the selected path to the
comparator matches a level on the corresponding
comparator input from the 11-stage ring counter.
When this occurs, the comparator generates a
signal to the clock control and to the Strobe Output
(via the delay network). The clock control stops the
clocks to the ring counters and the Data Outputs

(91-B9) stabilize with the selected 9-bit code,
indicated by a 'valid' signal on the Strobe Output.
The Data Outputs remain stable until the key is
released.

As an added feature two inputs are provided for
external polarity control of the Data Outputs. Parity
Invert (pin 6} provides polarity control of the Parity
Output (pin 7) while the Data and Strobe Invert
Input (pin 20) provides for polarity control of Data
Outputs B1 thru B8 (pins 8 thru 15) and the Strobe
Output (pin 16).

SPECIAL PATTERNS

Since the selected coding of each key is defined
during the manufacture of the chip, the coding can
be changed to fit any particular application of the
keyboard. Up to 264 codes of up to 8 bits (plus one
parity bit) can be programmed into the KR2376-XX

ROM covering most popular codes such as ASC11.
EBCDIC. Selectric. etc.aswellasmanyspecialized
codes. The ASCII code is available as a standard
pattern. For special patterns, use Fig. 9.

TIMING DIAGRAM

SWITCH

CtOSuftE

SWITCH

RELEASE

MAXIMUM C€TERV NFO OCTERVINCO BV MMMviU TlMt
EXPECTED BY FRECuENCY EXTCRNAl AC HEOmACO BY
OF OPERATION CXTCANAt

JEATEANAL AC) OACVlTAY

Fig. 2

POWER SUPPLY CONNECTIONS FOR
TTL/DTL OPERATION

-UV *SV On a

TTL/OTl
LOGIC OR
SMCLCW
VOLTAGE
UOS LOGIC

Vce

INPUTS

-■-*-*-

** 1 IT

WO'Wfi W

OUTPUTS

KRZj’b*XX

TTUOTl
LOGIC OR
SVC LOW
VOLTAGE
wOSlOOC

OUTPUT DRIVER & “X" OUTPUT STAGE

TO KEYBOARD

POWER SUPPLY CONNECTIONS FOR
MOS OPERATION

FROM HIGH OR
LOW VOLTAGE
MOS 0« TTl/DTl
RUCRENCCO
TO -SV

•17V

ON) , I

INPUTS

t$ 1 1?

OUTPUTS

TO HIGH
CR LOW
VOLTAGE
VOS

Fig. 3

Y" INPUT STAGE FROM KEYBOARD

Vco

KEVSOAPO >■
INPUT

INTERNAL

GATING

STATIC OARGE

PROTECTION DEYCC INPuT

Fig. 4

APPENDIX C 261

Copyrighted material

FLOW CHART—TRANSMITTER

FLOW CHART-RECEIVER

Circurt diagram* uMuing SMC product* are included at a mean* o« illustrating typical semiconductor applica¬
tions. consequently compete information aulfiCient tor construction purposes IS not necessarily frren The
information rat ocen carc'u >■ crocked and * believed to be entirety refeaWe However, no responsibility tt
assumed tor inaccuracies Furthermore, such mtormat-on does not convey 10 the Purchaser of the semiconductor
devices described any license under the patent rights ot SMC or others SMC reserves the nght to make changes
at any time in order to improve Oesign and supply the Pest product possible

APPENDIX C 269

Copyrighted material

Appendix C8

glANTO RI?MICROSYSTEMS
CORPORATION

W _

Hxkxj* NV11T87

. . ^ _ _ tS»273.Ji0lJ TWX.»277M»

we teep ahead of our competition so you can keep ahead of yours

CRT 5027
CRT 5037
CRT 5057’

CRT Video Timer and Controller

/U,PC FAMILY

VTAC®

FEATURES

□ Fully Programmable Display Format

Characters per data row (1-200)

Data rows per frame (1-64)

Raster scans per data row (1-16)

D Programmable Monitor Sync Format
Raster Scans/Frame (256-1023)

'•Front Porch"

Sync Width
"Back Porch"

Interlace/Non-Interlace
Vertical Blanking

□ Lock Line Input (CRT 5057)

□ Direct Outputs to CRT Monitor

Horizontal Sync
Vertical Sync

Composite Sync (CRT 5027, CRT 5037)

Blanking

Cursor coincidence

□ Programmed via:

Processor data bus
External PROM
Mask Option ROM

□ Standard or Non-Standard CRT Monitor Compatible
C Refresh Rate:60Hz.50Hz,...

□ Scrolling

Single Line
Multi-Line

C Cursor Position Registers
£ Character Format: 5x7,7x9....

£ Programmable Vertical Data Positioning
£ Balanced Beam Current Interlace (CRT 5037)

□ Graphics Compatible

PIN CONFIGURATION

A2C

l A1

A3 C

: A6

CSC

) H0

R3 C

1 Ml

R2 C

3fl

) H2

gnd

JM3

R1 t

)H4

Re c

JH5

OSE

1 M6

LLI/CSYN (

J M7/DR5

VSYN (

•

1 OR4

CCC [

) OR3

VDO(

J OR2

VCC E

3 DAI

MSYN C

3DRC

CRV t

3 D80

BL I

3D61

OB7C

3 082

oec C

0B3

OS5 £

3 0B4

PACKAGE: 40-Pin D.I.P

□ Split-Screen Applications

Horizontal

Vertical

O Interlace or Non-Interlace operation
C TTL Compatibility

□ BUS Oriented

□ High Speed Operation

□ COPLAMOS* N-Channel Silicon
Gate Technology

□ Compatible with CRT 8002 VDAC™

□ Compatible with CRT 7004

GENERAL DESCRIP TION

The CRT Video Timer and Controller Chip (VTAC)* isa user programmable 40-pin COPLAMOS* nchannel MOS/LSI
device containing the logic functions required to generate ail the timing signals for the presentation and formattmq of
interlaced and non-interlaced video data on a standard or non-standard CRT monitor.

With the exception of the dot counter, which may be clocked at a video frequency above 25 MHz and therefore not
recommended for MOS implementation, all frame formatting, such as horizontal, vertical, and composite sync, characters
per data row. data rows per frame, and raster scans per data row and per frame are totally user programmable. Thedatarow
counter has been designed to facilitate scrolling.

Programming is effected by loading seven8 bit control registersdirecttyoffanSbitbidirectionaldatabus.Fourregister
address lines and a chip select line prov.de complete microprocessor compatibility for program controlled set up The device

can be 'self loaded" v.aanextornalPROMtiedonthedatabusasdescr.bed in the OPERATION section. Formatting can also

be programmed by a single mask option.

In addition to the seven control registers two additional registers are provided to store the cursor character and data
row addresses for generation of the cursor video signal. The contentsof these two registers can also be read out onto the
bus for update by the program.

Throe versions of the vtac® are available. The CRT 5027 provides non-interlaced operation with an even or odd
number of scan lines per data row. or interlaced operation with an even number of scan lines per data row. The CRT 5037
may be programmed for an odd or even number of scan lines per data row in both interlaced and non-interlaced modes.
Programming the CRT 5037 for an odd number of scan lines per data row eliminates character distortion caused by the
uneven beam current normally associated with odd field/even field interlacing of alphanumeric displays.

The CRT 5057 provides the ability to lock a CRTs vertical refresh rate, as controlled by the VTAC's® vertical sync
pulse, to the 50 Hz or 60 Hz line frequency thereby eliminating the so called "swim" phenomenon. This is particularly
well suited for European system requirements. The line frequency waveform, processed to conform to the VTAC’s®
specified logic levels, is applied to the line lock input. The VTAC® will inhibit generation of vertical sync until a zero to
one transition on this input is detected The vertical sync pulse is then initiated within one scan line after this transition
rises above the logic threshold of the VTAC.®

To provide tne pin required for the line lock input, the composite sync output is not provided in the CRT 5057.

•FOR FUTURE RELEASE

APPENDIX C 271

Copyrighted material

Description of Pin Functions

Pin No.

Symbol

Name

Input/

Output

Function

25-18

DB0-7

Data Bus

I/O

Data bus. Input bus for control words from microprocessor or

PROM. Bidirectional bus for cursor address.

Chip Select

Signals chip that it is being addressed

39.40.1.2

A0-3

Address

Data Strobe

Strobes DB0-7 into the appropriate register or outputs the
cursor character address or cursor line address onto the data bus

DCC

DOT Counter

Carry

Carry from off chip dot countor establishing basic character
clock rate. Character clock.

38-32

H0-6

Character

Counter Outputs

Character counter outputs.

7.5.4

R1-3

Scan Counter

Outputs

Three most significant bits of the Scan Counter; row select
inputs to character generator.

H7/DR5

Pin definition is user programmable. Output is MSB of

Character Counter if horizontal line count (REG.0) is ^128;
otherwise output is MSB of Data Row Counter.

Scan Counter LSB

Least significant bit of the scan counter. In the inter¬
laced mode with an even number of scans per data row,

R0 will toggle at the field rate; for an odd number of
scans per data row in the interlaced mode. R0 will toggle
at the data row rate.

26-30

DR0-4

Data Row

Counter Outputs

Data Row counter outputs.

Blank

Defines non active portion of horizontal and vertical scans.

HSYN

Horizontal Sync

Initiates horizontal retrace.

VSYN

Vertical Sync

Initiates vertical retrace.

CSYN/

Composite Sync Output/ O/l
Line Lock Input

Composite sync is provided on the CRT 5027 and CRT 5037.

This output is active in non-interlaced mode only. Provides a true
RS-170 composite sync wave form. For the CRT 5057. this pin is
the Line Lock Input. The line frequency waveform, processed to
conform to the VTAC*s« specified logic levels, is applied to this pin.

CRV

Cursor Video

Defines cursor location in data field.

Vcc

Power Supply

+5 volt Power Supply

Voo

Power Supply

■*■12 volt Power Supply

272 APPENDIX C

Copyrighted material

Operation

The design philosophy employed was to allow the device to interface effectively with either a microprocessor based or

hardwire logic system. The device is programmed by the user in one of two ways: via the processor data bus as part of the
system initialization routine, or during power up via a PROM tied on the data bus and addressed directly by the Row Select

outputs of the chip. (Seo figure 4). Seven 8 bit words are required to fully program the chip. Bit assignments for these words
are shown in Table 1. The information contained in these seven words consists of the following:

Horizontal Formatting:

Character&Data Row

A 3 bit codo providing 8 mask programmable character lengths from 20 to 132.

The standard device will be masked for the following character lengths: 20.32.
40.64.72.80.96. and 132.

Horizontal Sync Delay

3 bits assigned providing up to 8 character times for generation of "front porch".

Horizontal Sync Width

4 Oils assigned providing up to 15 character times for generation of horizontal
sync width.

Horizontal Line Count

8 bits assignod providing up to 256 character times for total horizontal formatting.

Skew Bits

A 2 bit code providing from a 0 to 2 character skew (delay) between the
horizontal address counter and the blank and sync (honzontal.verticaUomposite)

signals to allow for retiming of video data prior to generation of composite video
signal. The Cursor Video signal is also skewed as a function of this code.

Vertical Formatting:

Interlaced/Non-interlaced

This bit provides for data presentation with odd/even field formatting for inter¬
laced systems It modities the vertical timing counters as described below.

A logic 1 establishes the interlace mode.

Scans/Frame

8 bits assigned, defined according to the following equations: Let X = value of 8
assigned bits.

1) in interlaced mode—scanstframe = 2X + 513. Therefore for 525 scans.
programX = 6 (00000110). Vertical sync will occur precisely every 262.5 scans,
thereby producing two interlaced fields

Range = 513 to 1023 scans/frame, odd counts only.

2) in non-interlaced mode—scans/frame • 2X + 256. Therefore for 262 scans,
program X - 3 (OOOOOO11).

Range = 256 to 766 scans/frame, even counts onfy.

In either mode, vertical sync width is fixed at three horizontal scans (■ 3H).

Vertical Data Start

8 bits defining the number of raster scans from the leading edge of vertical
sync until the start of display data. At this raster scan the data row counter is
set to the data row address at the top of the page.

Data Rows'Frame

6 bits assigned providing up to 64 data rows per frame.

Last Data Row

6 bits to allow up or down scrolling via a preload defining the count of the last
displayed data row.

Scans-'Data Row

4 txts assigned providing up to 16 scan lines per data row.

Additional Features

Device initialization:

Under microprocessor control—The device can be roset under syslem or program control by presenting a t010 address
on A3-0. The device will remain reset at the top of the even field page until a start command is executed by presenting a 1110
address on A3-0.

Via “Self Loading"—In a non-processor environment, the self loading sequence Is effected by presenting and holding the
1111 address on A3-0. and is initiated by the receipt of the strobe pulse (OS). The 1111 address should be maintained long
enough to insure that all seven registers have been loaded (in most applications under one millisecond). The timing
sequence will begin one line scan after the 1111 address is removed. In processor based systems, self loading is initiated by
presenting the 0111 address to the device. Self loading is terminated by presenting the start command to the device which
also initiates the timing chain.

Scrolling—In addition to the Register 6 storage of the last displayed data row a "scroll" command (address 1011)
presented to the device will increment the first displayed data row count to facilitate up scrolling in certain applications.

APPENDIX C 273

Copyrighted material

Horizontal Line Count:
Characters/Data Row:

Horizontal Sync Delay:
Horizontal Sync Width:

Skew Bits

Scans/Frame

Vertical Data Start:

Data Rows/Frame:
Last Data Row:

Mode:

Scans/Data Row:

Control Registers Programming Chart

Total Characters/Line * N +1, N = 0 to 255 (DBO = LSB)

DB2 DB1 DBO

0 0 0 * 20 Active Characters/Data Row

0 0 1 * 32

0 1 0 = 40

0 1 1 = 64

1 0 0 - 72

1 0 1 = 80

1 1 0 = 96

1 1 1 = 132

= N. from 1 to 7 character times (DBO = LSB) (N = 0 Disallowed)
* N, from 1 to 15 character times (DB3 = LSB) (N = 0 Disallowed)

Sync/Blank Delay Cursor Delay

DB7 DBS (Character Times)

0 0 0 0

10 1 0

0 12 1

112 2

8 bits assigned, defined according to the following equations:

Let X = value of 8 assigned bits. (DBO = LSB)

1) in interfaced mode-scans/frame - 2X + 513. Therefore for 525 scans,
program X = 6 (00000110). Vertical sync will occur precisely every 262.5
scans, thereby producing two interlaced fields.

Range ■ 513 to 1023 scans/frame, odd counts only.

2) in non-interlaced mode-scans/frame • 2X + 256. Therefore for 262
scans, program X * 3(00000011).

Range = 256 to 766 scans/frame, even counts only.

In either mode, vertical sync width is fixed at three horizontal scans (= 3H).
N ■ number of raster lines delay after leading edge of vertical sync o f
vertical start position. (DBO = LSB)

Number of data rows • N +1,N«0to63 (DBO* LSB)

N = Address of last dsplayed data row, N = 0 to 63, ie; for 24 data rows,
program N * 23. (DBO * LSB)

Interlace Mode

CRT 5027: Scans per Data Row = N +1 where N = programmed number of
data rows. N ■ 0 to 15. Scans per data row must be even counts only.

CRT 5037, CRT 5057: Scans per data Row ■ N +2.N * 0 to 14, odd or even
counts.

Non-Interlace Mode

CRT 5027, CRT 5037. CRT 5057: Scans per Data Row * N + 1. odd or
even count. N ■ Oto 15.

"LT

274 APPENDIX C

Copyrighted material

A3 A2 A1 A0

0 0 0 0
0 0 0 1
0 0 10
0 0 11
0 10 0
0 10 1
0 110
0 111

10 0 0
10 0 1
10 10

10 11

110 0
110 1
1110

1111

Select/Command

Load Control Register 0
Load Control Register 1
Load Control Register 2
Load Control Register 3
Load Control Register 4
Load Control Register 5
Load Control Register 6
Processor Initiated Self Load

Read Cursor Line Address
Read Cursor Character Address
Reset

Up Scroll

Description

} See Table 1

Command from processor instructing
VTAC' to enter Self Load Mode (via ex¬
ternal PROM)

Resets timing chain to top left of page. Reset
is latched on chip by Ds and counters are
held until released by start command.
Increments address of first displayed data
row on page, ie: prior to receipt of scroll
command—top line • 0. bottom line = 23.
After receipt of Scroll Command—top line =
1. bottom line = 0.

Load Cursor Character Address*

Load Cursor Line Address*

Start Timing Cham Receipt of this command after a Reset or

Processor Self Load command will release
the timing chain approximately one scan line
later. In applications requiring synchronous
operation of more than one CRT 5027 the
dot counter carry should be held low dunng

the DS for this command.

Non-Processor Self Load Device will begin self load via PROM

when D5 goes low. The 1111 command
should be maintained on A3-0 long
enough to guarantee self load. (Scan
counter should cycle through at least
once). Self load is automatically termi¬
nated and timing chain initiated when the
all “I s" condition is removed, indepen¬
dent of P5. For synchronous operation
of more than one VTAC*. the Dot Counter
Carry should be held low when the com¬
mand is removed.

‘NOTE: During Self-Load, the Cursor Character Address Register (REG 7) and the Cursor Row Address

Register (REG 8) are enabled during states Cl 11 and 1CCO of the R3-R0 Scan Counter outputs respectively.
Therefore, Cursor data in the PROM should be stored at these addresses.

TABLE 1

BIT ASSIGNMENT CHART

KXWCWTAl l*i€ COUNT SKEW BITS DATA RCW$TRAU€

,-1-,

#—i—- --1-

REG#

ft J_Mil *“»

7|6|5| | | |

MODE INTER. ACtO MSrNC WiQTh mS'NC DELAY
N3NiNTfffcAC€D i- 1 -i (- 1 -,

SCANtlSEStRAME

__1_

—i

REG *

7| 6 | | | 3 | Z 1 |0 | *0.

'Mill

SCAVSOATA ROW CHARACTERS DATA ROW

VERTICAL DATA START
f _-_1_

nt 02

! 6 1 1 1 3 1 2 I* H

7| 1 1 1 II

RCG«

l AST ClS^AVfOOATA t*JH
.- 1 - -

WTT I R1

CU*$0A CHARACTER ADDRESS

"“'M Mil TTal

RE 5 6

CURSOR ROW ADDRESS

- I

MAXIMUM GUARANTEED RATINGS*

Operating Temperature Range ...0*C to + 70*C

Storage Temperature Range ...-55*C to ♦ 150*0

Load Temperature (soldering, 10 sec).+325*C

Positive Voltage on any Pin. with respect to ground .♦ 18.0V

Negative Voltage on any Pin. with respect to ground .- 0.3V

'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.

NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.

In addition, voltage transient? on the AC power line may appear on the DC output. For example, the
bench power supply programmed to deliver +12 volts may have large voltage transients when the
AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (Ta= 0*C to 70‘C. Vcc« +5V-SV Voo* * 12Vs5%. unless otherwise noted)

Parameter Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level. V«.

High Level. Vih Vcc-1.5

OUTPUT VOLTAGE LEVELS
Low Level—Va for Rfif-3
Low Level—Va all others

High Level— Voh for R0-3. DB0-7 2.4

High Level— Voh all others 2.4

INPUTCURRENT
Low Level. In (Address, CS only)

Leakage, In (All Inputs except Address. CS)

INPUT CAPACITANCE
Data Bus. Cin
DS. Clock. Cin
All othor. Cin

DATA BUS LEAKAGE in INPUT MODE
loe

POWER SUPPLY CURRENT

Icc

loo

A.C. CHARACTERISTICS
DOT COUNTER CARRY

frequency 0.2

PWm 35

PWi 215

tr. tf

DATA STROBE

PW55 150ns

ADDRESS. CHIP SELECT
Set-uptime 125

Hold time 50

DATA BUS-LOADING

Set-uptime 125

Hold time 75

DATA BUS-READING
Toti*

Toci« 5

OUTPUTS: Hfif-7. HS. VS. 8L. CRV.
CS-Toeu

OUTPUTS: R7-3. DR0-5
Toco

Typ.

Max.

Unit

Comments

0.8

Vcc

0.4

lot =3 2ma

0.4

lex *1 6ma

lo-»80Ma

loH-40/ia

250

fiA

V in «0.4V

/*A

0<Vla<<Vcc

0.4V * V IN * 5.25V

100

Ta« 25’C

4.0

MHz

Figure 1

10 *s

Figure 2

Figure 2 ,

Figure 2

125

Figure 2. CL«50pF

Figure 2. CL=50pF

125

Figure 1.CL*20pF

500

Figure 3, CL-20pF

• R0-3 and DR0-5 may change prior to the falling edge of H sync

Restrictions

1. Only one pin is available for strobing data into the device via the data bus. The cursor X and Y coordinates are therefore
loaded into the chip by presenting one set of addresses and outpuled by presenting a (Afferent set of addresses. Therefore
the standard WRITE and READ control signals from most microprocessors must be "NORed” externally to present a single
strobe (£55) signal to the device.

2. In interlaced mode the total number of character slots assigned to the horizontal scan must be evon to insure that vertical
sync occurs precisely between horizontal sync pulses.

278 APPENDIX C

General Timing

HORIZONTAL TIMIVO

$TAOT Qt LINE N

START OFLlNCNvl

%i/i/i)i///i/))i//it//n/n n I777777

ACTIVE V'0€0»
CHARACTERS PER OATA LINE

HORIZONTAL $VNC DELAY
(FRONT PORCH!

HORIZONTAL SYNC WOTm-J
horizontal LINE COUNT.h •

VERTICAL THWjG

START Of FRAME M OR OOOF<LO

SON L»NES PER FRAME

STARTOP FRAME M* l OP EVEN FIELD

J77777///////7/////////77///77771 fH 7777

VERTICAL DATA
START

ACTIVE \n0€0-
OATA ROWS PER FRAME

-i

L VERTICAL SYNC
■ *H

H SYNC

V<x:
Vo-j

V SYNC •

Composite Sync Timing

n_n_n_

Vai

Vo~:

COMPOSITE
SVNC Vex

—HIJ-H

n n ruu

• • •

Vertical Sync Timing

»•*»*. «4

MUMC M •

• • •

sc***

SCAA. CCK^*t« *-«lO

HriXjmnjmiw

C***®0* —I

DATA C(X*M«
WAN'Mrt .»S» C(XHU

I—7S—*

1 n 111 m 1 n ii 11111

S**C

_njiimfmpumri

p **»CM 0*U 1CM..IH0K

~t 1111111111111 m 1111

li^M SAUOCM

Start-up, CRT 5027

Whon employing microprocessor controlled loading of the CRT 5027's registers, the following se¬
quence of instructions is necessary:

ADDRESS

1110
10 10
0 0 0 0

COMMAND

Start Timing Chain
Reset

Load Register 0

0 110
1110

Load Register 6
Start Timing Chain

The sequence of START RESET LOAD START is necessary to insure proper initialization of the
registers.

This sequence is not required if register loading is via either of the Self Load modes. This sequence
is optional with the CRT 5037 or CRT 5057.

Iqard mi crosystems

PORADONI

> orv

Circuit diagrams utilising SMC products are included as a mtons of illustrating typical semiconductor applica¬
tions. consequently compete information sufficient tor construction purposes is not necessardy gv.cn The
information has been carefully checked and rs belied to be entirety reliable However no responsibility it
assumed for inaccuracies Furthermore. Such information does not comey to the purchaser of the semiconductor
devices described any Kerne under the patent rights of SMC or others SMC reserves the right to make changes
at any t<me m order to improvo design and supply the best product possible

Copyrighted material

Appendix C9

STANDARD MICROSYSTEMS
CORPORATION

» Maras tM. Kjiaajge NV vw
(Mim-VOO Tta W W-ttM

we keep ahead of our competition so you can keep ahead of yours

CRT 8002

/XPC FAMILY

CRT Video Display Attributes Controller

Video Generator

VDAC™

FEATURES

□ On chip character generator (mask programmable)

128 Characters (alphanumeric and graphic)

7x11 Dot matrix block

□ On chip video shift register

Maximum shift register frequency
CRT 8002A 20MHz

CRT 8002B 15MHz

CRT 8002C 10MHz

Access time 400ns

□ On chip horizontal and vertical retrace video blanking

□ No descender circuitry required

□ Four modes of operation (intermixable)

Internal character generator (ROM)

Wide graphics
Thin graphics

External inputs (fonts/dot graphics)

□ On chip attribute logic-character, field

Reverse video
Character blank
Character blink
Underline
Strike-thru

□ Four on chip cursor modes

Underline
Blinking underline
Reverse video
Blinking reverse video

□ Programmable character blink rate

□ Programmable cursor blink rate

PIN CONFIGURATION

28 RET8L
27 CURSOR

26 MS#

25 MSI
24 BLINK
23 V SYNC
22 CHABL
21 REVID
20 UNOLN
19 STKRU
18 ATTBE
17 GND
16 R0
IS R1

□ Subscriptable

□ Expandable character set

External fonts
Alphanumeric and graphic
RAM. ROM. and PROM

□ On chip address buffer

□ On chip attribute buffer

□ +5 volt operation

□ TTL compatible

□ MOS N-channel silicon-gate COPLAMOS* process

□ CLASP® technology-ROM and options
D Compatible with CRT 5027 VTAC®

General Description

The SMC CRT 8002 Video Display Attributes Controller
(VDAC) is an N-channel COPLAMOS* MOS/LSl device
which utilizes CLASP® technology. It contains a
7X11X128 character generator ROM. a wide graphics
mode, a thin graphics mode, an external input mode,
character address/data latch, field and/or character
attribute logic, attribute latch, four cursor modes, two
programmable blink rates, and a high speed video
shift register. The CRT 8002 VDAC’* is a companion
chip to SMCs CRT 5027 VTAC Together these two
chips comprise the circuitry required for the display
portion of a CRT video terminal.

The CRT 8002 video output may be connected directly
to a CRT monitor video input. The CRT 5027 blanking
output can be connected directly to the CRT 8002
retrace blank input to provide both horizontal and
vertical retrace blanking of the video output.

Four cursor modes are available on the CRT 8002.
They are: underline, blinking underline, reverse video
block, and blinking reverse video block. Any one of
these can be mask programmed as the cursor func¬
tion. There is a separate cursor blink rate which can
be mask programmed to provide a 15Hz to 1 Hz blink
rate.

The CRT 8002 attributes Include: reverse video, char¬
acter blank, blink, underline, and strike-thru. The
character blink rateis maskprogrammablefrom7.5Hz
to 0.5Hz and has a duty cycle of 75/25. The underline
and strike-thru are similar but independently con¬
trolled functions and can be mask programmed to any
number of raster lines at any position in the character
block. These attributes are available in all modes.

In the wide graphic mode the CRT 8002 produces a
graphic entity the size of the character block. The
graphic ontity contains 8 parts, each of which is asso¬
ciated with one bit of a graphic byte, thereby provid¬
ing for 256 unique graphic symbols. Thus, the CRT
8002 can produce either an alphanumeric symbol or
a graphic entity depending on the mode selected.
The mode can be changed on a per character basis.

The thin graphic mode enables the user to create sin¬
gle line drawings and forms.

The external mode enables the user to extend the on-
chip ROM character set and/or the on-chip graphics
capabilities by Inserting external symbols. These ex¬
ternal symbols can come.from either RAM, ROM or
PROM.

APPENDIX C 279

Copyrighted material

MAXIMUM GUARANTEED RATINGS'

Operating Temperature Range .0 9 Cto + 70*C

Storage Temperature Range .- 55'C to +150®C

Lead Temperature (soldering. 10 sec.).+325 6 C

Positive Voltage on any Pin. with respect to ground . + 8.0V

Negative Voltage on any Pm. with respect to ground .- 0.3V

•Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.

NOTE: When powering this device from laboratory or system power supplies. It is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or “glitches" on their outputs when the AC power is switched on and off.

In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (T*-0 e C to 70*C. Vcc- +SVr5%. unless otherwise noted)

Parameter

Min.

Typ.

Max.

Unit

Comments

D.C. CHARACTERISTICS

INPUT VOLTAGE LEVELS

Low-level, V, t

0.8

excluding VDC

High-level, V w

INPUT VOLTAGE LEVELS-CLOCK

2.0

excluding VDC

Low-level. V*

0.8

High-level, V IM

OUTPUT VOLTAGE LEVELS

4.3

See Figure 6

Low-Ievol, V^

High-level, Voh

0.4

lot = 0.4 mA. 74LSXX load

2.4

Ion” “20*iA

INPUT CURRENT

Leakage. I L (Except CLOCK)

0<V 1N <Vcc

Leakage. I t (CLOCK Only)

INPUT CAPACITANCE

0SV w 5Vcc

Data

LD/SH

@ 1MHz
@ 1MHz

CLOCK

POWER SUPPLY CURRENT

@1MH 2

>cc

100

rnA

A.C. CHARACTERISTICS

See Figure 6,7

-——sr,,-

v. «■

‘’f

SYMBOL

PARAMETER

CRT 8002A

CRT 8002B

CRT 8002C

UNITS

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

VDC

Video Dot Clock Frequency

1.0

MHz

PW„

VDC—High Time

15.0

PW L

VDC-Low Time

15.0

ter

LD/§H cycle time

400

533

800

tr.t,

Rise, fall time

tsn-uf

Input set-up time

5K)

twoto

Input hold time

W tfCO

Output propagation delay

100

LD/§H set-uptime

LD/Sfi hold time

280 APPENDIX C

Copyrighted material

ROW ADDRESS
R3-R3

VDC

LO/5m

-4V

All INPUTS
(except VDC. LD/ 5*)

VIDEO

OUTPUT

h w -H

FIGURE 7

AC TIMING DIAGRAM

4.3V

11 k -

pw.

04V

'xi

20V

04V

—

— Uw—

20V

04V

20V

0 4V

APPENDIX C

DESCRIPTION OF PIN FUNCTIONS

PIN NO. SYMBOL

NAME

INPUT/

OUTPUT

VIDEO 1 Video Output

LD/

4-11

VDC

Video Dot Clock
Add'ess/Data

12 Vcc

13,14.15.16 R2.R3.Ri.Ri

17 GND

18 ATTBE

Power Suppty
Row Address

Ground _

Attribute Enable

GND

STKRU

Strike-Thru

UNDLN

Underline

REVID

Reverse Video

CHABL

Character Blank

V SYNC ' V SYNC

BLINK

Blink

MSI

MSfl

MSI

Mode Select 1
) Mode Select 0

MSP MODE

1 Alphanumeric

0 Thin Graphics

1 External Mode

0 Wide Graphics

_ FUNCTION _

The video output contains the dot stroam for the selected row of the alpha¬
numeric. wide graphic, thin graphic, or external character after processing by
the attribute logic, and the retrace blank and cursor inputs,
i In the alphanumeric mode, the characters are ROM programmed Into the
77 dots. (7X11) allocated for each of the 128 characters. Soo figure 5. The top
row (Rf) and rows R12 to R15 are normally all zorcs as is column C7. Thus, tha
character is defined in the box boundod by R1 to R11 and CD to C6. When a row
of the ROM. via the attribute logic, is parallel loaded into the 8-bit shift-register,
me first bit serially shifted out is C7 (A zero; or a one In REVID). It la followed
by C6.C5, through C0.

The timing of the Load/Shift pulse will determine the number of additional

(-. zoro to N) bac kfill z eros (or ones if in REViD) shifted out. See figure 4.

When the noxt Load/§hih pulse appoars the next character's row of the ROM,
via the attribute logic, is parallel loaded into the shift registor and the cycle

repeats. _

The 8 bit shift -reg ister parallel-in load or serial-out shift modes are established
by the Load/5hi?t input. When low. this Input enables the shift register for
serial shifting with each Video Dot Clock pulse. When high, the shift register
parallel (broadside) data inputs are enabled and synchronous loading occurs
on the noxt Vidoo Dot Clock pulse. During parallel loading, serial data flow
is inhibited. The Address/Data inputs (AD-A7) are latched on the negative
transition of the Load/SETft Input. See timing diagram, figure 7.

Frequency at which video is shifted. _

In the Alphanumeric Mode the 7 bits on Inputs (AD-A6) are Internally decoded
to address one of the 128 available characters (A7-X). In the External Mode.
A0-A7 i»used to insert an 8 bit word from a user defined external ROM, PROM
or RAM into tho on-chip Attribute logic. In the wide Graphic Modes A0-A7 is
used to define one of 256 graphic entities. In the thin Graphic Mode A0-A2 is
used to define the 3 lino segments.

+ 5 volt power supply _

These 4 binary inputs define the row addross in the current character block.

Ground __

A positive level on this input onaWos data from the Reverse Video. Character
Blank, Underline. Strike-Thru. Blink, Mode Select D. and Mode Select 1 Inputs
lo be strobed into the on-chip attribute latch at the negative transition of
the load/SKitt pulso. The latch loading is disabled when this input is low.
The latched attributes will remain fixed until this input becomes high again.
To facilitate attribute latching on a character by character basis, tie ATTBE
htflh. See timing diagram, figure 7,

Whon this inpul is high and RETBL = 0, tho parallel Inputs to the shift register
are forced high (SR0-SR7). providing a solid line segment throughout the
character block. The operation of strike-thru is modified by Reverse Video
(see table 1). In addition, an on-chip ROM programmable decoder is available
to decode the line count on which strike-thru is to bo placed as well as to
program the strike-thru to be 1 to N raster lines high. Actually, the strike-thru
decoder (mask programmable) logic allows the strike-thru to be any number
or arrangement of horizontal lines In the character block. The standard strike-
thru will be a double line on rows R5 and R6.

Whon this input Is high and RETBL — O. the parallel Inputs to the shift rogister
are forced high (SRD-SR7). providing a solid lino sogmont throughout the
character block. The operation of underline is modified by Reverse Video
(see table 1). In addition, an on-chip ROM programmable docodor is available
to decode the line count on which underline is to bo placed as well as to
program the underline to be 1 to N raster lines high. Actually, tho undortine
decoder (mask programmable) logic allows tho undorlino to be any numbor
or arrangement of horizontal lines in the character block. The standard undor-
lino will bo a single lino on R11.

. When this input is low ano RETBL - 0, data into tho Attribute Logic is presented
'directly to the shift register parallel inputs. When revorso video is high data
j into the Attribute Logic is Inverted and then presontod to the shift register
paraliol inputs. This operation reverses the data and field video. Soo table 1.

When this input is high, the parallel Inputs to the shift register aro all set low,
providing a blank character line segment. Character blank will override blink.
The operation of Character Blank is modified by the Reverse Video Input.
See table 1.

f This input is usod as tho dock Input for the two on-chfp mask programmable
blink rate dividers. The cursor blink rate (50/50 duty cycle) will be twice the
character blink rate (75/25 duty cycle). The divisors can be programmed from
■f- 4 to -*- 3Q for the cursor (-*- 8 to + 60 for the character).

When this input is high and RETBL = 0 and CHABL-0. the character will blink
at the programmed character blink rate. Blinking is accomplished by blanking
the character block with the Internal Character Blink clock. Tho standard
character blink rate Is 1.875Hz. _

These 2 inputs define the four modes of operation of the CRT 8002 as follows:
Al phanumeric Mode - In this mode addresses A0-A8 (A7«X) are in¬
ternally decoded to address 1 of the 128 available ROM characters The
addressed character along with the decoded row will define a 7 bit output
from the ROM to bo loaded into the shift register vie the attribute logic.

Thin Graphics Mode -In this mode A0-A2 (A3-A7-X) will be loaded
Into the thin graphic logic along with the row addresses. This logic will
define the segments of a graphic entity as defined in figure 2. The top of
the entity will begin on row 0000 and will end on a mask programmable row.

282 APPENDIX C

Copyrighted material

DESCRIPTION OF PIN FUNCTIONS

PIN NO.

SYMBOL

1 NAME

INPUT/

OUTPUT

FUNCTION

(corn.)

External Mode - In this mode the Inputs A0-A7 qo directly from the
character latch Into tho shift register via the attribute logic. Thus the user
may define external character fonts or graphic entities In an external
PROM. ROM or RAM. Soe figure 3.

Wide Graphics Mode-In this mode the Incuts A&-A7 will define a araohlc
entity as described In figure 1. Each line of the graphic entity is determined
by the wide graphic logic in conjunction with the row Inputs R0 to R3. In
this mode each segment of the entity is defined by one of the bits of the

8 bit word Therefore, the 8 bits can define any 1 of the 256 possible graphic
entities These entities can butt up against each other to form a contiguous
pattern or can be interspaced with alphanumeric characters. Each of the
entities occupies the space of 1 character block and thus requires 1 byte
of memory.

These a modes can be intermixed on a per character basis.

CURSOR

Cursor

When this input is onabiod 1 of tho 4 pre-programmed cursor modes will be
activated. The cursor mode is on-chlp mask programmable. The standard cur¬
sor will bo a blinking (at 3.75Hx) reverse video block. The 4 cursor modes are:
Underline-In this mode an underline (1 to N raster lines) at the programmed
underline position occurs.

Blinking Underllne-ln this mode the underline blinks at the cursor rato.

Rovcrse Video Block-In this medo the Character Block is set to reverse
video.

Blinking Reverse Video Block-In this mode tho Character Block is sot to
reverse video at tho cursor blink rate. The Character Block will alternate
between normal video and reverse video.

The cursor functions arc listed in table 1.

RETBL

Retrace Blank

When this input is latched high, the shift rogistor parallel Inputs ore uncon¬
ditionally cleared to all zeros and loaded into tho shift register on the next
Load/SnTFt pulse. This blanks the video, independent of ail attributes, during

1 horizontal and vertical retraco time.

TABLE1

CURSOR

RETBL

REVID

CHABL

UNDLN*

FUNCTION

1 X

"O’’

S.R.

All

(§.R.) All

M-J M

(S.R.)*

(S.R.) All others

"Q"

(S.R.) All

«.Q..

(S.R.)

(S.R.) All others

(S.R.) All

Underline*

M^lf

(S.R.)*

(S.R.) All others

Underline*

(S.R.)*

"O'*

(S.R.) All others

Underline*

"0"

(S.R.]

(S.R.;

1 All others

Underline*

“0"

(S.R.]

1 All others

Blinking*’Underline*

«»^ II

(S.R.)* Blinking

(S.R]

l All others

Blinking** Underline*

<•^>1

(s.r.:

1* Blinking

"O”

(S.R.]

1 All others

Blinking** Underline*

"0"

(s.r.;

|* Blinking

(s.r.;

I All others

Blinking** Underline*

"O"

(s.r.;

I* Blinking

(S^

1 All others

REVID Block

“8“

(S.R.) All

REVID Block

• 4l 0 ,f

(S.R.)*

(S.R. All others

REVID Block

11^ 19

(s.r :

) All

REVID Block

(s.r.;

(S.R.) All others

REVID Block

(S.R.) All

REVID Block

11^ It

(S.R.)*

(S.R.) All others

REVID Block

HQH

(S.R.) All

Blink** REVID Block

\ Alternate Normal Video/REVID

Blink*- REVID Block

1 At Cursor Blink Rate

Blink’* REVID Block

Blink*-REVID Block

*At Selected Row Decode **At Cursor Blink Rate

Note: If Character is Bunking at Character Rate. Cursor will change it to Cursor Blink Rate.

APPENDIX C 283

Copyrighted material

FIGURE 5

ROM CHARACTER BLOCK FORMAT

wi;*: hkks

’••T4W

38838

wsw

»y«;* .

» 2 * • • •

•Vivyj

•«• • • •

<4X<Xo* I W«

• kin

■ 98

ran

i ms

’ SgHBfl

\ ii?”':-:

•*rv

.nit

<> t**

• • • • •

BHra 5V

;«*«»«

XCw

I 5?&&3

inralftMt::

m 8

1:14 • irert a 4 3

9xn !

284 APPENDIX C

Copyrighted material

s&ts" Mam**

FIGURE 1

WIDE GRAPHICS MODE

MS0=0 MS1=0

C7 C6 C5 C4 C3 C2 Cl Ctf BF BP •

3 ONES'
JUNES
JUNES
J L'NES

ROWADD*t»
0005 —

| AT | AS | A> | A4 | A3 | A3 | A1 | At

'ON CHIP BOM r*CC*AV»VU8Lf TO J JOU LME MULTIPLES
"CAN BE PNO3RAUME0 FROM 1 TO 7 B'T$

•••UNOTH OETEHMJNEO 8Y LO/CT. VOC TIU.NO

example looioiio

Rtf

Rltf

R11

R12

R13

R14

R15

NOTE: Unsdcctcd rastorlino rows
are always filled with ones.

BF»back fill

FIGURE 2

THIN GRAPHICS MODE

MS0=0 MSI =1

— *0*0000

— PR00PAWA5^f
ROW

i ■ i ■ i«i ■ i»i * i M i -1

I.OOVTCAAE

* THE INSIDE SEGMENT IB MASK PAOORAMWL9LE
TO NOW WOO

•• LENGTH OITEAWINEO BY LOrSR VCC Timing

C7 C6 C5 C4 C3 C2 Cl Cg BF BF

R0
R9
Ritf

R11 NOTE
R12
R13
R14
R15

MOTE: WHeoAl «••!".Iheunoerlln*
tCw from* MtC at «!Ofl
Whan A1 - "O'. «*• yiderlin#.
If seicciaO. will appear.

BF-back Mi

R0-R15

FIGURE 3
EXTERNAL MODE

MS0=1 MSI =0

C7 C6 C5 C4 C3 C2 Cl C0 BF BF
A7 I A6 I A5 I A4 I A3* I A2 I A1 I AO I A7 I A7

BF=» back fill

APPENDIX C 205

Copyrighted material

FIGURE 4 TYPICAL VIDEO OUTPUT

LD/§H

JT»TRWJ

WW1

»c

J_r<u3

jn*ri

VIDEO DATA
0 DOT FIELD

VIDEO DATA
9 DOT FIELD

NOTE: C„

x« character number
y« column number

BF = back fill

VIDEO OOT
CLOCK

MICRO-

PROCESSOR

DATA 803

ACORESSBUS

CONTROL. BUS

PAW A ROW
IFOR *P)

}

carry

CHAWACTf R CLOCK

BI-DIRECTIONAL DATA BUS

ADDRESS BUS «

PAQE

LCOiC

CHIP SELECT

DATA STROBE

CHARACTER COLUMN

6 CHARACTER ROW

CHARACTER

ADDRESS

BUS

DCC

M SYNC

D8#-7

V SYNC

A8-3

VTAC

C SYNC

H0-7

DR8-5

R*3

CRV

SELECTOR

WITH

OPTONAl
MEMORY
MAPPING
CIRCUIT
(IP REQUIRED)

ASCII

PASTER

SCAN
COUNTER

ADDRESS

•2.P0RT RAM
IK * B TO 4K 16
CHARACTER
FRAME
BUFFER

OATA

DATA

BUS
ATTRIBUTE

OUT

-N

Vi OEO DOT

Clock

VDAC
CRT 8002

•OR 1 PORT RAM
WITH 01-OiPtCT

PORT

TIMING
FRCAI

DOT COUNTER
OR

CHARACTER

CLOCK

HQRIZ SYNC

VERT SYNC

COMPOSITE

SYNC

BLANKING

RETRACE

VIDEO

Blanking

SERIAL

OUTPUT

CRT 5027 VTAC
CRT 8002 VDAC
pP CONFIGURATION

Circuit degramS Utilizing SMC product* are included a* a means Of illustrating typical semiconductor applica¬
tions. consequently complete information sufficient tor construction purposes tS not necessarily given The
•nformaton has Been carelully Checked enq is t»el-e.«d to he entirety r#kat>te However. no responsibility «
assumed for inaccuracies Furthermore such information docs not convey to the purchase* of the semiconductor
devices descrioed any Kerne under the patent rights of SMC or others SMC reserves me nght to make changes
at any time m order to improve design and supply the ocs: product possitxo

286 APPENDIX C

Copyrighted material

Appendix CIO

STANDARD MICROSYSTEMS
CORPORATION

uncoil* tirjr
I5i6i??)-310C' IWtW-aMMt

We fcBep ahead of our competition so you can keep ahead of Yours.

COM 8046
COM 8046T

Baud Rate Generator

Programmable Divider

FEATURES PIN CONFIGURATION

□ On chip crystal oscillator or external
frequency input

□ Single +5v power supply

□ Choice of 32 output frequencies

□ 32 asynchronous/synchronous baud rates

□ Direct UART/USRT/ASTRO/USYNRT
compatibility

□ Re-programmable ROM via CLASP®
technology allows generation of other
frequencies

□ TTL. MOS compatible

□ IX Clock via fo/16output

□ Crystal frequency output via fx and fx/4
outputs

□ Output disable via FENA

XTAL/EXT1 1 IT
XTAL/EXT2 23
+ 5v 3 L
fx 4 0
GND 5 0
fo/16 6 0
FENA 7(j
E 8f!

^7~D16 fo
b 15 A
b 14 B

a 13 c

b 12 D
b 11 ST
bio fx/4
_5 9 NC

BLOCK DIAGRAM

fo/16

fx/4

APPENDIX C 287

Copyrighted material

General Description

The Standard Microsystems COM 8046 is an en¬
hanced version of the COM 5046 Baud Rate
Generator. It is fabricated using SMC's patented
COPLAMOS® and CLASP* technologies and em¬
ploys depletion mode loads, allowing operation from
a single +5v supply.

The standard COM 8046 is specifically dedicated to
generating the full spectrum of 16 asynchronous/
synchronous data communication frequencies for IX.
16X and 32X UART/USRT/ASTRO/USYNRT devices.

The COM 8046 features an internal crystal oscillator
which may be used to provide the master reference
frequency. Alternatively, an external reference may be
supplied by applying complementary TTL level sig¬
nals to pins 1 and 2. Parts suitable for use only with an
external TTL reference are marked COM 8046T. TTL
outputs used to drive the COM 8046 or COM 8046T
should not be used to drive other TTL inputs, as noise
immunity may be compromised due to excessive
loading.

The reference frequency (fx) is used to provide two
high frequency outputs: one at fx and the other at
fx/4. The fx/4 output will drive one standard 7400
load, while the fx output will drive two 74LS loads.

The output of the oscillator/buffer is applied to the
divider for generation of the output frequency f 0 . The
divider is capable of dividing by any integer from 6

to 2" + 1, inclusive. If the divisor is even, the output
will be square: otherwise the output will be high
longer than it is low by one fx clock period. The output
of the divider is also divided internally by 16 and made
available at the f 0 /16 output pin. The f 0 /16 output will
drive one and the f D output will drive two standard
7400 TTL loads. Both the f 0 and f c /l6 outputs can be
disabled by supplying a low logic level to the FENA
input pin. Note that the FENA input has an internal
pull-up which will cause the pin to rise to approx¬
imately V cc if left unconnected.

The divisor ROM contains 32 divisors, each 19 bits
wide, and is fabricated using SMC's unique CLASP y
technology. This process permits reduction of turn-
around-time for ROM patterns.

The five divisor select bits are held in an externally
strobed data latch. The strobe input is level sensitive:
while the strobe is high, data is passed directly
through to the ROM. Initiation of a new frequency is
effected within 3.5*s of a change in any of the five
divisor select bits: strobe activity is not required.
This feature may be disabled through a CLASP 5 pro¬
gramming option causing new frequency initiation to
be delayed until the end of the current f Q half-cycle
All five data inputs have pull-ups identical to that
of the FENA Input, while the strobe input has no
pull-up.

Description of Pin Functions

Pin No.

Symbol

Name

Function

XTAL/EXT1

Crystal or
External Input 1

This input is either one pin of the crystal package or one polarity
of the external input.

XTAL/EXT2

Crystal or
External Input 2

This input is either the other pin of the crystal package or the other
polarity of the external input.

Vcc

Power Supply

+ 5 volt supply

Crystal/clock frequency reference output

GND

Ground

fo/16

f 0 /16

IX clock output

FENA

Enable

A low level at this input causes the f 0 and f 0 /16 outputs to be
held high. An open or a high level at the FENA input enables the
f 0 and f 0 /16 outputs.

Most significant divisor select data bit. An open at this Input Is
equivalent to a logic high.

No connection

f x /4

fx/4

Vi crystal/clock frequency reference output.

Strobe

Divisor select data strobe. Data is sampled when this input is high,
preserved when this input is low.

12-15

D.C.B.A

Divisor select data bits. A = LSB. An open circuit at these inputs
is equivalent to a logic high.

16X clock output

288 APPENDIX C

Copyrighted material

ELECTRICAL CHARACTERISTICS COM8046, COM8046T, COM8116, COM8116T, COM8126,

COM8126T, COM8136, COM8136T, COM8146, COM8146T

MAXIMUM GUARANTEED RATINGS'

Operating Temperature Range . .(PC to 70*C

Storage Temperature Range .- 55*C to ♦ 1 50*C

Lead Temperature (soldering. 10 sec )..♦325*C

Positive Voltage on any Pm. with respect to ground . +8.0V

Negative Voltage on any Pm with respect to ground . .-0.3V

‘Stresses above those listed may cause permanent damage to the device This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not impfied

NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or '•glitches’* on their outputs when the AC power is switched on and off.

In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (Ta=0 C to 70’C. Vcc=*5Vr5%. unless Otherwise noted)

Parameter

Min.

Typ-

Max.

Unit

Comments

D.C. CHARACTERISTICS

INPUT VOLTAGE LEVELS

Low-level, V*

0.8

High-level. V«

OUTPUT VOLTAGE LEVELS

2.0

excluding XTAL inputs

Low-level. Va

0.4

l a = 1.6mA. for f x /4,f 0 /16

0.4

l a « 3.2mA. for f 0 , f„f r

0.4

l<x = 0.8mA, for f x

High-level. V<x

3.5

lo*» —100,-A; for f«. Iom = — 50>*A

INPUT CURRENT

Low-level. In

INPUT CAPACITANCE

-0.1

V--GND, excluding XTAL inputs

All inputs. C -

V -» GND. excluding XTAL inputs

EXT INPUT LOAD

POWER SUPPLY CURRENT

Series 7400 equivalent loads

Ice

A.C. CHARACTERISTICS

T»- +25°C

CLOCK FREQUENCY, f-

0.01

7.0

MHz

XTAL/EXT. 50% Duty Cycle ±5%
COM 8046. COM 8126. COM 8146

0.01

5.1

MHz

XTAL/EXT. 50% Duty Cycle ±5%
COM 8116. COM 8136

STROBE PULSE WIDTH. t,w

INPUT SET-UP TIME

150

t«

INPUT HOLD TIME

200

to*

STROBE TO NEW FREQUENCY DELAY

3.5

@ f. - 5.0 MHz

APPENDIX C 289

Copyrighted material

Crystal Operation
COM 8116
COM 8136

External Input Operation
COM 8116/COM 8116T
COM813E/COM8136T

74XX—totem pole or open cdlector output (external
pull-up resistor required)

Crystal Operation
COM 8126
COM 8146
COM 8046

External Input Operation
COM 8126/COM 8126T
COM 8146/COM 8146T
COM 8046/COM 8046T

74XX

TTL

74XX

TTL

74XX—toiem pole or open collector output (external
pull-up resistor required)

For ROM re-programmmg SMC has a computer program avaiiaole whercOy the Customer
need only supply the input frequency and me desired output frequences
The ROM programming »$ automatically generated

Crystal Specifications

User must specify termination (pm. w*re. Other)

Prefer: HC-18/U or HC-25/U
Frequency — 5 0608 MHz AT cut
Temperature range 0 C to 70 C
Senes resistance 5011
Senes Resonant

Overall tolerance * 0i*«
or as required

Crystal manufacturers .Pirr.aiL.sti

Northern Engineering Laboratories

357 Beio.t Street
Burlington. Wisconsin 53105
(414) 763-3591

Bulova Frequency Control Products

61-20 Woodstde Avenue
Woodside. New York 11377
(212) 335-6000

CTS Knights Inc.

101 East Church Street
Sandwich. Illinois 60548
(815) 786-8411

Crystek Crystals Corporation

1000 Crystal Drive

Fon Myers Flcr da 33901

(813)936-2109

290 APPENDIX C

Copyrighted material

COM 8046
COM 8046T

Divisor

Select

EOCBA

OODCO

OOOOl

OOOlO

00011

00100

00101

00110

00111

01001
01010
01011
01 ICO
01101
omo
01111
10000
10CO1
10010
10011
10100
10101
10110
10111

mi*

11C01

11010

11011

11100

11101

11110

11111

Table 2

REFERENCE FREQUENCY = 5 068800MHz

Deseed

Baud Clock

Rate Factor

Desired

Frequency

(KHz) Divisor

Actual Actual

Baud Frequency

Rate (KHz)

50 00

32X

75 00

32X

110 00

32X

134 50

32X

150 00

32X

200 00

32X

300 00

32X

600 00

32X

1200 00

32X

1800 00

C2X

2400 00

32X

360000

32X

4800 00

32X

7200 00

32X

9600 00

32X

19200 00

32X

50 00

16X

75 00

16X

110 00

16X

134 50

16X

150 00

16X

300 00

16X

600.00

16X

1200 00

16X

1800.00

16X

2000 00

16X

2400 00

16X

3600 00

16X

4800 00

16X

7200 00

16X

9603.00

16X

192CO.OO

16X

1 60000

2 400CO

3 52000

4 30400
4 80000
6 40000
9 60000

38 40000
57 6COOO
76 0COOO
115 2COOO
1 53 60000
230 40000
307.20000
614 40000
0 80000
1.20000

215200
2 40000
4 80000

1920000

28 80000
32 00000
30 40000

76 80000
115 2CCOO
153 60000
3C7.20CO0

3168

2112

1440

1177

1056

792

528

264

132

6336

4224

2880

2355

2112

1056

528

264

176

159

132

50 00
75 00
110 00
134 58
150 00
200 00
300 00
600 00
1200 00
1800 00
2400 00
3600 CO
4800 OO
7200 00
9900 00
19800 00
50 00
75 00
HOOO

134 52
150 00
300 00
600 00
1200 00
1800 OO
2005 06
2400 00
3600 00
4800 00
7200 00
9600 00
19800 00

lOO

16i
2.401
3.520CO0
4 306542
4 800000
6 400000
9 600000
19 200000
38 4COOCO

i • I

• Mi

57 600000
76 800000
115 200000
153 6COOOO
230 4COOOO
316 8COOOO
633 6COOOO
0 800000
1 200000
1 76COOO

2152357

Ml*

4 800000
9 600000
19 20CO00
28 8OO0CO
32 081013
38 400000
57 600000

•IMI*

115 200000
153 600000
316 8COOOO

Deviation

0 0000 %
0 0000 %

0 0000 %

0 0591%
00000%
0 0000%
0 0300%
0 0000 %
0 0000 %
0 0000 %
00000 %
0 0000 %
0 0000%
0 0000 %
3 1250%
3.1250%
0 . 0000 %
0 OOCO%
00000 %
00166%
0 0000%
0 0000%
0 0000 %
0 0000%
0 0000%
02532%
0 0000%
0 0000%
0 0000 %
0 0000 %
0 . 0000 %
3.1250%

292 APPENDIX C

RCP

RSI

OUAL

BAUD RATE GENERATOR

COM 8017
COM 2017

UART

TCP

TSO

Typical UART—Dual Baud Rata Gtnaralor Configuration

Full Duplax-Splil Speed

TSO

RSI

XTAL

XTAL/EXT1

XTAL/EXT2

To System

+ V

To System

STANDARD MICROSYSTEMS
CORPORATION

v* ro J«x hj ;j

kojcj rniac^nn

Circuit diagrams utilizing SMC products art included as a means of illustrat-ng typcai semiconductor applica¬
tions. consequently compete inlormation sufficient tor construction purposes it not necessarily given The
information has been carefully checked and is bettered to be entirety reliable However, no responsibility ft
assumed for inaccuracies Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any kcense under the patent rights of SMC or others SMC reserves the right to make Changes
at any time m order to improve design and supply the best product possible

Copyrighted material

Appendix D

ZAP Operating
System

Copyrighted material

Appendix D

ZAP Operating System

file

3000

7323

READY

ASSN

7324

0100

7324

0110

7324

0120

♦THE FOLLOWING EQUATES ARE USED

7324

0130

♦AS OPERATING SYSTEM

CONSTANTS

7324

0140

♦

7324

0150

ZERO

EQU

7324

0160

ONE

EQU

7324

0170

TWO

EQU

7324

0130

THREE

EQU

7324

0190

FOUR

EQU

7324

0200

FIVE

EQU

7324

0210

EIGHT

EQU

7324

0220

ADDIS1

EQU

♦MSDS ADDRESS DISPLAY

PORT

7324

0230

ADDIS2

EQU

♦LSDS ADDRESS DISPLAY

PORT

7324

0240

DATDIS

EGIJ

♦DATA DISPLAY PORT

7324

0250

EXECC

EQU

16D

♦EXEC KEY

7324

0260

NEXTC

EQU

32D

♦NEXT KEY

7324

0270

UART10

EQU

♦UART I/O PORT

7324

0280

UARTST

EQU

♦IJART STATUS PORT

7324

0290

KEYPT

EQU

♦KEYBOARD INPUT PORT

7324

0300

♦

7324

0310

♦

0000

0320

0000

0330

♦

0000

0340

♦

0000

0350

♦COLD SETS

THE OPERATING SYSTEM STACK POINTER

0000

0360

♦AND ENTERS

THE COMMAND RECQGNIITION MODULE

0000

0370

♦

0000

0380

♦

0000

0390

COLD

SP t SPSTRT ♦INITALIZE STACK POINTER

0003

0400

WARM01

0006

0410

0008

0420

WARM

WARM1

♦RST 1 OR WARM START

OOOB

0430

0010

0440

RST2E

RST2V

♦RST 2 TRANSFER

0013

0450

0018

0460

RST3E

RST3V

♦RST 3 TRANSFER

001B

0470

0020

0480

RST4E

RST4U

♦RST 4 TRANSFER

0023

0490

0028

0500

RST5E

RST50

♦RST 5 TRANSFER

0028

0510

0030

0520

RST6E

RST6U

♦RST 6 TRANSFER

0033

0530

0038

0540

RST7E

RST7V

♦RST 7 TRANSFER

0038

0550

0040

DB 07

0551

WARM01

(SPLSAO)

rSP

APPENDIX D 295

Copyrighted material

0044

0552

UARM2

*G0 TO COMMAND RECOGNITION

0047

0560 *

0047

0570 *

0047

0580 *

0047

0590 *WARM

START

SAVES THE USERS REGISTERS AND

0047

0600 CENTERS THE

COMMAND RECOGNITION MODE WITH

0047

0610 *FS DISPLAYED ON THE DATA AND ADDRESS DISPLAYS

0047

0620 *

0047

0630 UARM1

(ASAV) rA

♦SAVE USERS A

004A

0640

POP

♦GET USERS PC FROM STACK

004B

0650

(PCLSAV)fHL

♦SAVE USERS PC IN SAVE AREA

004E

0660

PUSH

004F

0670

POP

♦GET USERS FLAGS

0050

0680

(ESAU)rHL

♦SAVE USERS FLAGS

0053

0690

(IXLSAV)* IX

♦SAVE USERS IX

0057

0700

(IYLSAV)* IY

♦SAVE USERS IY

005B

0710

(SPLSAV ) f SP

♦SAVE USERS SP

005F

0720

A* I

♦SAVE USERS I

0061

0730

(ISAV)fA

0064

0740

AfR

♦SAVE USERS R

0066

0750

(RSAV)fA

0069

0760

HLfBSAV

006C

0770

(HL)fB

♦SAVE USERS B

006D

0780

INC

006E

0790

(HL)fC

♦SAVE USERS C

006F

0800

INC

0070

0810

(HL)fD

♦SAVE USERS D

0071

0820

INC

0072

0830

(HL)fE

♦SAVE USERS E

0073

0840

AFfAF

♦SAVE ALTERNATE REGISTERS

0074

0850

PUSH

0075

0860

(AASAV)fA

♦SAVE ALT A

0078

0870

(ALSAV)fHL

♦SAVE ALT H&L

007B

0880

POP

007C

0890

(AESAV)fHL

♦SAVE ALT FLAGS

007F

0900

HLfABSAV

0082

0910

(HL)fB

♦SAVE ALT B

0083

0920

INC

0084

0930

(HL)fC

♦SAVE ALT C

0085

0940

INC

0086

0950

(HL)fD

♦SAVE ALT D

0087

0960

INC

0088

0970

(HL)fE

♦SAVE ALT E

0089

0980 ♦

0089

0990 *

0089

1000 ♦COMMAND RECOGNITION MODULE

0089

1010 *

0089

1020 WARM2

CALL

CLDIS

♦CLEAR DISPLAY

008C

1030

A r255D

♦DISPLAY FFFF FF

008E

1040

OUT

ADDIS1

0090

1050

OUT

ADDIS2

0092

1060

OUT

DATDIS

0094

1070

CALL

KEYIN

♦GET INPUT CHARACTER

0097

1080

BfMEM

0099

1090

009A

1100

Zf MEMORY

♦JUMP IF MEMORY REQUEST

009D

1110

INC

009E

1120

009F

1130

ZfREGIST

♦JUMP IF REGISTER REQUEST

OOA2

1140

INC

OOA3

1150

00A4

1160

ZfGOREQ

00A7

1170

UARM2

OOAA

1180 *

OOAA

1190 MEM

EQU

64D

♦MEMORY KEY

OOAA

1200 ♦

OOAA

1210 *

OOAA

1220 ♦RESTART RESTORES THE USERS REGISTERS

OOAA

1230 ♦AND

RETURNS CONTROL TO

THE ADDRESS

296 APPENDIX D

Copyrighted material

OOAA

1240

♦SPECIFIED

IN THE PC SAVE LOCATION IN THE

OOAA

1250

♦REGISTER SAVE AREA

OOAA

1260

♦

OOAA

1270

RESTRT

A?(ABSAO)

♦RESTORE ALT REGISTERS

OOAD

1280

Br A

OOAE

J 290

A? ( ACSAV)

OOB1

1300

Ct A

00B2

1310

A* < ADSAU)

OOB5

1320

L.D

D? A

00B6

1330

A?(AESAY)

00B9

1340

E> A

OOBA

1350

A r (AFSAV)

OOBD

1360

L r A

OOBE

1370

PUSH

OOBF

1380

POP

OOCO

1390

A r (AASAY >

OOC3

1400

HLr (ALSAY)

OOC6

1410

EXX

00C7

1420

IYr(IYLSAY)

♦RESTORE IY

OOCB

1430

IX r(IXLSAY)

♦RESTORE IX

OOCF

1440

HLrISAY

OOD2

1450

A r < HL)

OOD3

1460

IrA

00B5

1470

INC

00 D6

1480

A r(HL)

OOD7

1490

Rr A

00D9

1500

HLrASAY

OODC

1510

A ?(HL)

♦RESTORE A

OODD

1520

INC

OODE

1530

Br (HL)

♦RESTORE B

OODF

1540

INC

OOEO

1550

Cr (HL)

♦RESTORE C

OOEl

1560

INC

00E2

1570

Dr(HL)

♦RESTORE D

OOE3

1580

INC

00E4

1590

Er(HL)

♦RESTORE E

00E5

1600

SPr(SPLSAY)

♦RESTORE STACK POINTER

OOE9

1610

HLr(PCLSAY)

♦REPLACE PC ON STACK

OOEC

1620

PUSH

OOED

1630

HLr(LSAY)

♦RESTORE HSL

OOFO

1640

RET

♦RETURN TO USER

OOF1

1650

♦

00F1

1660

♦ ♦

00F1

1670

♦

00F1

1680

♦CLDIS

CLEARS THE DATA

AND ADDRESS DISPLAYS

OOF1

1690

♦SETS

THE KEYBOARD BUFFERS AND CLEARS THE

00F1

1700

♦KEYBOARD FLAGS

OOF 1

1710

♦

00F1

1720

CLDIS

A r ZERO

OOF3

1730

(KFLAGS)rA

♦CLEAR FLAGS

OOF6

1740

(KDATA1> rA

♦CLEAR BUFFER

OOF9

1750

(KDATA2)rA

OOFC

1760

OUT

DATDIS

♦CLEAR DATA FIELD DISPLAY

OOFE

1770

OUT

ADDIS1

♦CLEAR ADDRESS FIELD DISPLAY

0100

1780

OUT

ADDIS2

0102

1790

RET

0103

1800

♦

0103

1810

♦

0103

1820

♦KEYIN

WAITS FOR INPUT

FROM THE KEYBOARD

0103

1830

♦UPON

DETECTING DATA AT

THE INPUT PORT (0)

0103

1840

♦01A THE STROBE BIT (7)

BEING SET THE DATA

0103

1850

♦ IS INPUT?THE STROBE BIT CLEARED? AND THE INPUT

0103

1860

♦CHARACTER

IS RETURNED

TO THE USER IN A

0103

1870

♦

0103

1880

♦

0103

1890

KEYIN

KEYPT

♦INPUT DATA

0105

1900

BIT

7 r A

0107

1910

ZrKEYIN

♦LOOP IF NO DATA

010A

1911

(TEMP)rA

♦SAYE CHARACTER

APPENDIX D 297

Copyrighted material

010D

1912

KEYIN1

KEYPT

010F

1913

BIT

7, A

0111

1914

NZtKEYIN1

♦JUMP IF STROBE PRESENT

0114

1915

Ar(TEMP)

0117

1920

RES

7,A

♦CLEAR STROBE

0119

1930

RET

011A

1940

011A

1950

011A

1960

*KFLG02 SETS THE NEXT(O)

AD NO DATA(2) KEYBOARD

FLAGS

011A

1970

♦

011A

1980

♦

011A

1990

KFL602

HLrKFLAGS

01 ID

2000

SET

Or(HL)

♦SET NEXT FLAG

01 IF

2010

SET

2r(HL)

0121

2020

POP

♦CLEAR RETURN

0122

2030

RET

0123

2040

♦

0123

2050

♦

0123

2060

*KFLGO

SETS

THE NEXT(0)

KEYBOARD FLAG

0123

2070

0123

2080

♦

0123

2090

KFLGO

HLrKFLAGS

0126

2100

SET

Or(HL)

♦SET NEXT FLAG

0128

2110

POP

♦CLEAR RETURN

0129

2120

RET

012A

2130

012A

2140

012A

2150

♦KFLG12 SETS THE EXEC(l)

AND NO DATA(2) KEYBOARD

FLAG

012A

2160

♦

012A

2170

♦

012A

2180

KFLG12

HLrKFLAGS

012D

2190

SET

lr(HL)

012F

2200

SET

2r (HL)

0131

2210

POP

♦CLEAR RETURN

0132

2220

RET

0133

2230

♦

0133

2240

0133

2250

♦KFLG1

SETS

THE EXEC (1)

KEYBOARD FLAG

0133

2260

0133

2270

0133

2280

KFLG1

HLrKFLAGS

0136

2290

SET

lr(HL)

♦SET EXEC FLAG

0138

2300

POP

♦CLEAR RETURN

0139

2310

RET

013A

2320

♦

013A

2330

♦

013A

2340

013A

2350

♦ONECAR INPUTS ONE CHARACTER FOLLOWED BY A NEXT

OR EXEC

013 A

2360

♦FROM *

fHE KEYBOARDr VALIDATES ITr AND RETURNS IT

013A

2370

♦THE USER IN KBATA2

013A

2380

♦

013A

2390

♦

013A

2400

ONECAR

CALL

CLDIS

♦CLEAR DISPLAYrBUFFERr&FLAGS

013D

2410

CALL

KEYIN

♦GET CHARACTER

0140

2420

OUT

DATDIS

♦DISPLAY CHARACTER

0142

2430

CALL

CARCK1

♦CHECK CHARACTER

0145

2440

BIT

6 r A

0147

2450

NZrONECAl

♦JUMP IF SHIFT

014A

2460

SUB

16D

♦CHARACTER=0-F

014C

2470

PrONECAR

♦JUMP IF NOT 0-F

014F

2480

ADD

16D

0151

2490

0NECA1

(KDATA2)rA

♦SAVE CHARACTER

0154

2500

CALL

KEYIN

♦GET NEXT CHARACTER

0157

2510

CALL

CARCK2

015A

2520

0NECA1

♦GO DO AGAIN NOT EXEC OR

015D

2530

♦

015D

2540

♦

015D

2550

♦CARCK1 CHECKS FOR A NEXT OR EXEC ON AN INITIAL

015D

2560

♦CHARACTER•

IF NEXT THE

i ROUTINE RETURNS TO CALLER VIA

298 APPENDIX D

Copyrighted material

015D

2570

♦KFLG02. IF

EXEC THE ROUTINE RETURNS TO THE CALLER

0150

2580

♦VIA KFLG12

0150

2590

0150

2600

♦

0150

2610

CARCK1

BrNEXTC

♦CHECK FOR NEXT

015F

2620

0160

2630

Z?KFLG02

♦IF NEXT JUMP

0163

2640

BrEXECC

♦CHECK FOR EXEC

0165

2650

0166

2660

Z fKFLG12

♦IF EXEC JUMP

016?

2670

RET

♦ELSE RETURN

016 A

2630

♦

016A

2690

♦

0.16 A

2700

*CARCK2 CHECKS FOR NEXT

OR EXECr SETS THE PROPER

016 A

2710

♦FLAG VIA KFLGO OR KFLG1 AND RETURNS TO THE USER

016 A

2720

♦ IF NOT NEXT OR EXEC THE ROUTINE RETURNS TO

016A

2730

♦THE ORIGINATOR OF THE

REQUEST

016 A

2740

♦

016A

2750

♦

016A

2760

CARCK2

BrNEXTC

♦CHECK FOR NEXT

016C

2770

0160

2730

Zt KFLGO

♦IF NEXT JUMP

0170

2790

BrEXECC

♦CHECK FOR EXEC

0172

2800

0173

2810

ZrKFLGl

0176

2820

RET

0177

2830

♦

0177

2840

♦

0177

2850

♦TWOCAR INPUTS 2 CHARACTERS FROM THE KEYBOARD

0177

2860

♦FOLLOWED BY A NEXT OR

EXEC AND RETURNS THEM TO THE

0177

2870

♦USER

IN KDATA2

0177

2880

♦

0177

2890

♦

0177

2900

TWOCAR

CALL

CLDAT

♦CLEAR BUFFER t FLAGSrAND DISPLAY

017A

2910

CALL

KEY IN

♦GET CHARACTER

017D

2930

CALL

CARCK1

♦CHECK FOR NEXT OR EXEC

0180

2940

TW0CA1

SUB

160

♦CHARACTER=0-F

0182

2950

PrTWOCAR

♦JUMP IF NOT 0-F

0185

2960

ADD

16D

0137

F 3

2970

HLrKDATA2

018A

2980

B r <HL>

♦GF.I OLD DATA

0183

2990

RLC

018D

3000

RLC

018F

3010

RLC

0191

3020

RLC

0193

3030

ADD

ArB

♦A=OLD&NEW

0194

3031

OUT

DATDIS

♦DISPLAY INPUT

0196

3040

(HL)rA

♦SAVE NEW DATA

0197

3050

CALL

KEYIN

♦GET NEXT CHARACTER

019A

6 A

3060

CALL

CARCK2

♦CHECK FOR TERMINATION

019D

3070

TW0CA1

♦JUMP IF NO TERMINATION

01 AO

3080

♦

01 AO

3090

♦

01 AO

3100

♦CLDAT

CLEARS THE INPUT BUFFERfFLAGS* AND DATA DIS

01 AO

3110

♦

01 AO

3120

♦

01 AO

3130

CLDAT

AfZERO

01A2

3140

(KFLAGS)»A

♦CLEAR FLAGS

01A5

3150

(KDATA2)rA

♦CLEAR BUFFER

01A8

3160

(KDATA1> rA

01AB

3180

RET

01 AC

3181

CLADD

ArZERO

♦CLEAR ADDRESS DISPLAY

01AE

3182

OUT

ADDIS1

0130

3183

OUT

ADDIS2

0132

3184

RET

01B3

3190

♦

0183

3200

01B3

3210

♦FORCAR INPUTS FOUR CHARACTERS FROM THE KEYBOARD

01B3

3220

♦FOLLOWED BY A NEXT OR

EXEC AND RETURNS THEM

APPENDIX D 299

Copyrighted material

01B3

3230

*T0 THE USER IN KDATA1

AND KDATA2

01B3

3240

01B3

3250

01B3

3260

FORCAR

CALL

CLDAT

♦CLEAR FLAGS AND BUFFER

01B6

3270

CALL

KEYIN

♦GET INPUT CHARACTER

01B?

3280

CALL

CARCK1

♦CHECK FOR NEXT OR EXEC

OIBC

3290

F0RCA1

SUB

16D

♦CHARACTER=0-F

OIBE

3300

PfFORCAR

♦JUMP IF NOT 0-F

01C1

3310

ADD

16D

01C3

3320

(TEMP)fA

♦SAVE CHARACTER

01C6

3330

Af(KDATA1)

♦A=MSD

01C9

3340

HL f KDATA2

01CC

3350

RRD

♦ADJUST DATA FOR NEW CHARACTER

01CE

3360

RLCA

01CF

3370

RLCA

01 DO

3380

RLCA

01D1

3390

RLCA

01D2

3400

AND

240D

♦MASK OFF OLD IDGIT

01D4

3410

HLrTEMP

01D7

3420

ADD

Af(HL)

♦ADD IN NEU DIGIT

01D8

3430

HLr(KDATA2)

♦SAVE NEU LSDS

01DB

3440

(KDATADfHL

♦SAVE NEU MSDS

01DE

3450

(KDATA2)fA

♦SAVE NEU LSDS

01E1

3460

OUT

ADDIS2

♦DISPLAY LSDS

01E3

3470

Af(KDATAI)

01E6

3480

OUT

ADDIS1

01E8

3490

CALL

KEYIN

♦GET NEXT CHARACTER

01EB

3500

CALL

CARCK2

♦CHECK FOR NEXT OR EXEC

01 EE

3510

F0RCA1

♦JUMP IF NOT NEXT OR EXEC

01F1

3520

♦

01F1

3530

♦

01F1

3540

♦

01F1

3550

♦

01F1

3560

♦MEMORY INPUTS AN ADDRESS FROM THE KEYBOARD FOLLOUED

01F1

3570

♦BY DATA AS

DEFINED BY

THE SEQUENCE

01F1

3580

♦ MEM(ADDRESS)NEXT f (DATA)NEXT»..(DATA >EXEC

01F1

3590

♦IF DATA IS

TO BE DISPLAYED

01F1

3600

♦ MEM(ADDRESS)NEXT f NEXT..♦.NEXT f EXEC

01F1

3610

♦EXEC 1

WILL RETURN CONTROL TO THE COMMAND RECOGNITION

01F1

3620

♦

01F1

3630

♦

01F1

3640

MEMORY

AfZERO

♦CLEAR MEMORY BASE ADDRESS

01F3

3650

(MBASEDfA

01F6

3660

(MBASE2) f A

OIF?

3661

CALL

CLADD

01FC

3670

CALL

FORCAR

♦GET BASE ADDRESS

OIF F

3680

Af(KFLAGS)

0202

3690

BIT

1 F A

0204

3700

NZ f UARM2

♦JUMP IF EXEC FLAG SET

0207

3710

Af(KDATA1)

♦SAVE MEMORY ADDRESS

020A

3720

(MBASE2)fA

020D

3730

Af(KDATA2)

0210

3740

(MBASE1) f A

0213

3750

HL f (MBASE1)

♦SET MEM BASE ADDRESS

021A

3760

MEM1

Af(HL)

♦GET MEMORY DATA

0217

3770

OUT

DATDIS

♦DISPLAY MEMORY DATA

0219

3780

CALL

TWOCAR

♦GET NEU DATA

021C

3790

Af(KFLAGS)

02 IF

3800

BIT

2 f A

0221

3810

NZ f MEM2

♦JUMP IF NO DATA

0224

3820

HLf(MBASEI)

♦GET MEM ADDRESS

0227

3830

Af (KDATA2)

♦GET NEU DATA

022A

3840

(HL)fA

♦REPLACE OLD DATA

022B

3850

Af(KFLAGS)

022E

3860

BIT

IfA

0230

3370

NZ fUARM2

♦JUMP IF EXEC FLAG SET

0233

3380

MEM12

HLf(MBASEI)

♦INC BASE MEM ADD

0236

3390

INC

0237

3900

(MBASEI)fHL

300 APPENDIX D

Copyrighted material

023A

3901

AfL

023B

3902

OUT

ADDIS2

023D

3903

ArH

023E

3904

OUT

ADDIS1

0240

3910

MEM1

0243

3920

MEM2

BIT

If A

0245

3930

NZfUARM2

♦JUMP IF EXEC FLAG SET

0248

3940

MEM12

024B

3950

024B

3960

024B

3970

024B

3980

♦

024B

3990

*REGIST INPUTS A REGISTER FROM THE KEYBOARD FOLLOWED BY

024E<

4000

♦DATA

AS DEFINED BY THE SEQUENCE

024B

4010

♦ REG(INIT

REG)NEXT f(DATA)NEXT♦.♦ ( DATA)EXEC

024B

4020

♦REGISTER SEQUENCE IS

IXflYfSPfPCfltRfHfLfAfBfCfDfEfFf

024B

4030

♦ALrAH

f AA r AB y AC y AD y AE y i

024B

4040

♦IF ONLY DATA IS TO BE

DISPLAYED

024B

4050

♦ REG(INIT

REG)NEXT y NEXT«♦.EXEC

024B

4060

♦EXEC

WILL RETURN CONTROL TO THE COMMAND RECOGNITION

024B

4070

♦

024B

4080

♦

024B

4090

REGIST

CALL

ONECAR

♦GET INITIAL CHARACTER

024E

4100

Af(KFLAGS)

0251

4110

BIT

2f A

0253

4120

NZfWARM2

♦JUMP IF NO DATA FLAG SET

0256

4130

Af(KDATA2)

♦GET BASE REGISTER

0259

4140

REGIO

(TEMP2)f A

025C

4141

BIT

6 f A

♦CHECK FOR SHIFT

025E

4142

NZfREGISA

♦JUMP IF SHIFT KEY SET

0261

4143

0263

4144

PfREGIl

♦JUMP IF EIGHT BIT REGISTER

0266

4145

DEC

0267

4146

DEC

0268

4147

ADD

♦I=(I-2)^2

0269

4148

REG 12

026C

4149

REGI1

INC

026B

4150

INC

026E

4151

REGI2

(REGINX)fA

♦SAVE INDEX

0271

4152

Af(TEMP2)

0274

4153

10H

0276

4154

MrREGI2A

0279

4155

BIT

6 f A

027B

4157

NZ fREGI2A

♦JUMP IF BIT 6 SET

027E

4158

Af 48H

0280

4159

(TEMP2)fA

0283

4160

REGI2A

OUT

DATBIS

♦DISPLAY REGISTER SELECT

0285

4210

Af(REGINX)

0288

4220

EIGHT

028A

4230

MfXYSP

♦JUMP IF 16 BIT REG

028D

4240

HLfIXLSAV

♦GET BASE ADD

0290

4250

Cf A

0291

4260

B f ZERO

0291

4270

ADD

HLfBC

0294

4280

(MBASEl)fHL ♦SAUE REG SAVE ADD

0297

4290

Af(HL)

♦GET REGISTER DATA

0298

4300

OUT

ADDIS2

♦DISPLAY DATA

029A

4310

A f B

029B

4320

our

ADDIS1

029D

4330

CALL

TUQCAR

♦GET NEW DATA

02AO

4340

Ar(KFLAGS)

02A3

4350

BIT

2 f A

02A5

4360

NZfREG13

♦JUMP IF NO DATA

02A8

4390

HLf(MBASE1)

02AB

4400

Af(KDATA1)

♦GET NEW DATA

02AE

4410

(HL)fA

♦REPLACE OLD DATA

02AF

4411

Af(KFLAGS)

02B2

4412

BIT

1 f A

APPENDIX D 301

Copyrighted material

02B4

4413

NZ rWARM2

♦JUMP IF EXEC FLAG SET

02B7

4420

REGI3

Ar < TEMP2)

♦INCREMENT INDEX

02BA

4421

INC

02BB

4422

(TEMP2)r A

02BE

4423

A.(REGINX)

♦INCREMENT INDEX

02C1

4430

INC

02C2

4440

1 AH

02C4

4450

MrREG12

♦JUMP IF INDEX .LT• 1A

02C7

4460

REGI4

Ar TWO

♦SET INITIAL INDEX

02C9

4470

REGIO

02CC

4430

REGISA

SUB

48H

0*2 C£

4490

MrREGIST

♦JUMP IF INVALID REGISTER

02D1

4500

ADD

12H

02D3

4510

REG 12

02D6

4520

XYSP

HLrIXLSAV

02D9

4530

CrA

02BA

4540

Br ZERO

02 BC

4550

ADD

HLrBC

♦HL=REG SAVE ADDRESS

02DD

4560

(MBASE1> rHL

02E0

4570

Ar(HL)

♦DISPLAY REGISTER DATA

02E1

4580

OUT

ADDIS2

02E3

4590

INC

02E4

4600

A r(HL)

02E5

4610

OUT

ADDIS1

02E7

4620

Ar(REGINX)

02EA

4630

INC

02EB

4640

(REGINX)rA

02EE

4650

CALL

FORCAR

♦GET NEW DATA

02F1

4660

Ar(KFLAGS)

02F4

4670

BIT

2 r A

02F6

4680

NZrREGI5

♦JUMP IF NO DATA

02F9

4710

HL r(MBASE1)

♦REPLACE OLD DATA

02FC

4720

Ar(KDATA2)

02FF

4730

(HL)rA

0300

4740

A r(KDATA1)

0303

4750

INC

0304

4760

(HL)rA

0305

4761

Ar(KFLAGS)

0308

4762

REG 15

BIT

1 r A

030A

4763

NZ r WARM2

♦JUMP IF EXEC FLAG SET

030D

4770

REGI3

0310

4780

♦

0310

4790

♦

0310

4800

♦

0310

4810

♦

0310

4820

*G0 RESETS THE USERS RESTART ADDRESS IN THE

0310

4330

♦REGISTER SAVE AREA AND

EXITS TO THE RESTART

0310

4840

♦MODULE

0310

4850

♦

0310

4860

♦

0310

4870

GOREQ

CALL

CLADD

0313

4871

CALL

FORCAR

♦GET RESTART ADDRESS

0316

4880

Ar(KFLAGS)

0319

4890

BIT

2 r A

031B

4900

NZ rWARM2

♦IF NO DATA EXIT

031E

4910

Ar(KDATA2)

♦SAVE NEW ADDRESS

0321

4920

(PCLSAV)r A

0324

4930

A r(KDATA1)

0327

4940

(PCHSAV)rA

032A

4950

RESTRT

032D

4960

♦

032B

4970

♦

032D

4980

♦

032D

4990

♦UATST

IS A

UART LOOP CHECK ROUTINE

0320

5000

♦IT UTILIZES A LOOP WITH THE OUTPUT

0320

5010

♦PORT 1

PATCHED TO THE INPUT PORT

032D

5020

♦ IF AN

ERROR IS DETECTED THE ERROR IS

032D

5030

♦DISPLYED ON THE ADDRESS DISPLAY AND

302 APPENDIX D

Copyrighted material

032D

5040

*THE CHARACTER IS DISPLAYED ON THE DATA DISPLAY

03 2D

5050

*THE OUTPUT

CHARACTE IS

DISPLAYED ON THE MSD

032D

5060

♦OF THE ADDRESS DISPLAY

032D

5070

♦

032D

5080

UATST

ByZERO

♦

032F

5090

UARTST

♦GET STATUS

0331

5100

BIT

0>A

0333

5110

ZfUAERI ♦JUMP IF XMIT BUFFER NOT EMPTY

0336

5120

UATSTO

ArB

♦GET OUTPUT CHARACTER

0337

5130

OUT

ADDIS1

033?

5140

OUT

UART10

033B

5150

UATST1

UARTST

033D

5160

BIT

lyA

033F

5170

ZrUATSTl

♦JUMP IF NO DATA AVAILABLE

0342

5130

AND

1CH

0344

5190

NZrlJAERl

♦JUMP IF PARITY ERROR

0347

5240

UARTIO

♦GET INPUT CHARACTER

0349

5250

OUT

BATDI3

034B

5260

034C

5270

NZfUAER2

♦JUMP IF INPUT♦NE♦OUTPUT

034F

5280

INC

0350

5290

UATSTO

0353

5300

UAER1

OUT

ADDIS2

♦DISPLAY UART STATUS

0355

5310

UARTTO

♦GET INPUT DATA

0357

5320

OUT

DATDIS

0359

5330

HALT

035A

5340

UAER2

A»OFH

035C

5350

OUT

(ADDIS2)fA

035E

5360

HALT

035F

5370

035F

5380

035F

5390

♦TTYINPUT DRIVER

035F

5400

♦INPUTS DATA INTO THE SPECIFIED BUFFER

035F

5410

♦INPUT

IS TERMINATED WHEN A CARRIAGE RETURN

035F

5420

♦IS DETECDED OR THE NUMBER OF SPECIFIED CHARACTERS

035F

5430

♦HAVE BEEN !

INPUTED FROM

THE TRANSMITDING DEVICE

035F

5440

♦

035F

5450

TTYINP

HLr(TTYIBF)

♦GET BUFFER ADDRESC

0362

5460

Ay(TTYIC)

♦GET NYMBER OF CHARACTERS

0365

5470

By A

0366

5480

TTYIN1

UARTST

♦GET UART STATUS

0368

5490

BIT

1 1 A

036A

5500

ZrTTYINl :

*JUMP IF NO DATA

036D

5510

AND

1CH

036F

5520

NZfTTYERR

♦JUMP IF PARITY ERROR

0372

5570

UARTIO

♦GET INPUT CHARACTER

0374

5580

(HL)rA

♦SAFE CHARACTER IN USERS BUF

0375

5590

ApODH

0376

5600

ZfTTYIN2

♦JUMP IF CARRIAGE RETURN

0379

5810

ArONE

♦SET OUTPUT CHARACTER COUNT

037B

5620

TTYIN3

(TTYOBF)yHL

♦SET OUTPUT BUFFE ADDRESS

037E

5630

(TTYOC)y A

0381

5631

AyB

0382

5632

(TEMP)yA

0385

5640

CALL

TTYOUT

♦GO OUTPUT CHARACTER

0388

5641

Ay (TEMP)

038B

5642

ByA

038C

5650

DEC

038D

5660

RET

♦RETURN IF ALL CHARACTERS IN

038E

5670

TTYIN1

0391

5680

TTYIN2

HLy LF

♦GET LINE FEED ADDRESS

0394

5690

AyTWQ

0396

5700

ByONE

0398

5710

TTYIN3

039B

5720

TTYERR

RET

♦RETURN WITH ERROR CODE IN

039C

5730

ODHyOAH

♦LINE FEED/CARRIAGE RETURN

039E

5740

♦

039E

5750

♦TTY OUTPUT

DRIVER

APPENDIX D 303

Copyrighted material

039E

07C4

07D7

07D8

07D9

07DA

07DB

07DC

07DD

07DE

07DF

5760 ♦TTYOUT OUTPUTS BATA FROM THE SPECIFIED
5770 *USERS BUFFER TO THE UART♦ THE NUMBER OF
5780 *USER SPECIFIED CHARACTES ARE OUTPUT
5790 *AND CONTROL RETURNED TO THE USER

039E

5800

♦

039E

5810

TTYOUT

HLf(TTYOBF >

♦GET BUFFER ADDRESS

03A1

5820

Af(TTYQC)

♦GET NUMBER OF CHARACTERS

03A4

5830

Bf A

03A5

5840

TTY0U1

CfZERO

03A7

5850

DEf ZERO

03AA

5860

TTY01

UARTST

♦GET STATUS

03AC

5870

BIT

Of A

03AE

5880

ZfTTY0U2

♦JUMP IF BUFFER NOT EMPTY

03B1

5890

Af(HL)

♦GET CHARACTER

03B2

5900

OUT

UARTIO

♦OUTPUT CHARACTER

03B4

5910

DEC

03B5

5920

A f ZERO

03B7

5930

RET

♦RETURN IF BUFFER EMPTY

03B8

5931

INC

03B9

5940

TTY0U1

03BC

5950

TTY0U2

INC

♦TRY AGAIN DELAY

03BD

5960

ArE

03BE

5970

ZERO

03C0

5980

NZ ? TTY0U2

03C3

5990

A r D

03C4

6000

ZERO

03C6

6010

NZ f TTY0U2

03C9

6020

INC

03CA

6030

FIYE

03CC

6040

NZfTTYOI

♦JUMP IF .LT.5 TRYS

03CF

6050

AfONE

♦ELSE RETURN WITH A=1

03D1

6060

RET

03D2

6070

♦

07C4

6080

7C4H

07C4

6090

♦

6100

6110

6120

♦PAGE

♦SAVE

♦

2 CONSTANSfJUMP AREAS»AND REGISTER
AREAS

07C4

6130

SPSTRT

♦STACK

; AREA

07C5

6140

♦

07C5

6150

♦ USER

RESTART

AREA

07C5

6160

♦

07C5

6170

RST2Y

♦ USER

BRANCH

AREA

FOR

RST

07C8

6180

RST3V

♦USER

BRANCH

AREA

FOR

RST

07CB

6190

RST4Y

♦ USER

BRANCH

AREA

FOR

RST

07CE

6200

RST5Y

♦ USER

BRANCH

AREA

FOR

RST

07D1

6210

RST6Y

♦USER

BRANCH

AREA

FOR

RST

07D4

6220

RST7Y

♦USER

BRANCH

AREA

FOR

RST

6230

6240

6250

6260

♦REGISTER SAVE AREA
♦

IXLSAY DB

6270 IXHSAY DB

6280 IYLSAY DB

6290 IYHSAY DB

6300 SPLSAY DB

6310 SPHSAY DB

6320 PCLSAY DB

6330 PCHSAY DB

6340 ISAY

304 APPENDIX D

Copyrighted material

07E0

6350

RSAV

07E1

6360

LSAV

07E2

6370

HSAV

07E3

6380

ASAV

07E4

6390

BSAU

07E5

6400

CSAV

07E6

6410

DSAU

07E7

6420

ESAV

07E8

6430

FSAV

07E9

6440

ALSAU

07EA

6450

AHSAU

07EB

6460

AASAU

07EC

6470

ABSAV

07ED

6480

ACSAU

07EE

6490

ADSAU

07EF

6500

AESAU

07F0

6510

AFSAU

07F1

6520

6530

♦BATA STORAGE AREA

07F1

6540

6550

KFLAGS

♦KEYBOARD FLAGS

07F2

6560

KDATA1

♦KEYBOARD INPUT BUFFER

07F3

6570

KDATA2

07F4

6580

TEMP

07F5

6581

TEMP2

07F6

6590

MBASE1

♦BASE MEMORY ADDRESS

07F7

6600

MBASE2

07F8

6610

REGINX

♦REGISTER INDEX

07F9

6620

TTYIBF

♦TTY INPUT BUFFER ADDRESS

07FB

6630

TTYOBF

♦TTYOUTPUT BUFFER ADDRESS

07FD

6640

TTYIC

♦TTY INPUT CHARACTER COUNT

07FE

6650

TTYOC

♦TTY OUTPUT CHARACTER COUNT

07FF

6660

6670

END

FILE 3000 7323

READY

APPENDIX D 305

Copyrighted material

Appendix E

Z80 CPU

Technical

Specifications

Copyrighted material

Appendix El Electrical Specifications

Absolute Maximum Ratings

Temperature Under Bits
Storage Temperature
Voltage On Any Pin
with Respect to Ground
Power Dissipation

Specified operating range.
-65 # C to ♦ I $0°C
-0.3V to +7V

1.5W

•Comment

Stresses above those listed under “Absolute
Maximum Rating** may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device
at these or any other condition above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.

Note: For Z80CPU all AC and DC charactcnsttcs remain the
same for the military grade parts except l cc .

1^- 200 mA

Z80-CPU D.C. Characteristics

T A * 0*C to 70°C. V tfC ■ SV t 5‘A unless otherwise specified

Symbol

Parameter

Min.

Typ-

Max.

Unit

Test Condition

V ILC

Clock Input Low Voltage

-0.3

0.45

V IHC

Clock Input High Voltage

V cc -.6

V cc *.3

V IL

Input Low Voltage

-0.3

0.8

V lH

Input High Voltage

2.0

V cc

V 0L

Output Low Voltage

0.4

, OL s, ' bmA

V 0H

Output High Voltage

2.4

'oh ‘ - 250 * A

•cc

Power Supply Current

ISO

•li

Input Leakage Current

Vjn-O to V cc

•loh

Tri-State Output Leakage Current in Float

v OUT’ 24,oV cc

•lol

Tii Staie Output Leakage Current in Float

-10

v out*° 4V

! ld

Dau Bus Leakage Current in Input Mode

110

°< V .N< V «

Capacitance

T a * 25°C, f 3 1 MHz,
unmeasured pins returned to ground

Symbol

Parameter

Max.

Unit

Clock Capacitance

C IN

Input Capacitance

C OL'T

Output Capacitance

Z80-CPU

Ordering Information

C - Ceramic
P — Plastic

S - Standard SV *5% 0* to 70°C
E - Extended SV iS% -40* to 85*C
M - Military SV tlO%-SS° to I2S*C

Z80A-CPU D.C. Characteristics

* 0*1* to 70*(\ V cc ■ 5V t S*; unlow otherwise specified

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Condition

V ILC

Cluck lupin Low Voliage

-0 3

045

V IIK

Clock Input High Voltage

v cc -.6

v «o

V IL

Input Low Voltage

-0.3

•

V |»l

Input High Voltage

:.o

v «

V OL

Output Low Voltage

0.4

■ol" 1 bmA

V OII

Output High Voltage

2,4

•on * -- 5( * A

hrwei Suppt> Cuireut

:oo

*LI

input Leakage Cut rent

V |N*° lw v cc

'loii

Tti-Siatc Output Leakage Current m Float

V 0lT -2.4 l,s V vV

■loi.

Tn-Slate Output Leakage Current in Float

-10

V OUT -0.4V

•ld

Da'a Bun Leakage Current in Input Mode

210

0<V IN< V cc

Capacitance

r A * 2$°C, f • I MH*.

unmeasured pins returned to ground

Symbul

Parameter

Max

Unit

(

CI»k k l apa, name

<|N

lupin Capacitance

pi-

l on

Output C apa%ilaiKc

Z80A-CPU

Ordering Information

C - Ceramic
P - Plastic

S - Standard SV tS* 0 V to 70*C

APPENDIX E 309

Copyrighted material

A.C. Characteristics

Z80-CPU

T a = 0°C to 70°C, Vcc = +SV t 5%, Unless Otherwise Noted.

Signal

Symbol

Pm meter

Max

Unit

Tel Condition

»c

Clock Period

1121

jjsec

lit

i w WI|

CKn.it Pulse Width. Clock High

1 HO

|k|

nscc

l w (4*t.)

Clock Pulse Wtdlli. ClsK.it Low

ISO

2000

nscv

‘t.f

Clock Rise and Fall Time

nsti

'D(AD)

Address Ouipui Delay

14$

nscc

'Ft AD)

Delay lo Floal

nsec

Vis

‘acm

Address Stable Prior to MRF0(Memory Cycle)

III

nsec

C L ■50pF

•ac.

Address Stable Pnoe to IORO RD .v WR (I/OCycle 1

' [!!

nsec

Address Stable fions RD. WR, IQRQ or MREQ

nscc

Address Stable From Hl)m WR During Final

nsti

'D(D»

Data Output Delay

230

nsev

'F(D)

Delay to Float IXartng Write Cycle

nsec

*S4» < Dl

IXna Setup Time lo Rising Edge ol Clock Doing Ml Cycle

nsec

°0-7

‘S*(Dl

Data Setup Time to Falling Edge of Clock During M2 to MS

(30

nsec

C, = 50pF

'dem

Data Stable Prior to W'K (Memo*)- Dyck)

I<1

nsec

‘dci

Data Stable Prior lo WR (1,0 Cycle)

tol

nsec

•cdt

Data Stable From WR

1*1

Any Hold Time for Setup Time

nsei

'DL$(MR>

m'kFO Delay Fiom Falling Edge ol Cluii. MRE6 Low

too

n>cc

vmrs

'DH4» (MR)

MKfcO May From Rising Edge of Clock. MREQ High

100

nsec

«DH4»(MR)

MREQ DLy From Falling Edge of Ckxk. MK£'J High

l6()

nsec

C. -50pF

'w(MRL)

Pulse Width. MREO Low

181

nsec

‘wfMRH)

Pulse Width. mRE( 5 High

191

nsec

'DO (IR)

16ft<5 Dtby Fiom Rising Edge of Clock. i(!)R<5 Low

nsec

R5W3

‘DLi(IR)

IORO DeLy From Falling Edge of Clock. IORO Low

TTCT

nscc

C L * 50pF

‘DH$ (IR>

I6r 6 DeLy From Rising Edge of Clock. IORO High

H55

nsec

'DH4> (IR)

I0RQ Delay From Falling Edge of Clock. IORO High

110

nsec

‘DL 1 * (RD)

RD DeLy From Rasing Edge of Clock. RD Low

RD Dtby From Falling Edge of Clock. RD Low

100

nsec

‘Dl$(RD)

130

nsec

C L -50pF

'DHO(RD)

RD DeLy From Rating Edge of Clock. RD High

TTO

nsec

‘DH^(RD)

RD DeLy From Falling Edge of Clock. RD High

nsec

‘Dl«>(WR)

WR DeLy From Rasing Edge of Clock. W R Low

nsec

‘DL«b(WTt)

WR Delay From Falling Edge of Clock. WR Low

nsec

C L *50pF

«DH*(WR)

‘w(WRu

Wr Delay From Falling Edge of Clock. WR High

100

nsec

Pulse WSdth. WR Low

HO)

nsec

'DL(MI)

Ml Delay From Rising Edge of Oock. Ml Low

130

nsec

C L - 50pF

Wl Delay From Rising Edge of Clock. Ml High

130

nscc

EFsB

«DL(RF)

RFSH Delay From Rising Edge of Clock. RFSH Low

180

nsec

P- 5 CAnC

'DH(RF)

RFSH DeLy From Rasing Edge of Otxk. RFSH High

150

nsec

vi B JUpr

WAIT

‘s (WT)

WAIT Setup Time to Falling Edge of Clock

7°

nsec

HALT

'D(HT)

HALT Delay Time From Falling Edge of Clock

300

nsec

C L = SOpF

iNT

'* (IT)

IFT Setup Tim* to Raung Edge of Cluck

nsec

nmT

•w(NMU

Pulse Width. NMi Low

nsec

BUSRQ

l »(B0>

8USRQ Setup Time to Rasing Edge of Clock

nsec

BUSAK

'DL(BA)

BL'SAK Delay From Rasing Edge of Oock. BUSAK Low

120

nsec

* <AaF

'DH(BA)

BUSaK Delay From Failing Edge of Clock. BUSAK High

nscc

v L Jvpr

reset

's(RS)

RESET Setup Time to Rising Edge of Clock

nsec

«F(C)

DeLy to Float (MREQ. IOKQ. RDand WR)

100

nscc

l rru

Ml Stable Ptiue to IORO (Interrupt Ack.)

(111

nsec

NOUS

A Data thould Kr enabled onto the CPU d ata bu\ when RD is active During interrupt acknowledge data
should be enabled when Ml and IOKQ aie both active
B All ctininil wpuk are internally yynrfttunucd. wr they may be toiaily asynchronous with roped
in i l ie cluck

C". The RESET signal must be act me tor a minimum of 3 clock cycles.

D Output Delay vs. Loaded Capacitance
TA * 70*C Vsv-*5Vi5-f

Add lOnsec delay for each SOpf increase in load up to a maximum of 200pf for the data bus it lOOpf for
address & control lines

h Although'lane by dolpv testing guarantees of -00 »asec maximum

vMota mi

(I2| 'c'Wl^WLl^r^f

‘acm * 'wf4M) • *f m 75

|2| « acl -» c -«0

< 3 1 ’ca-'wmi^r- 40
caf" , wfd.L) 4 ‘r- t)0

don "V 2,0

dd * *w(«>L) + *r “ 2,0

‘cdf * ! w<4>L) * *r - 80

l«l

|S|

I 8 1 *w IMRL) * *e " ^O

l 9 l ‘MMRHl’SMtH^'f - 30

l ,0 « *WWRl.)

t c -40

I**! , m.' :, c M ^H)*'r 80

*,*a»«n

Load circuit for Output

310 APPENDIX E

Copyrighted material

A.C. Characteristics

Z80A-CPU

T a = 0°C to 70°C. Vcc = +5V ± S%. Unless Otherwise Noted.

Signal

Symbol

Parameter

Min

Unit

Test Condition

•c

Dock Period

.25

112)

Jffft

t w (♦H)

Dock Pulse Width, Dock High

nice

t w ($L)

Dock Pulse Width. Dock Low

2000

nice

‘r.f

Clock Rise and Fall Time

mcc

‘D(AD)

Address Output Delay

nice

'F(AD)

Delay to Float

nice

Vi 5

'kid

Address Stable Pnor to MREO (Memory Cycle)

111

nice

f\ a CAmC

‘ad

Addrcu Subfc Prux to \6WQ. RD or WR (I/O Cycle)

Addrcu Subic from RD. \VTR. T6KQ or WFEO

IJI

nice

*ca

"nr

nice

Address Stable From RD or WR During Float

(4J

nice

‘0(D)

Data Output Delay

ISO

rucv

'F(D)

Delay to Float During Write Cycle

nitv

Po-7

«S* (D)
'S*(D)

Dau Setup Time to Rising Edge of Dock During Ml Cyde

nifv

Data Setup Time to Falling Edge of Clock During M2 to M5

nice

C, * 50pF

'dcra

Dau Stable Pnor to WR (Memoty Cycle)

(51

nice

‘dci

Data Stable Prior to WR (I/O Cycle)

(6)

n \€k

‘cdf

Data Stable From WR

Any Hold Time fot Setup Time

nice

»DL*(MR)

MREO Delay From Falling Edge of Clock. MREO Low

nice

MREO

'DH4» (MR)
‘DH4»(MR)

MREO Delay From Rising Edge of Clock. Hr£§ High

nice

MfcEO Delay From Faflmg Edge of Clock. MREO High

nice

C. « SOpF

*w(RRE)

Pulse Width. HR03 Low

nice

‘wfHfifl)

Pulse Width. MR 1.0 High

191

nice

*DL«b(IR)

IORO Delay From Rising Edge of Dock, iORQ Low

nice

(OrO

'DLO(IR)

16RQ Delay From Falling Edge of Clock. IORQ Low

nice

'DHt(IR)

IORQ Delay From Rising Edge of Clock. IORQ High

T0R5 Delay From Falling Edge of Dock. IORO High

nice

Vi jwpr

*DH4> (IR)

nice

l DL* (RD)

RD Delay From Rising Edge of Dock. RD Low

nice

‘DL$ (RD)

RD Delay From Falling Edge of Clock. RD Low

nice

C L ■ 50pF

*DH$(RD)
‘DH$ (RD)

RD Delay From Rising Edge of Clock. RD High

' 85

nice

RD Delay From Falling Edge of Dock. RD High

nsec

‘DLt (WR)

WR Delay From Rising Edge of Dock. WR Low

nice

'DL$ (WR)

WR Delay From Falling Edge of Dock. WR Low

nice

C L -50pF

«DH*(WR)

Wft Delay From Falling Edge of Clock. WR High

nice

•w(wRl)

Pulse Width. WR Low

no!

nice

‘DL (Ml)

M1 Delay From Rising Edge of Dock, M1 Low

100

nice

C L »50 P F

‘DH (Ml)

HI Delay From Rising Edge of Dock. HI High

100

nice

KF5H

‘DL(RF)

RFSH Delay From Riling Edge of Dock. RFSH Low

130

nice

C L -50pF

*DH(RF)

RFSH Delay From Ruing Edge of Clock. RFSH High

120

nice

WaT?

«s(WO

WAIT Setup Time to Falling Edge of Dock

nice

RaET

»D(HT)

HALT Delay Time From Falling Edge of Dock

300

n icc

C L • SOpF

InT

*» (IT)

iRT Setup Time to Rising Edge of Dock

nice

NMl

•w (NML)

Pulse Width. NMl Low

nice

8D5RO

*s(B0)

BUSRQ Setup Time to Rising Edge of Dock

50 !

nsec

BUSaK

‘DL(BA)
‘DH(BA)

6USAK Delay From Rising Edge of Clock. BUSAK Low

100

mcc

r v (hop

&li$AK Delay From Falling Edge of Dock. BUSaK High

100

nice

RESET

•s(RS)

ktSff Setup Time to Rising Edge of Dock

mcc

*F(C)

Delay to Roat (MKEQ. IORQ. RD and W R) I

mcc

‘mr

Ml Stable Prior to IORQ (interrupt Ack.)

nice

t'*l 'c■ '.(♦«) * 'w(*L)♦ ♦ 'r

I'l '.cm
|2) Ijd • t c -70

I J 1 'c ■ V*L) ♦ *1 - 50
{*] ‘caf"V<^L)* , r" 4S
W ‘dcm^c- 170
,6J t dd" t w(*L)' f t T“ 170
,7J *cdf “ 1 *<$L) ♦ l r * 70

I®1 ‘w(MRL) - ‘c -30

M ‘mmRm) “ **<♦»!) ♦ ‘f ’ 20

l'°l VWRL) ■ 'c - 30

l"l V 2 '= 65

NOTES:

A. Data should be enabled onto the CPU d ata bus when RD a active. During mtemipt acknowledge dau
should be enabled whcnHT and iOftQ are both active.

B. All control signals art internally synchioruzed. »o they may be totally asynchronous with respect
to t he clock.

C. The RESET signal must be active foe a minimum of 3 clock cycles.

D. Output Delay vs. Loaded Capacitance

TA - 70‘C Vcc - *5V 15%

Add lOnsec delay for each 50pf increase in load up to maximum of 200pf for data bus and lOOpf for
address & control lines.

E. Although suttc by design, testing guarantees t^^j^ of 200 iitec maximum

Load circuit for Output

312 APPENDIX E

Copyrighted material

Appendix E2 CPU Timing

The Z-80 CPU executes instructions by stepping through a very precise set of a few basic operations.
These include:

Memory read or write
I/O device read or write
Interrupt acknowledge

All instructions are merely a series of these basic operations. Each of these basic operations can take from
three to six clock periods to complete or they can be lengthened to synchronize the CPU to the speed of
external devices. The basic clock periods are referred to as T cycles and the basic operations arc referred to
as M (for machine) cycles. Figure 0 illustrates how a typical instruction will be merely a series of
specific M and T cycles. Notice that this instruction consists of three machine cycles (Ml, M2 and M3). The
first machine cycle of any instruction is a fetch cycle which is four, five or six T cycles long (unless length¬
ened by the wait signal which will be fully described in the next section). The fetch cycle (Ml) is used to
fetch the OP code of the next instruction to be executed. Subsequent machine cycles move data between
the CPU and memory or I/O devices and they may have anywhere from three to five T cycles (again they
may be lengthened by wait states to synchronize the external devices to the CPU). The following para¬
graphs describe the timing which occurs within any of the basic machine cycles.

BASIC CPU TIMING EXAMPLE
FIGURE 0

All CPU timing can be broken down into a few very simple timing diagrams as shown in figure 1
through 7. These diagrams show the following basic operations with and without wait states (wait states
are added to synchronize the CPU to slow memory or I/O devices).

1. Instruction OP code fetch (M1 cycle)

2. Memory data read or write cycles

3. I/O read or write cycles

4. Bus Request/Acknowledge Cycle

5. Interrupt Request/Acknowledge Cycle

6. Non maskable Interrupt Re quest/Acknowledge Cycle

7. Exit from a HALT instruction

APPENDIX E 313

Copyrighted material

INSTRUCTION FETCH

Figure 1 shows the timing during an Ml cycle (OP code fetch). Noti ce that t he PC is placed on the
address bus at the beginning of the Ml cycle. One half clock time later the MREQ signal go es active. At this
time the address to the memory has had time to stabilize so that the falling edge of MREQ can be used
directly as a chip enable clock to dynamic memories. The RD line also goes active to indicate that the
memory read data should be enabled onto the CPU data bus. The CPU samples the data from the memory on
the data bu s with the rising edge of the clock of state T3 and this same edge is used by the CPU to turn off
the RD and MRQ signals. Thus the data has already been sampled by the CPU before the RD signal becomes
inactive. Clock state T3 and T4 of a fetch cycle are used to refresh dynamic memories. (The CPU uses this
time to decode and execute the fetched instruction so that no other operation could be performed at this
time). During T3 and T4 the lower 7 bits of the address bus contain a memory refresh address and the RFSH
signal becomes active to indicate that a refresh read of all dynamic memories should be accomplished. Notice
that a RD signal is not generated d uring ref resh time to prevent data from different memory segments from
being gated onto the data bus. The MREQ signal during refresh time should be used to perform a refresh read
of all memory elements . The re fresh signal can not be used by itself since the refresh address is only guaran¬
teed to be stable during MREQ time.

•1*

- Ml <

T 2

: YC it-

t 3

AO ' A15 ”

1 REFRESH ADOR

MREQ

J \_

•••

WAIT

non v nm H

1_1_

—

r777

UdU s Ut)/ “

r 1 lw j

RFSH

INSTRUCTION OP CODE FETCH
FIGURE 1

Figure 1A illustrates how the fetch cycle is delay ed if th e memory activates the WAIT line. Our-
ing T2 and every subsequent Tw, the CPU samples the WAIT line with the falling edge of <t>. If the WAIT
line is active at this time, another wait state will be entered during the following cycle. Using this technique
the read cycle can be lengthened to match the access time of any type of memory device.

314 APPENDIX E

Copyrighted material

A0-A15 j

T 2

-Ml C

“ ycl*-

T w

T 3

\ ,

\ 1

] REFRESH ADDR.

MREQ

J \

DBO “*■ DR7

wUW l/Wf

_ ~ 1

■i

WAIT

\ j

\ /

\ _

RFSH

INSTRUCTION OP CODE FETCH WITH WAIT STATES

FIGURE 1A

MEMORY READ OR WRITE

Figure 2 illustrates the timing of memory read or write cycles other than an OP code fetch (MI
cycle). These cycles are g enerally three clock p eriod s long unless w ait states are requested by the memory
via the WAIT signal. The MR F.Q sign al and the RD signal are used the same as in the fetch cycle. In the case
of a memory write cycle, the MREQ also becomes active when the address bus is stable so that it can be
used directly as a chip enable for dynamic memories. The WR line is active when data on the data bus is
stable so that it can b e used directly as a R/W pulse to virtually any type of semiconductor memory.
Furthermore the W'R signal goes inactive one half T state before the address and data bus contents are
changed so that the overlap requirements for virtually any type of semiconductor memory type will be met.

•i* —

AO A15

»*-- ^ —

— -UWl.tB — 1

T t

T 2 T 3

y »n uv

t 2

T 3

] MEMORY ADDR

’ MEMORYADDR

.VIREQ

VVR

DATA BUS _

DATA OUT

I} -

IDO •» 071

M g

WAIT _

.J L"__

___ —

_J L”I

MEMORY READ OR WRITE CYCLES

FIGURE 2

APPENDIX E 315

Copyrighted material

Figure 2A illustrates how a WAIT request signal will lengthen any memory read or write opera¬
tion. This operation is identical to that previously described for a fetch cycle. Notice in this figure that a
separate read and a separate write cycle are shown in the same figure although read and write cycles can
never occur simultaneously.

A0-A15

1 -\

T w

t 3

1 i

MEMORY ADDR

•

MREQ

DATA BUS _

1 N

(DO - 07)

M M

DATA BUS

DATA OUT

-1

1 1

WAIT

\ f

~~J

} READ
CYCLE

l WRITE
j CYCLE

MEMORY READ OR WRITE CYCLES WITH WAIT STATES

FIGURE 2A

INPUT OR OUTPUT CYCLES

Figure 3 illustrates an I/O read or I/O write operation. Notice that during I/O operations a single
wai t state is automatically inserted. The reason for this is t hat dur ing I/O operations, the time from when
the IORQ signal goes active until the CPU must sample the WAIT line is very short and without this extra
state sufficient time does not exist for an I/O port to decode its address and activate the WAIT line if a wait
is required. Also, without this wait state it is diffi cult to design MOS I/O devices that can operate at full
CP U spe ed. During this wait state time the WAIT request signal is sampled. During a read I/O operation,
the RD line is used to en able t he addressed port onto the data bus just as in the case of a memory read. For
I/O write operations, the WR line is used as a clock to the I/O port, again with sufficient overlap timing
automatically provided so that the rising edge may be used as a data clock.

Figure 3A illustrates how additional wait states may be added with the WAIT line. The operation
is identical to that previously described.

BUS REQUEST/ACKNOWLEDGE CYCLE

Figure 4 illustrates the timing for a Bus Request/Acknowledge cycle. The BUSRQ sign al is
sampled by the CPU with the rising edge of the last clock period of any machine cycle. If the BUSRQ
signal is active, the CPU will set its address, data and tri-state control signals to the high impedance state
with the rising edge of the next clock pulse. At that time any external device can control the buses 10
transfer data between memory and I/O devices. (This is generally known as Direct Memory Access [DMA]
using cycle stealing). The maximum time for the CPU to respond to a bus request is the length of a machine
cycle and the external controller can maintain control of the bus for as many clock cycles as is desired.
Note, however, that if very long DMA cycles are used, and dynamic memories are being used, the external
controller must also perform the refresh function. This situation only occurs if very large blocks of data are
transferred unde r DM A co ntrol. Also note that during a bus request cycle, the CPU cannot be interrupted
by either a NMI or an INT signal

316 APPENDIX E

Copyrighted material

AO-A7

PORT ADDRESS

IORQ

DATA BUS

Read

Cycle

WAIT

OATA BUS

OUT

\ Write
f Cycle

INPUT OR OUTPUT CYCLES

FIGURE 3

AO - A7

PORT AODHESS

IORQ

DATA BUS

WAIT

READ

CYCLE

DATA BUS

OUT

WRITE

CYCLE

INPUT OR OUTPUT CYCLES WITH WAIT STATES

FIGURE 3A

Automatically inserted WAIT state

APPENDIX E 317

Copyrighted material

A ... U

T 1

— Any m uyuf

last T Slate

9 W

T *

_ _ i

BUSRQ

1 y

Sample- W

Sjmplc

BUSAK

rn MMB MM ■

AO A15

D-

DO - D7 '

U-

-1

MREQ. RO.

-1

Floating

* ■

WR. ior?5.

RFSH

BUS REQUEST/ACKNOWLEDGE CYCLE

FIGURE 4

INTERRUPT REQUEST/ACKNOWLEDGE CYCLE

Figure 5 illustrates the timing associated with an interrupt cycle. The interrupt signal (INT) is
sampled by the CPU with the rising edge of the last clock at the end of any instruction. The signal wil l not be

accepted if the internal CPU software controlled interrupt enable flip-flop is not set or if the BUSRQ signal
is active. When the signal is accepted a speci al M1 cy cle is generated. During this special Ml cycle the 10RQ
signal becomes active (instead of the normal MREQ) to indicate that the interrupting device can place an
8-bit vector on the data bus. Notice that two wait states are automatically added to this cycle. These states
are added so that a ripple priority interrupt scheme can be easily implemented. The two wait states allow
sufficient time for the ripple signals to stabilize and identify which I/O device must insert the response
vector.

ItstM Cycle

L_Ml

0 _

of Intt

ruction

Last T State

t 2

- mi -

T 3

'—

■B MBHP MHV 4%

AHAk A

INT “

A0-A15

"Y REFRESH

MREQ

CT<

IORQ

DATA RIK -|

UH 1 M DUO ■

Li£

WAIT

Lj cl.

INTERRUPT REQUEST/ACKNOWLEDGE CYCLE

FIGURE 5

318 APPENDIX E

Copyrighted material

Figures 5A and 5B illustrate how a programmable counter can be used to extend interrupt
acknowledge time. (Configured as shown to add one wait state)

EXTENDING INTERRUPT ACKNOWLEDGE TIME WITH WAIT STATE

FIGURE 5A

LAST T STATE OF
LAST M CYCLE OF
INSTRUCTION

AUTOMATIC WAIT
T„

I T

USER WAIT
T W

REQUEST/ACKNOWLEDGE CYCLE WITH ONE ADDITIONAL WAIT STATE

FIGURE 5B

APPENDIX E 319

Copyrighted material

NON MASKABLE INTERRUPT RESPONSE

Figure 6 illustrates the request/acknowledge cycle for the non maskable interrupt. This signal is
sampled at the same time as the interrupt line, but this line has priority over the normal interrupt and it can
not be disabled under software control. Its usual function is to provide immediate response to important
signals such as an impending power failure. The CPU response to a non maskable interrupt is similar to a
normal memory read operation. The only difference being that the content of the data bus is ignored while
the processor automatically stores the PC in the external stack and jumps to location 0066u. The service
routine for the non maskable interrupt must begin at this location if this interrupt is used.

HALT EXIT

Whenever a software halt instruction is executed the CPU begins executing NOP’s until an interrupt is
received (either a non maskable or a maskable interrupt while the interrupt flip flop is enabled). The two
interrupt lines are sampled with the rising clock edge during each T4 state as shown in figure 7. If a non
maskable interrupt has been received or a maskable interrupt has been received and the interrupt enable
flip-flop is set, then the halt state will be exited on the next rising clock edge. The following cycle will then
be an interrupt acknowledge cycle corresponding to the type of interrupt that was received. If both are
received at this time, then the non maskable one will be acknowledged since it has highest priority. The
purpose of executing NOP instructions while in the halt state is to keep the memory refresh signals active.
Each cycle in the halt state is a normal Ml (fetch) cycle except that the data received from the memory is
ignored and a NOP instruction is forced internally to the CPU. The halt acknowledge signal is active during
this time to indicate that the processor is in the halt state.

NON MASKABLE INTERRUPT REQUEST OPERATION

FIGURE 6

MEMORY CYCLE FIGURE 7

320 APPENDIX E

Copyrighted material

Appendix E3 Instruction Set Summary

Zilog

ADC HL, ss

Add with Carry Reg. pair ss to HL

ADC A, s

Add with carry operand s to Acc.

ADD A, n

Add value n to Acc.

ADD A, r

Add Reg. r to Acc.

ADD A, (HL)

Add location (HL) to Acc.

ADD A. (IX+d)

Add location (IX+d) to Acc.

ADD A, (IY+d)

Add location (IY+d) to Acc.

ADD HL, ss

Add Reg. pair ss to HL

ADD IX, pp

Add Reg. pair pp to IX

ADD IY, rr

Add Reg. pair rr to IY

AND 5

Logical 'AND' of operand s and Acc

BIT b, (HL)

Test BIT b of location (HL)

BIT b, (IX+d)

Test BIT b of location (IX+d)

BIT b, (IY+d)

Test BIT b of location (IY+d)

BIT b, r

Test BIT b of Reg. r

CALL cc, nn

Call subroutine at location nn if
condition cc if true

CALL nn

Unconditional call subroutine at
location nn

CCF

Complement carry flag

CPs

Compare operand s with Acc.

CPD

Compare location (HL) and Acc.
decrement HL and BC

CPDR

Compare location (HL) and Acc.
decrement HL and BC, repeat
until BC & 0

CPI

Compare location (HL) and Acc.
increment HL and decrement BC

CPIR

Compare location (HL) and Acc.
increment HL, decrement BC
repeat until BC=0

CPL

Complement Acc. (Vs comp)

DAA

Decimal adjust Acc.

DEC m

Decrement operand m

DEC IX

Decrement 1X

DEC IY

Decrement IY

DECss

Decrement Reg. pair ss

Disable interrupts

DJNZe

Decrement B and Jump
relative if B/0

Enable interrupts

EX (SP), HL

Exchange the location (SP) and HL

EX (SP), IX

Exchange the location (SP) and IX

EX (SP), IY

Exchange the location (SP) and IY

EX AF, AF'

Exchange the contents of AF
and AF'

EX DE, HL

Exchange the contents of DE
and HL

EXX

Exchange the contents of BC, DE,
HL with contents of BC', DE', HL'
respectively

HALT

HALT (wait for interrupt or reset)

IMO

Set interrupt mode 0

IM 1

Set interrupt mode 1

IM 2

Set interrupt mode 2

IN A,(n)

Load the Acc. with input from
device n

IN r, (C)

Load the Reg. r with input from
device (C)

INC (HL)

Increment location (HL)

INC IX

Increment IX

APPENDIX E 321

Copyrighted material

INC (IX+d)

Increment location (IX+d)

INC IY

Increment IY

INC (lY+d)

Increment location (lY+d)

INC r

Increment Reg. r

INCss

Increment Reg. pair ss

IND

Load location (HL) with input
from port (C), decrement HL
and B

INDR

Load location (HL) with input
from port (C), decrement HL and
decrement B, repeat until B*=0

INI

Load location (HL) with input
from port (C); and increment HL
and decrement B

INIR

Load location (HL) with input
from port (C), increment HL
and decrement B, repeat until

B=0

JP (HL)

Unconditional Jump to (HL)

JP (IX)

Unconditional Jump to (IX)

JP (IY)

Unconditonal Jump to (1Y)

JP cc, nn

Jump to location nn if
condition cc is true

JP nn

Unconditional jump to location
nn

JP C.e

Jump relative to PC+e if carry-1

JR e

Unconditional Jump relative
to PC+e

JP NC. e

Jump relative to PC+e if carry=0

JR NZ, e

Jump relative to PC+e if non
zero (Z=0)

JR Z.e

Jump relative to PC+e if zero (Z-1)

LD A. (BC)

Load Acc. with location (BC)

LD A, (DE)

Load Acc. with location (DE)

LD A, 1

Load Acc. with 1

LD A, (nn)

Load Acc. with location nn

LD A, R

Load Acc. with Reg. R

LD (BC), A

Load location (BC) with Acc.

LD (DE), A

Load location (DE) with Acc.

LD (HL), n

Load location (HL) with value n

LD dd, nn

Load Reg. pair dd with value nn

322 APPENDIX E

LD HL, (nn)

Load HL with location (nn)

LD (HL), r

Load location (HL) with Reg. r

LD 1, A

Load 1 with Acc.

LF IX, nn

Load IX with value nn

LD IX, (nn)

Load IX with location (nn)

LD (IX+d), n

Load location (IX+d) with value n

LD (IX+d), r

Load location (IX+d) with Reg. r

LD IY. nn

Load IY with value nn

LD IY. (nn)

Load IY with location (nn)

LD (lY+d), n

Load location (lY+d) with value n

LD (lY+d), r
LD (nn), A

Load location (lY+d) with Reg. r
Load location (nn) with Acc.

LD (nn), dd

Load location (nn) with Reg. pair dd

LD (nn), HL

Load location (nn) with HL

LD (nn). IX

Load location (nn) with IX

LD (nn), IY

Load location (nn) with IY

LD R. A

Load R with Acc.

LD r. (HL)

Load Reg. r with location (HL)

LD r, (IX+d)

Load Reg. r with location (IX+d)

LD r. (lY+d)

Load Reg. r with location (lY+d)

LDr.n

Load Reg. r with value n

LD r, r'

Load Reg. r with Reg. r'

LD SP, HL

Load SP with HL

LD SP, IX

Load SP with 1X

LD SP, IY

Load SP with IY

LDD

Load location (DE) with location
(HL), decrement DE, HL and BC

LDDR

Load location (DE) with location
(HL), decrement DE, HL and BC;
repeat until BC=0

LDI

Load location (DE) with location
(HL), increment DE, HL,
decrement BC

LDIR

Load location (DE) with location
(HL), increment DE, HL,
decrement BC and repeat until

BC=0

NEG

Negate Acc. (2's complement)

NOP

No operation

Copyrighted material

ORs

Logical 'OR* or operand s and Acc.

RSTp

OTDR

Load output port (C) with location

(HL) decrement HL and B, repeat
until B=0

SBC A, s

OTIR

Load output port (C) with location
(HL), increment HL, decrement B,
repeat until B=0

SBC HL, ss

SCF

OUT (C), r

Load output port (C) with Reg. r

SET b, (HL)

OUT (n), A

Load output port (n) with Acc.

SET b, (IX+d)

OUTD

Load output port (C) with location

(HL), decrement HL and B

SET b, (lY+d)

OUTI

Load output port (C) with location

SET b, r

(HL), increment HL and decrement

SLAm

POP IX

Load IX with top of stack

SRA m

POP IY

Load IY with top of stack

SRLm

POP qq

Load Reg. pair qq with top of stack

SUBs

PUSH IX

Load IX onto stack

XORs

PUSH IY

Load IY onto stack

PUSH qq

Load Reg. pair qq onto stack

RES b, m

Reset Bit b of operand m

RET

Return from subroutine

RET cc

Return from subroutine if condition
cc is true

RETI

Return from interrupt

RETN

Return from non maskable interrupt

RLm

Rotate left through carry operand m

RLA

Rotate left Acc. through carry

RLC(HL)

Rotate location (HL) left circular

RLC (IX+d)

Rotate location (IX+d) left circular

RLC (lY+d)

Rotate location (lY+d) left circular

RLCr

Rotate Reg. r left circular

RLC A

Rotate left circular Acc.

RLD

Rotate digit left and right between

Acc. and location (HL)

RR m

Rotate right through carry operand m

RRA

Rotate right Acc. through carry

RRC m

Rotate operand m right circular

RRCA

Rotate right circular Acc.

RRD

Rotate digit right and left between

Acc. and location (HL)

Restart to location p

Subtract operand s from Acc. with
carry

Subtract Reg. pair ss from HL with
carry

Set carry flag (C=1)

Set Bit b of location (HL)

Set Bit b of location (IX+d)

Set Bit b of location (lY+d)

Set Bit b of Reg. r
Shift operand m left arithmetic
Shift operand m right arithmetic
Shift operand m right logical
Subtract operand s from Acc.
Exclusive 'OR' operand s and Acc.

APPENDIX E 323

Copyrighted material

GLOSSARY

Accumulator A temporary register where results of calculations may be stored by the
central processor. One or more accumulators may be part of the arithmetic-logical
unit.

Acoustical coupler A device that permits a terminal to be connected to the computer
via a telephone line. It connects to the telephone handset.

Address An identifying number or label for locations in the memory.

Algorithm A step-by-step solution to a problem in a finite number of steps. A specific
procedure for accomplishing a desired result.

ASCII American Standard Code for Information Interchange. Widely used 7-bit
standard code. Also known as USASCI1; IBM uses EBCDIC, which has 8 bits.

Assembler A program that converts symbolic instructions into machine macro-
instructions.

Backplane A board equipped with plugs interconnected by buses into which the
modules that make up a computer may be inserted. Also known as a motherboard.

BASIC Beginner's All-purpose Symbolic Instruction Code. Algebraic language devel¬
oped at Dartmouth College. The language is easy to learn and use.

Binary A numbering system based on multiples of two using the digits 0 and 1.

Bit Abbreviation of binary digit. A single element in a binary number—either a 0 or a
1. Bits are represented in a microcomputer by the status of electronic switches that can
be either on or off. Four bits equal a nibble; eight bits equal a byte.

Byte A group of adjacent bits, usually eight bits, which is operated upon as a unit by
the central processor.

CMOS Complementary Metal-Oxide Semiconductor. Technology that combines the
component density of p-channel MOS (PMOS) and the speed of n-channel MOS
(NMOS). Power consumption is very low.

Clock A device that generates regular pulses that synchronize events throughout a
microcomputer.

Central processor The central processor controls the operation of a microcomputer.
The central processor can fetch and store data and instructions from memory.

CRT Cathode-Ray Tube. An electronic vacuum tube that can be used for graphic dis¬
play. Also refers to a terminal incorporating a CRT.

Compiler A program that translates high-level programming language into machine
language. May produce numerous macro-instructions for each high-level instruction,
unlike an assembler which translates item for item. When using a compiler, one cannot
change a program without recompilation.

Development system A microcomputer system having all the related equipment
necessary for hardware and software development.

Digital Pertaining to discrete integral numbers in a given base which may express all

GLOSSARY 325

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the variables occurring in a problem. Represented electronically by 2 (binary) to 16
(hexadecimal) states at the present time. Contrasts with analog, which refers to a con¬
tinuous range of voltage or current quantities.

Double density Method of doubling bit density on magnetic storage mediums.

Dynamic memory Storage of data on dynamic chips in which storage of a small
charge indicates a bit. Because the charge leaks over time, dynamic memory must be
periodically refreshed.

EBCDIC IBM's 8-bit code, similar to ASCII.

Editor A program that rearranges text. Permits the addition or deletion of symbols
and changes of format.

EIA-RS-232C Interface standard for data transmitted sequentially that is not syn¬
chronous with the central processor.

EPROM Erasable-Progammable Read-Only Memory. A PROM that can be erased
and reprogrammed. Some EPROMs have a quartz window over the chip; data can be
erased by exposure to intense ultraviolet light; other EPROMs may be erased electrical¬
ly.

File A set of related records treated as a unit.

Flag A bit attached to a word for identification or for the purpose of signaling some
condition. Typical microprocessors include carry, zero, sign, overflow and half-carry
status flags.

Floating-point package A set of software routines that allows some microcomputers
to perform floating-point arithmetic without the addition of extra hardware.

_•

FSK Frequency Shift Keying. Technique of transforming bits into two different fre¬
quencies representing 0 and 1 for transmission over telephone or radio lines. The inter¬
face device is called a modem.

Ground Electrical reference point of a circuit.

Hard-copy Printed output on paper.

Hardware The physical components, peripherals, or other equipment that make up a
computer system. Contrast with software.

Hexadecimal A numbering system based on multiples of 16 using the character 0 thru
9 and A thru F. For example, OB hexadecimal equals 0000 1011 binary. One byte may
be encoded in exactly 2 hexadecimal symbols.

High-level language A programming language that is relatively independent of as¬
sembler or machine language. The grammar often resembles English and requires a
compiler or interpreter to convert to executable code. Examples: BASIC, FORTRAN,
COBOL, ALGOL, PL/M, APL.

Instruction A step in a program that defines an operation together with the
address(es) of any data needed for the operation.

Interface A common boundary between two systems or devices. The hardware or
software necessary to interconnect two parts of a system.

Interrupt A break in the execution of a program usually caused by a signal from an

32 6 GLOSSARY

Copyrighted material

external device.

Kansas City standard Refers to a standard for cassette tape recordings of
EIA-RS-232C data. Eight cycles of 2400 Hz equals 1, and 4 cycles of 1200 Hz equals 0.

Least significant bit The binary digit occupying the right-most position in a number
or word, ie: 2° or 1.

LIFO Last-In, First-Out. Method of accessing the most recent entry, then the next
most recent, and so on.

Light pen Photosensitive device that can be used to change the display on a CRT by
generating a pulse at the point of contact.

Machine language Sets of binary integers that may be directly executed as instruc¬
tions by the microcomputers without prior interpretation.

Mass storage Floppy disks, cassettes or tapes used to store large amounts of data.
Less accessible, but larger than main storage.

Memory Storage device for binary information.

Microcomputer A small computer system capable of performing a basic repertoire of
instructions. Includes a central processor, often contained on a single chip, memory,
I/O devices, and power supply.

Microprocessor A central processor on a chip. A complete processor on a single chip,
manufactured using microminiature manufacturing techniques, known as LSI (large
scale integration).

Modem MOdulator—DEModulator. Device that transforms binary data into fre¬
quencies suitable for transmission over telephone lines and back again.

Monitor A program that controls the operation of basic routines to optimize comput¬
er time.

Most significant bit The binary digit occupying the left-most position in a number or
word, usually 2 7 or 128.

Octal A numbering system based on multiples of eight using digits 0 thru 7. Now
largely superseded by the hexadecimal system.

Operating system Software that operates the hardware resources of a microcomput¬
er. The operating system may do scheduling, debugging, I/O control, accounting,
compilation, storage assignment, and data management.

Parity An extra bit that indicates whether a computer word has an odd or even num¬
ber of Is. Used to detect errors.

Peripheral Any piece of equipment, usually an I/O device, attached to the central
processor.

Programmable memory Storage in which access to new information is independent
of the address previously examined.

Read-only memory (ROM) Storage that cannot be altered. The information is writ¬
ten at the time of manufacture.

GLOSSARY 327

Copyrighted material

temporary storage of a computer word during arithmetic, logical, or input/output op¬
erations.

S-100 A 100-pin bus used in the popular 8080/Z80 system.

Software Programs that translate high-level languages into machine language, such
as compilers, operating systems, assemblers, generators, library routines, and editors.

Stack A technique of presenting programs sequentially. A stack is a LIFO structure
controlled by PUSH and POP instructions.

Tiny BASIC The BASIC programming language reduced to a simple form that per¬
mits integer arithmetic and some string operations. Tiny BASIC usually occupies 4 K
or less bytes of memory.

Three-state Capable of existing in three logical states—0 (low), 1 (high), or undefined
(high-impedance), ie: floating.

UART Universal Asynchronous Receiver Transmitter. A transmitter that converts
serial to parallel and vice versa.

Word A set of bits that occupies one storage location and is treated as a unit. May
have any number of bits, but usually 4, 8, or 16.

Word processor A text editor that allows the user to modify text: formats, books, let¬
ters, and reports.

326 GLOSSARY

Copyrighted material

INDEX

Accumulators, 27, 33

ADC, 51, 63

ADD, 49, 63

Addressing, 29, 32-33, 98, 105

capability, 32
high-order, 32
low-order, 32
AND, 34, 54

Arithmetic and Logic Unit (ALU), 21-22. 29
ASCII, 129, 131, 134. 138. 220
BASIC, 12L 183

Binary-coded decimal (BCD), 31, 61, 184
BIT, 75
Bits:
flag. 33

least significant (LSB), 184
manipulation, 32, 75
most significant (MSB), 184
start and stop, 139
Branching:
conditional, 80
unconditional, 79
Buffering, 98
address bus, 99
data bus, 100
Buses, 22

address, 29, 85, 98, 105. 110
architecture, 24
buffering, 98
control, 100
signals, 101
testings, 105

data, 22. 29. 85. 100. 116
bi-directional, 22, 100, 105
drivers, 93, 99-100
testing, 105
power, 98
structures, 22
voltage, 19
Bytes, 32
CALL, 82, 152
Capacitance, 14
Capacitors, 2, S8, 97
bypass, 14
charging time, 5
filter, 2, 4, 14
ripple factor of, 4
input, 14
sizing, 5

time constants of, 6
Carry, 23
flag, 51, 80

Cassettes, 121, 129, 145
interface, 113, 145, 148-149
Kansas City Standard, 146
software, 148
CCF, 60

Characters, 213
format, 214
Chip select, 116
Circuits:

complexity, 21, 23
integrated, 10, 22
layouts, 14
protective, 10
reset, 97
Clocks, 91, 209
periods, 91
real-time, 208
single-stepping, 92,105
testing, 105
COM 8046, 220
COM 2017, 220
Communication, 138
asynchronous, 139. 142
parallel and serial, 138
software, 148
signal levels, 142
standard, 144
Cooling, 17
Control section, 22
Controllers, intelligent, 183
Converters:

analog-to-digital, 184,189
analog to pulse width, 189
binary-ramp counter, 191
successive approximation, 194
3Vi-digit AC/DC, 199
software, 205
digital-to-analog, 184
calibration, 188
multiplying, 186
R-2R, 184

weighted-resistor, 184
Cost, 23
C£, 57
CPD, 48
CPDR, 48
CPI, 47
CPIR, 47
CPL, 60
CRT 8002, 213
CRT 5027, 213
Currents:
continuous, 6
regulator, 5
surge, 6
DAA, 61

Data, 22. 33. 112. 116
acquisition, 198. 208
ASCII, 138
communication, 138
formats, 32

high- and low-order, 33
rates, 142, 148, 220
DEC, 59, 65
Decoding:
hexadecimal, 135
I/O, 91, 105-106, 108
memory, 91, 105-106. 110
testing. 111

Demultiplexers, 108. 206

Central processors (see also Microprocessors), 21-22. 27
architecture, 27
control, 29, 32
registers, 27-29
status, 33
synchronizing, 97
testing, 127
timing, 92

INDEX 329

Copyrighted material

DI, 62

Diodes, 3, 5-6, 97
bridges, 58, 16
silicon, 3
zener, 8, 10

Direct memory access (DMA), 99, 129
Displays:

cathode-ray tube (CRT), 129,138, 213
hexadecimal, 134

light-emitting diode (LED), 93.121, 129,134,153
octal, 134

video, 121. 183. 213
visual, m 134
DJNZ, 82
Drivers:
bus, $3
display, 93
LED, 93
El, 62

8080A, 24, 31, 91
8212, 1QQ
EX, 44
EXX, 44
Fanout, 98
Farads, 5
Flags, 33
carry (C), 51, 80
condition, 33-34
status, 33
zero (Z), 75, 80
Flip-flops, 92, 132
Frequency shift keying (FSK), 146
Full-wave bridges (see also Rectifiers), 3, 5
Fuses, 17
Grounds, 15
buses, 15
common, 14
references, 11
single-point, 15
HALT, 30, 62
Heat sinks, 16
HP7340, 135

IM, 62

IN, 85,122

INC, 58, 64

IND, 87
INDR, 87
Inductance, 14

INI, 86
INIR, 86

Input, 21, 85,122
filters, 33

Input/output, 121, 129
decoding, 91, 105
testing. 111
instructions, 32, 85
ports, 98, 105, 108
read, 106
registers, 91
request, 30, 106
testing, 122. 127
write, 106
Instructions, 21
arithmetic and logical, 31
8-bit, 49

general purpose, 8Q
16-bit, 63

bit manipulation, 32, 75
block transfer and search, 3L 44
call and return, 32, 82,152

CPU control, 32, 60
cycle, 91

exchange, 28, 31, 44

execution, 92
fetch cycle, 29, 91-92
formats, 32

input and output, 32, 85, 88, 122
jump, 32, 78
load, 31
8-bit, 34
16-bit, 39
pop, 43
push, 42
restart, 152

rotate and shift, 31, 66
sets, 33

single-stepping, 92
testing, 105
types, 31
Interfaces:
cassette, 145
tuning, 149
clock, 209
RS-232C, 213
serial, 129, 138. 142
3 Vi-digit AC/DC, 199

testing, 205
Interrupts, 30, 62, 84
non-maskable, 30, 84
page address, 29
JP, 78
JR, 79

Kansas City Standard, 146
Keyboards, 113. 121, 129
ASCII, 129,134
bounce, 132
encoders, 131-132, 220
hexadecimal, 133
input software, 163
KR2376, 220
LD, 34
LDD, 46
LDDR, 46
LDI.45
LDIR, 46

Light-emitting diodes (LED), 93, 121
drivers, 93
Loads, 7, 99
TTL, 93

Logic analyzers, 91, 93, 99
Low-power Schottky TTL (LSTTL), 98
Machine cycles, 29, 91
Memory, 21, 32, 91, 112
addresses, 32, 97, 110
banks, 110,117
contents, 34
decoding, 91, 105, 110
testing. 111

direct memory access (DMA), 99
display and replace, 151, 153
dynamic, 116

erasable-programmable read-only (EPROM), 112 , 115, 152
erasers, 177
programmers, 173
automatic, 174
manual, 173
locations, 28
map, 117
page, 213

programmable, 27 , 110

330 INDEX

Copyrighted material

random-access (RAM), 116
read, 30, ?L 106
cycles, 112

read-only (ROM), 110, 112. 173
character-generator, 213
diode-matrix, 113
programmable (PROM), 112
read/write (RWM), 112, 116
refresh, 29-30, 116
request, 30,116
slow, 92
static, 116

storage, 112, 12L 145
testing. 122
write, 30, 91, 106
cycles, 112
Microcomputers, 21
construction, vii, 22, $1
definition of, 21
design of, 2L 22
single-board, 163
system, 22

Microprocessors (see also Central processors), 21
architecture, 21,22
common, 24
definition of, 22
Z80. 24,22

Monitors (see also Software), 113, 118, 134. 151. 173
cold start, 151
command recognition, 161
execute. 151, 155, 121
keyboard input, 163

memory display and replace, 151,153, 168
register display and replace, 151, 154. 169
restart, 162

serial input/output, 151, 156-157, 159
UART diagnostic, 156
warm start, 151-152. 16Q
Multiplexers, 22, 112
NEG, 60

No operation (NOP), 30, 32, 61-62

Nyquist criterion, 197

Operands, 35

Operating systems, 151

Operation code, 29

OR, 34, 55

Oscilloscopes, 91, 93

OTDR, 90

OTIR, 89

OUT. 88. 122

OUTD.89

OUT1.88

Output, 22. 88, 122
Overflow, 28

Overvoltage protectors, 12
Parity, 28
Pascal, 183

Peak inverse voltages (PIV), 4
Peripherals. 121, 129, 151
synchronizing, 130

POP, 43

Ports, 33. 85. o8 . 105. 108
hexadecimal output, 136
octal. 136

parallel and serial, 129, 183
Power dissipation, 4, 15
Power supplies, 1 ,15
DC, 1

Printed-circuit boards, 21
Programs:

debugging, 153
development, 153
PUSH, 42

Rectifiers (see also Full-wave bridges), 6,14
bridge, 2, 5, 16
full-wave, 3, 5

silicon-controlled (SCR), 18-19
Refresh, 29-30. 116
Registers, 27-28
accumulator (A), 27-28, 33
contents, 34

display and replace, 15L 154
8-bit (B, C, D, E, H, L), 27,112
flag (F), 27-28, 33
general purpose, 28
index (IX, IY), 29
instruction, 29

interrupt page address (I), 29
main and alternate, 28-29
memory refresh (R), 29
pairs, 28. 33. 39

program counter (PC), 28, 32, 78, 82, 152
sets. 27-28

16-bit (BC. DE, HL), 22
special purpose, 28
stack pointers (SP), 28, 42,152
Regulators, voltage (see Voltages, regulators)
Requests, 106
input/output, 106
memory, 106
read, 106
write, 106

RES. 28

Resets, 62, 97, 152
automatic, 92
manual, 92
testing, 105, 122
Resistance, 4, 6, 15
series, 6, 8
thermal, 16
Resistors, 19,185
ladder, 185
variable, 8

Resolution, 184. 187. 198

RET, 83
RETI, 84
RETN, 84
Ripple factor, 4
RL, 68

RI.A, 66

RLC, 62
RLCA, 66

RLD, 74
RR, 20
RRA, 66

RRC, 69
RRCA, 66

RRD, 25

RS-232C, 144, 213
RST, 84, 152
Sample rates, 194, 192
SBC, 53, 64
SCF, 60
SET, 76
78H05, 10, 16
7812, 12
7912, 12

Short-circuits, 18

Sign. 28

Sine waves, 3

INDEX 331

Copyrighted material

6800.24

6502.24
SLA, 71

busing and control logic, 51
pinout, 29

Software (see also Monitors), 24

Z80 Applications Processor (ZAP), vii, 1, 51
testing, 123,12Z

monitor, 151
single-stepping, 52

Zero, 28

flag, 75, 80

SRA, 72
SRL, 23

Stocks, 28, 32, 42, 82,152
Strobes:
data-ready, 130
duration, 132
key-pressed, 139

SUB, 52

Subroutines, 28, 82,118
Surge currents, 6
Terminals, 213
Testing:
dynamic, 127
static, 123

Thermal considerations, 15
Timers, 130
Transformers. 1, 6
primary input to, 3
secondary output from, 3-4
Transistor-transistor logic (TTL), 93, 98, 217
levels, 142
loads, 53

low-power Schottky (LSTTL), 98, 217
outputs, 138, 146
Transistors, 8,17
FAMOS, 115,173
series-pass, 10
wide-band, 14

2114, 117

2102A, 117
2708, 113, 173
2716, 113, 173

Universal synchronous receiver/transmitter (UART), 139, 220
diagnostic, 156
output, 146
pinout, 139

Voltages:

alternating current, 1
comparators, 7-8
control element, 7
direct current (DC), 1
drops, 3, 6, 11,14
input and output, 7,14
loads, 5
peak, 4, 15
peak inverse (PIV), 6
reference, 7, 10

regulators, 1, 3-4, 7, 10, 16
choosing, 10
overloads, 10
series, 8

three-terminal, 9-10
ripple, 45, 14

root mean square (RMS), 3, 6
sine waves, 2
transients, 6
translators, 7-8
VAC, L 3
waveforms, 3-4
Voltmeters, 93, 184,199
Waits, 30, 52
XOR, 56

Z80, 24,27
bus structure, 25

332 INDEX

Copyrighted material

NOTES

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NOTES

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NOTES

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NOTES

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NOTES

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NOTES

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NOTES

BY THE SAME AUTHOR

CIARCIA'S CIRCUIT CELLAR

1979, 128 pages

This volume provides a wealth of imaginative and practical microcomputer projects. Selected from
the popular series in BYTE magazine, topics included D/A conversion, programming EPROMS. AC
remote-controlled appliances, digitized speech, and touch input video display.

CIARCIA'S CIRCUIT CELLAR, VOLUME II

1981, 224 pages

Presented in the same easy-going style and sprinkled with amusing anecdotes, this second volume
offers more practical uses for the home computer. Focused on how microcomputers can be uniquely
interfaced to our environment, projects cover building a computer-controlled home security system,
computerizing appliances, transmitting digital information over a beam of light, building the Intel
8086 microprocessor system design kit, and input/output expansion for the TRS-80.

ALSO FROM BYTE BOOKS

THREADED INTERPRETIVE LANGUAGES

Ronald Loeliger, Senior Analyst with Intermetrics, Inc.

1981, 272 pages

This text on threaded languages (such as FORTH) develops an interactive, extensible language with
specific routines for the Zilog Z80 microprocessor.

BEGINNER'S GUIDE FOR THE UCSD PASCAL SYSTEM

Kenneth L Bowles, Director of the Institute for Information Systems, University of California,
San Diego
1980. 204 pages

Written by the originator of the UCSD Pascal System for users of microcomputers and minicom¬
puters, this book is both an orientation guide to the System and an invaluable reference tool for
creating advanced applications.

THE BYTE BOOK OF PASCAL

Blaise W Liffick, Editor
1980, 334 pages

Written for both potential and experienced computer users, this valuable software resource in¬
troduces the Pascal language and examines its merits and possible implementations.

Copyrighted material

Build Your Own Z80 Computer:

Desi g n Guidelines an d Ap plication Notes

“There is a major need for a book such as this. The information is not readily
available elsewhere. Or anywhere. There are dozens (hundreds?) of microprocessor
books, but nearly all deal with software and treat hardware as abstractions or block
diagrams. Garcia's book is literally filled with very useful and practical “hands-on"
hardware advice, tips and techniques....The book will do for the reader what no
other microprocessor book or manufacturer’s literature I know of does: It will
enable a person to actually buy individual parts and assemble them into a working
microcomputer—with peripherals and options! That’s very important. Too bad we
couldn’t have had such a book years ago.”

—Forrest Mims, III
Contributing Editor of POPULAR ELECTRONICS

“To my knowledge the material covered in this book is not available elsewhere.
There is sufficient detail to enable an individual with previous experience to assemble
a working Z80-based microcomputer from the component level. The design trade¬
offs, the circuits, the software, and the test circuits and procedures are discussed at
a level sufficient for the book to have educational value even if one did not actually
construct a Z80-based system.*'

—Joseph Nichols
Digital Analysis Corporation

About the Author

Steve is a computer consultant, electrical engineer, author of BYTE magazine’s most popular column.
“Garcia's Circuit Cellar.“ and a “national technological treasure.”

ISBN 0-07-010962-1

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