dec :: pdp11 :: memos :: 690204 PDP-11 Instruction Set

^liiOiO INTEROFFICE MEMORANpUM

TO

DATE: February 4, 1969

fi:

mMJUCT. PDP-11 Instruction Set NOs RC:69j08
and B^vived Page 5

Th« attached if the firm, final and irrevocable
instruction eat for the PDP-11 family. Please
^eatrov all information on this subj ect dated .
arior to January 31. 1969. ]i.

Attached also is a revised Page 5 for the BUS

DESCRIPTION memo dated January 29, 1969. -Plea^ V,'jHVJ.;|t?

destroy previous Page 5. !:' ^l ,ii. y^'^:^ '$1^1%

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aiQlTAL EQUIPMENT ••RPQRATt.N . MAYNARD. M AS^Q^Hi^^ffg

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Reviaed Feb. 4, isesTf^

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' '..''' ^)'..}'- -l- m*-' when fiuik ifU| bus ;. ' I, :

ii 111.' uM.. oi tlio bus ].s requeair^rj :.y ,. oovice for data transfer or
othvr uprivition whirh does not affect the processor (DIN, DOT, or'
mn otho.r than to processor) it may gain access to the bus in'the
jiuddU- of .m instruction cycle by asserting ASAP along with its BR •
Ixna. Whon thf processor a) has control of the bus, b) does not ■
have a HiAvo devxco selected, and c) sees NPR asserted, it 'enters
into a PTR sequence if the BR priority is greater or equal to the '
procoa«or priority. Note that by means of the NPR line, a device' '
may obt<n.n the buw before completion of the current instruction. <
'll2IL±£lJi:Sl^±'i r_mny not be interrupted (DTR sequence) at this time '
ThuB, the.- NPT .siqnal must inhibit a device from putting its minor
priorxiy on D 7:0 if it is requesting the bus for processor
interrupt .

l/fU -> [>i feet Tr.insfer

This is ufu?ri to unconditionally transfer control of the bus to
anuthiocpdovi.'e. ft is the means by which the processor executes
nWiii'Aiii'^iitd j-niitructions and by which a device may interrupt the ■ -
pi'occHHur. • ■' ■■ •

1. Mr^tiLer sots C=--6, st^ts D<7:0^to the Device Selection
vcxio (DS) oi the device to which it wishes to transfer
contruL, and sets D^15:B^to the Function Command (PC)
bf'inrj itisuod to the selected device, (the significance
<->i the Device Command is specific to the selected -". .

cir'V ir.'f) ,

'/. M.iNtci- asserts MSYN and negates BBSY. ■ '

:i. All devices see c=-6 and MSYN, and examine D^:0>; ■. ' ' ' "■ '

The selected device examines D^15:8^ (PC) and performs

Acf.'ordinqly. if the selected device requires the bus, -■■.

it: .lasorts BBSY.
4. The ««'lected device asserts SSYN. : ' .■'■.-

'>. Tho fi\afjf.07- sees SSYN and negates MSYN. "' "

6. Th<; HeLected device sees MSYN, negates SSYN. If the

BvUH'tvd device has asserted BBSY, it then becomes master;

otluTW.iao, the processor sees MSYN and SSYN and BBSY

and becomes master.

Nf/ri'J :

Th.- i>rocr-sr,o)- roa[jonds to DS==0. Processor interprets FC as the
<uffh"f^s.s 11, ih*. firBt 256 bytes of rac-mory at which an interrupt
oniry viM.Mcr m located and performa an interrupt via that address.

'''''"■.'"'"';'"''■ '* 'M-"^'.'i;> tu DS-i-'v^e- ■'^'"i^- -onsolo interprets any command
^^' •' "'■'''. ■"•"■' h>'ida tnc; i-An-. ur.lxl inan.:... !. in ,;.jrvcn\:,ion restarts the
"V-"'!'""^. ■- ...icJjt.ir„-,, ,f the h'unct , o.-, Command xs in the range Of PO,^
^" '■'''■ I (.' ' '■' ' ^nsuLe i.'X.immo.s and dxs.jiays the cij.u.onts- of the pro-
'■■'■•"■'•■■' ' ■■ ji'-'- ' vv, Lj. t.-.at adareiis an the last 256

PDP-11 INSTRUCTION SET
January 31, 1969

PDP-11 Instruction Set
RC:69j01 - January 31, 1969
Page 1

I. introduction

The. PDP-11 is a 16-bit small computer. It operates on bytes (8 bits)
or words (16 bits). The memory is byte addressable, to a maximum of
65536 bytes, instructions are one, two, or three bytes (8, 16, 24
bits). Throughout this memo, several conventions will be adhered to:

The term "byte" refers to an 8-bit quantity.

The term "word" refers to two consecutive bytes. The low
order byte is first. in memory.

Numbers are hexadecimal except as noted and when specifying
bit positions within a byte or word.

Bit numbering begins at at the right or low order end of a
byte or word and increases to the left to 7 for a byte or 15
for a word. For example, the high order bit of the accumula-
tor is bit 15.

This memo describes the processor registers, the memory reference
instruction addressing and the six groups of machine instructions -
memory reference, operate, conditional jump, add to register, push/pop

and external.

II . storage Organization

The PDP-11 system has a single bus for memory and input/output
devices. Addresses for memory locations or status registers in
devices are referred to in a similar manner. There are 16 address
bits, allowing locations through 2^6-1 to be assigned to memory
units or input/output devices.

There is no paging as in the PDP-8, but certain locations are reserve<5
for special purposes. Words through 7F are called pageO and may be
referred to from any location by a 2 byte instruction. Words through
ET may be used for interrupt status (described in the next section.

The last 128io bytes (FP80 through FFFF) are called the external page
and are normally assigned to hardware registers in the processor and
input/output devices. The last 16 bytes (FFFO-PFFF) are internal
processor registers.

PDP-11 Instn'uction Set

EC 8 69! 01 - January 31, 1969

Pag© 2

III . ,'' Irocessor^Registers

•I^e PDP-11 has 8 addressable 16-bit hardware registers.

A. Program Counter (P)

15

counter contains the addres

of

prior to each instruction, the program counter contains the address
of the instruction. During the execution it contains t^- -f-- °
?hG next sequential instruction. The program counter itself is
addressable at (FFPC) 16.

B. Status Register (S) ^^^MM^MSSm ^

]^5 8 7 4 3 ^ i U

Bits 7 through 4 of the status,_ register contain ^^^ -^^-^ P^^^f^^^
priority. Bits 3 throtigh contain the condition codes Bits 15 8
arHero if referenced. The status register is addressable at (FFFE) 16,

1. condition Codes j

Bit. 3 through of the status register are called the condition codes.
?iey ar' set according to the results of most instructions^ L (bi,t 0)
is complmentcd as a result of carry out from the adder. N (bit 1) is
iJt^reset) if the result of an arithmetic instruction is negative
1nL-n%ative). Z (bit 2) is set (reset) if the result of an arith-
ie^lc operatic; is Lro (non^zero) . Bit- 3 is the input/output flag
^F) It is set by certain devices on conditions determined by the

device .

2. Priority

Rli-a 7 throuqh 4 of the status register determine the priority of _
i"tte sisti i£ it is operating .t a lower priority than the request-

ing device.

C . Ac cumu la t or (A )

A _J

15 ~

This register is used both as an operand and as the result Register

^ormS?- arithmetic instructions . /^^^f ^^ j^^.^^^tJ^Li^ ^^ ^ jLd
^Ar\^rs^P.c^a bv these instructions, it also may oe Gxpiit,iu y

addressed by these

PDP-11 Instruction Set
RC:69:01 - January 31, 1969
Page 3

at location (FFP0) 16.

D. X- Register (X)

3

15

Th^ X-RegiBter is used to provide a hardware push down Ust facxlity.
It may also be employed as a general index register. It ^^^^<=J^
mented or decremented by various instructions below. It may be
explicitly addressed at (FPF8)16.

E. Y- Register (Y)

Skj

15

This register is a general index register. It may be explicitly

addressed at (FFFA)16.

p. General Registers (K, M, N)

N

M

K

15

The aenoral registers are three hardware 16-bit registers useable by
Se progra.1 tot temporary address or data storage They are normally

addressod in the mode described ^-1°^/" ^^^f °" ]l^.^l][^ (M6) "'
K, M, N may be explicitly addressed at (FFF2)16, (Ftl.4)16, {itt'ojxo,

respectively. .

IV'.' >^m£i^ry;_ Reference instruction Addressing

j— ■■••■•'N/"'~"T

M

4 3 10

Each memory reference instruction consists of one, two or three bytes.
Se f rs? byte is called the instruction byte. Successive bytes, if
^nv contain either address information or data. The operation code
Tol') is In the range of through (C)16. The mode bits (M) determine
the^ddresB cLputation.' The deferred bit , (D) specifies whether the
address is to be deferred one level indirectly.

A. Relative Addressing

Q

OP

1 10 jp]

15

8 7

4 3 10

The rs complement offset quantity Q is added to ^^^ f ^f^-^^^^f,:!
to form an effective address which is in the range (-80, 4-71) 16 rela

tivc to the program counter,

PDP-11 Instruction Set
RC}69;01 - January 31, 1969
Pag© 4

B. Page j2f Addressing

15 "14"

_op 1 111 Td>

^f

8 7 4 3

1

OP

Q ie used to form an address in the range (0,^?F-)16
C. Full Addressing .1, , ^

Q is taken as a full 16-bit address. This address mode cannot be

OOOlj

8 7

4 3

deferred

D. immediate Addressing

OP

0000

23

16 15

8 7

3

The operand is taken directly from the byte or word following the
instruction byte. The operand is a byte or a word de'pending on the
oparation code (see Section V) . This addressing mode may not be
deferred

E. General Register Addressing

\ OP ' I oTxx Id]

"^ I 4 3 2 1 0^^^^.^ ^^^,,

Th«' effective address before deferral is K, M, or N depending on ^ ^ "^^'
whether XX is 01, 10, or 11 respectively. ^^ ^^^^^^l^^^f/!^^^
incr^^ment" ia added to the register w-^e^e^fi ^i e the ef footiv e-aJJ.^oS.
l^it« new effective address also replaces the contents of the register.
The autoincrement is 0, 1, or 2 depending on the instruction (see
Section V) . •

F. External Addressing

1 L

_fi_..

OP I 111

15 14

8 7

4 3

1

in this mode, the high order 9 bits of the effective ^f ^^^^^^^f°^!^^^
deferral are all ones. The low order 7 bits are Q. Thus, the address
range before deferral is (FF8^-FFFF) 16. Input/output and external
devices are typically assigned in this area allowing input/output or
external references in a two byte instruction.

G. X"Xndexed Addressing

Q

OP

100

15

8 7

4 3

1

The effective address before deferral is the sum of the 2-s complement
number Q and the contents of the Y-registcr. This provides a range of
(-00,+7F)16 relative to the contents of X.

PDP-ll Instruction Set
RCs 69:01 '- January 31, 1969
Page 5

H. y-lndexea Addressing L,_iZjIl-5£~".-^^^

^y-~--~Q 7 4 3

^.e affective address, ^^f "/^f "f i^J^Ster ^^iTjJ^JTl"''
ment number Q and the contents of the ^"^^9^^^;- ^ .
range of (^80,4-7F)16 relative to the contents of Y.

V. Memory Reference in fit.ruction Groug

Bit« 3-0 are defined by the address ^ode as discUBsed in Section IV

above .

A. Load Byte (LDB) ^LCZEZSI^

'^^<^^^>*^j^^!^'^'^^^^'^ ' . . i_x.„ -7 +.v,vi-inrf"h n of the accumulator.

Thc^^ecCriT byte is lf^<5^^,/"*° ,^^'= ' 's emended through bits 15-8
Th« high order bit of the effective byte " J=<*Jf ^« ^l „j the
ef the acc.,.uUtor.^ L xs -t a Kected . ^1^^%^^^.^^ ^^,3 ,, ,,,„

effective byte. Z is set t.o one v-'-c,^ /
(non-aero). The autoincrement is one. ^ ^

aZ13 ■ .

B. Load Word (LDW)

0011

TT"^"" 1

^ 4o ^r.■,r\e'ci into the accumulator. L is not changed,
inie effective word is 1°^^®°^'-''^° ^''^^^. 2 is set to one (zero) if

±. x^it. It: v-.f +-hp effective wora . ^ -i-» oi_i- ^^
N is set to bit 15 of the eiiec autoincrement is two.

the effective word is zero (non-zero).

C. Store Byte (STB) {lO^IOIIKlJ^

The contents of accumulator ^^^^ J^^;;-^J^,LteI''?h:^utoS;:r:mf:t'
tive byte. The condition codes are not affectea.

is one.

D. Store Word (STW) |i00lZI].,^-J?1_J3

7 '" "'4 3 10

Lo contents of the accumulator are stored in the effective word.. Tl.e
The contents oi ^ne effected. The autoincrement is two.
condition codes are not arrccx-tu.

l4jo aJ^ '^'' ^ /W^^^'^^ '

PDP-11 Instruction Set
RC:69:01 - January 31, 1969
page 6

E. Add Byte (ADB) \2S^£IZILfl^^

4 3 10

r^;?;r.:a"rtSTpLa;3.on causes ^ -^V °ut. o. .U zero o. t.e
:^f <;.r:;,"./:L"er:?."if ;:« <r.:Lr ro"au.oin=.e.e„. .3 one.

P. Add word (ADW) ^^^21-.l-IIf^^^--4^^

•J 4 3 i "J

co.„pla.nontea if the °P-^J-" ^^/bit ^^tL "eoult! Z is set to
:r <;e/o,"i/ e' e utt'^if .:" ,no„-..ro, . The autoino.e.ent i. two.

G.

compare Byte (CPB) JOIOO IXIKIX?1

•7 4 3 i- ^

..e rs co.ple.ent of the accun. later and t.e effective .yte are^added
together. The effective byte xs ^^^^^'^f^^'^^i^^er but is used to
quantity. The result is "^.f^-^.^^.^^^/If^re Operation causes a
set the condition codes. L ^^ f^'^^^''l''ff° to the high order. bit of
carry out of bit .ero of the adder N J^ ^^^^^^"^^ ,J, (non-zero)
M.C. result. Z is set to one (^ero) if the resuii:

the result.

Tho autoincrement is one

H. compare Word (CPW) \^kl^ Z^-"^^

^e 2.. complement of the ^accumulator and t^je effective^word^are^. ^^^^
added together. The result xs ^°t stored in any g ^^.^^ ^^^^^^

to set the condition codes. L ^^^^"^P^^^.f J^,"J, the high order bit

%^:r^ Tulf Tirs:t1oTneTz: ;) L^Lrxesult if .ero (non-
of the result. -^ is sgl \-u >-'"'= \
zero). The autoincrement is two.

I.

0110

43" 10

^ . ^ :i * ^ i-y.n rontGhf^ of the accumulator bits

T':^:^:^T '^^I'S^J^^ thf::o;.,uU..to. a.e „ot a«ectea.
I f :? chingoa. N is set to the sign ll^J^^ZtZoTlft^rtl^e
B^t to one (.-.ero) if the accumulator is zero (n,on p.cxo)
operation. 'Iljc autoincrement is one.

PDP-11 Instruction Set
RC:69:01 - January 31, 1969
Page 7

J. And Word (ANW)

0111

M

¥.

4 3

1

The effective word is anded to the contents of the accumulator. X

Is not changed. N is sef to one (zero') ' if the result is negative

(non!negative). Z is set to one (zero) if the result is zero (non-
zero). The autoincrement is two.

K. Increment (INC) [lOlO^

M

III

4.3

1

The effective word is incremented by one. L is complemented if the
op ration cLses a carry out of bit zero of f^^^^J " - '^
the high order bit of the result. Z is set to one (zero) if the
result is zero (non-zero). The autoincrement is two.

L. Jump (JMP)

1100

M

D

4 3

1

The effective address replaces the contents of the program counter.
Ihe etiecrive cc ^ affected. The autoincrement is zero.
The condition codes are not eti. j.i-t-i-<^u .

M. Jump to Subroutine (JSR) \^11

3Zm rs

1

The program counter is stored in the word which has the addre s
specified by the contents of the X-register. The X-^regibter is
then incremented by two. The effective address then replaces the
contents of the program counter. The condition codes are not
affected. The autoincrement is zero. |

VI. npprate Ins truction ..Grou£

■ A. NO operation (NOP) ^.J:SIIL±.^JL.^

7 4 3

^

V

^

The program counter is advanced one byte. The condition codes are
not changed.

'W. — Iiicrement Accumulator (lAC)

7"'""'"-"""""4"" 3

[)^£, m> 1^'

The accmnulator is incrc'inontcd by one

L is complemented if the
operation causes a carry out^'of'^bit '^ero of the adder. N is uat
to the high order bit o^ the result. Z is set to one (..ro), it
the result is zero (non-zero) .

5? DP- 11 Iftfit-ruction S©t
RCseSiOl - vJanuary 31, 1969
Paga 8 . .

C. complement .Accumulator (CMA) [ULl-0--|--5ll-|

The contenta of the accumulator and the L bit are replaced by the
S^^Js complement of the origin.! contents. N is set ^^fj^lf,^
order bit of the result. 2; is set to one (zero) if the result
zero (non-zero) .

D. Negate (NEG) OXITIIOJ

fPh,^ 2 'a complement of the accumulator replaces the original ^
Ic umulatoTc^ontents. L is complemented f ^^^^^^.-j;?^ rdeTbi •
^f th. accumulator are non^zero. N xs .et to the ^^9^ -^e^^-^
-tha reBult. Z is set to one (zero) xf the result xs zero ^n

E. Clear Accumulator (CLA)

1111

10

G'

r

ma contents of the accumulator are set to zero. L is not affected.
N is set to zero and z< is set to one.

F. Plus One to Accumulator (PAC)

1111 101

I i^

, accumulator is set to plus one. L is not affected. Both N and

n \^l are set to zero.

.#

/

G. Minus One to Accumulator (MAG) \ l 1 11

110

The accumulator is set to minu? one, l is complemented . N is set
to one and Z is set to zero.

H. Rotate Accumulator Right (RAR) ll_.l„l_l

1 1
3

The L bit and the accumulator are treated as a single 17 bit circular
register! "rhe combination is rotated right one ^-^P-^^^°"^(^3^°;J
i:?o accumulator bit 15 and accumulator bxt^ goes into LNs set
to the high order bit of the result. Z xs set to one izero;
result is zero (non-zero) .

PPP-II Instruction Set
RC:69:01 - January 31, 1969

page ■ 9 . : : .

' I. Rotate Accumulator Left (RAL) [^ 1 ^ 1 . ...L-|.-0-i-ll

.h. L bit ana the -cu.ulator are reate. as a sx xe l^^^^^^^^^^^^.

fha combination is ^^^f f , f f,,°"^,\'.) ^Tis set'to the high order
bit and accumulator bxt 15 ^-^^^^° ^^'^;^)^i, the result is .ero
bit of the result. Z xs set to one k^
(non-zero) . _ _

J. complement Link (CML) [iXi:^IEil_P„-|l

The L bit is complemented. N, Z, and F arej^ot^af fected.
K. Clear condition codes (CCC) [IXl-i-LUlO

The four condition codes (p/ Z. N, L) are set to zero.

VII . CinKlii;ijOTal_JAamEj[-nstri^^

,,e«oLtructions_test ^^ ^^^^^^^^Jo^'^i iT '

There are 16 such ^f ^^^^^^^^^^^f ^"J't The format of these instruc-
thre© conditions and a true/false bic. m

tions is as below: _„„«..^

.-_^— _ — --— - T r~i~o"i JjLMiliEl

L — --^^ -^-r- 4 3 2 1-0

■rnrv f-Tumt) on Conditions True) or JCF (Jump on ■
Wb^^rc. T/E specxfxes JCT (J^ on Con condition code pattern
Conditionr, False) and Z, ^^"^,^^J^^es then the I/O Flag bit (F) is
under test. If Z N L are all ^^^^ '^^^fl^^^ ,, performed on the OR
tested. If the T/F ^^^ xs zero then^^^he ___^^P ^^ ^.^^^^ ^^^

of the indicated ^^^^^i^^^^?" '' ^•^;' F^ thei the test is performed on
or 1.^1". If the T/F ^^%-^:j"tJ'^^^l;/eonditions. Thus, JCF Z L is
the AND of the falsity of the indicated conax

"jump on Z-'-0 and L«0.

. . • «,„!- 4-v.o nffset Q is added as a 2's
If the specified condition xs met, ^he offset u ^ ^f

complement number to the f°^^^"^^^°^f^^^;3,^^';/the condition is. not
(.80,.7F)16 relative to ^^^^/^^^^^^d The 'condition codes themselves
met, the next instruction is executed.

are not affected. _ .

E'DP-ll Xnetruction Set
RCs69:01 - January 31, 3.969
page 10

Mnemonics, for more commonly used conditions tested are:

MNEMONIC

MEANING

VII J

jump on equal

jump on not equal

jump on less than

jump on greater than

jump on less than or equal

jump on greater or equal

jump on link set

jump on link reset

jump on F flag set

jump on F flag reset

JEQ
JNE
JLT
JGT
JLE
JGE

jr..s

JLR
JFS

CONDITION

Z

not Z

N

not N and not Z

N or Z

not N

L

not L

F

not F

A. Add to M (ATM)

1111 I 1100 1

15

8 7

4 3

\q i<n treated as an 8-bit 2's complement number and added to the con-
Lnt. of M L is complemented if the operation causes a carry out
of bit .or; of the adder. N is set to the high order bxt of ..the
rL It. Z is set to one (.ero) if the result is zero (non-zero).

B. Add to N (ATN)

C

Q

1111

1110

15

8 7

4 3

Q is treated as an 8^bit 2's complement number ^"^/f^f ^^^/;, ^^t'
complemented if the operation causes a --/ll^^fj^l^'''-\'ll'',ll ^o
adder. N is set to the high order bit of the lesult. Z is set to
one (zero) if the result is zero (non-zero).

C.

Add to X- Register (ATX) \Z 9 L^-Hil

15 8 7

1000 [
4 3

Q ia treated as an 8-bit 2's complement number ^^^/^^f ^^°/;£ ^^^"
complemonted if the operation causes a carry out ^^ ^^t^/Jf °^ [^^^^
adder. N is set to the high order bit of the result. ,Z is set to one
(^ero) if the result is zero (non-zero).

D. Add to Y>- Register (ATY) [

1111

1010

^ K

8 7

4 3

and added to Y. I. is

O i-. treated as an a-bit 2's complement number

roumemontcd if the operation causes a carry out of bit zero of the

complemented ii , I ^^ _ ^.^^^ ^^^_^^^^ ^.^ ^^ ^^^ result. Z is set to one

fulder .
(x.eTu)

N is set to the
if the rcHuM. ;i s zero

(r)on-zero) .

I'DP>-X3. Instruction Set
RCs69:01 ".January 31, 1969
Pag© 11

IK. PushZESE^JlSHH

rides for moving data words between the

This inBtruction group prov:

general registers and the push down Hot. ^

[rXIllIIIsiG___iJ

A. push Instructions

4 3

1

a.ha contents ot t»e aao.essa.le ha.aware re i.,.. ^^^^f ^^ ^^^^

„o atorod at the aaare.. J^ *f^„^;^=,f f,",;^ Lg is not altered.

t-hen incremented by two. The contenx-e.

S» instructions specifying the registers are.

REG MNEMONIC

. OPERATION

000
001
010
Oil
100
101
110

111

PUA
PUK
PUM
PUN
PUX
PUY
PUP
PUS

Push Contents

of

A

push Contents

of

K

Push Contents

of

M

Push contents

of

N

Push Contents

of

X

Push Contents

of

Y

Push Contents

of

P

Push Contents

of

S

B. pop Instructions

[iILi__piR?-5.-

7 4 3 10

. r V nr^ decremented by two. Then the word at the addrcs.
The contents of X are decrementea ^ hardware register speci-

■in thi? x-^reqister is stored m the addressacic aai. ^
m tne A juyj-n >-<-.i. „„„,, 4 ^^xri vio the rectisters are:

fied toy REG. The instructions specifying tiie reg

REG

000
001
010

oil

100
101
110

111

MNEMONIC

POA

POK

POM

PON

POX

POY

POP

POS

OPER^^TION

Pop Into A
Pop Into K
pop into M
Pop Into N
pop Into X
Pop Into Y
pop Into P
Pop Into S

POI- is t
The innt
routine

,.,,,„„„ instruction corresponding to JSR Cjun-.p to subroutine)
ruction .sequence POS, rOP causes a return fror»

an interrup-t

PDP-11 Inntruction Set

RC :69 s 01 - Jauiuary 31, 1969

Page 12

X.. Kxterrial Transfer (XTR)

This instruction allows the program to control certain devices in the
sviLm The procesBor is device zero ~ a reference to the processor
in an ;xternal instruction causes a programmed interrupt. The console
is device (FF)16 - an external instruction to the console ca.uses a
i^lt. Othir device numbers may be assigned to -^-^f ^^J^^f ;^^ ,^,
elamentB, input/output devices or user equipment. Thefunction of tne
extornal instruction , in these cases depends on the device.

L. _FTOCTXOH COMMAND
24 A

A. Interrupt of Processor

Tbt-a instruction causes the processor to "interrupt' itself ■• -that is,
^ ^ond as if the interrupt had occurred from an -^^^^^^^J^;;^^^; J^,
occurs if the contents of DEVlbE SELECT are ^-^o T^e P^^^^^^^^^^^J^
is Btorod in the location specified by the contents of ^^^J^-^^^JJ^^^^*
The Btatu6 byte is stored in the location which is two greater than
Z contents of the X-register. The FUNCTION COMMAND -^jJ^^^^J^^^^^^^
of the instruction is stored in the location which is three greater .
than the contents of the X-register. The X-register, itself, is
incremented by four.

Tho proconsor resumes operation as determined by a three byte "status m
blorV- which begins at the address with bits 15-8 ^ero and bits ^-^ ?^^
FiNCTION COMMAND. The first two bytes of the ^J^^-^^^^^^^^^^';^: J^^^
the program counter and the third byte becomes the new status byte.y

B. Halt

If DEVICE is {FF)16, the system stops. Condition codes are not
affected.

C. Input/Output Control

if DEVICE refers to an input/output device, the operation of the
instruction is determined by the device.

j?pr~ll InfitJtuctlon set
mt&9i0l " January 31, 1969
page 13

D. Extended Arithmetic References

U th. .aferoncad device is - ^^^^f .^^^^^ ctntrSl!' ^ ^^.^
parfoms the appropriate operation ^^^^^^^^^^^.^^'^^^
?ion format is determined by the referenced unit.

E. Trap

Ion with DEVICE and FUNCTION ^^f^ 'j:^:- ^Yirm^^re programs. The
„en.ted extended °P-/^^f ^^^.f^f^^^Lrf lurtbrth^starting address of a
contents of the v;ord at location zero mu . ,

softv/are trap handler.,

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