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HP 64000 

Logic Development 
System 



Model 64621A 
State Analysis 
Control Board 



HEWLETT 
PACKARD 



CERTIFICATION 

Hewlett-Packard Company certifies that fft/s product met its published specifications at the time of shipment 
from the factory. Hewlett-Packard further certifies that its calibration measurements are traceable to the United 
States National Bureau of Standards, to the extent allowed by the Bureau's calibration facility, and to the calibra- 
tion facilities of other International Standards Organization members. 

WARRANTY 

This Hewlett-Packard system product is warranted against defects in materials and workmanship 
for a period of 90 days from date of installation. During the warranty period, HP will, at its option, 
either repair or replace products which prove to be defective. 

Warranty service of this product will be performed at Buyer's facility at no charge within HP service 
travel areas. Outside HP service travel areas, warranty service will be performed at Buyer's facility 
only upon HP's prior agreement and Buyer shall pay HP's round trip travel expenses. In all other 
cases, products must be returned to a service facility designated by HP. 

For products returned to HP for warranty service. Buyer shall prepay shipping charges to HP and 
HP shall pay shipping charges to return the product to Buyer. However, Buyer shall pay all ship- 
ping charges, duties, and taxes for products returned to HP from another country. 

HP warrants that its software and firmware designated by HP for use with an instrument will ex- 
ecute its programming instructions when properly installed on that instrument. HP does not war- 
rant that the operation of the instrument, or software, or firmware will be uninterrupted or error 
free. 

LIMITATION OF WARRANTY 

The foregoing warranty shall not apply to defects resulting from improper or inadequate main- 
tenance by Buyer, Buyer-supplied software or interfacing, unauthorized modification or misuse, 
operation outside of the environment specifications for the product, or improper site preparation or 
maintenance. 

NO OTHER WARRANTY IS EXPRESSED OR IMPLIED. HP SPECIFICALLY DISCLAIMS THE 
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 

EXCLUSIVE REMEDIES 

THE REMEDIES PROVIDED HEREIN ARE BUYER'S SOLE AND EXCLUSIVE REMEDIES. HP 
SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR 
CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT, TORT, OR ANY OTHER LEGAL 
THEORY. 

ASSISTANCE 

Product maintenance agreements and other customer assistance agreements are available for Hewlett-Packard 
products. 

For any assistance, contact your nearest Hewlett-Packard Sales and Service Office. 



ISSUE A 

SERVICE MANUAL CHANGES 



MANUAL IDENTIFICATION 



Model Number: 64621A 



Date Printed: June 1983 



Part Number: 64621-90903 



This supplement contains important information for correcting manual errors and for adapting 
the manual to instruments containing improvements made after the printing of the manual. 

To use this supplement: 

Make all ERRATA corrections. 

Make all appropriate serial number related changes indicated in the tables below. 

Serial Prefix or Number Mal<e Manual Changes Serial Prefix or Number Make Manual Changes 



ALL 









▲ NEW ITEM 

Model 64621 A is now supported by the Bluestripe program, which means you should no longer 
perform component level troubleshooting on the board whose .part number is listed here. The 
Bluestripe pipeline contains replacement boards for 64000 options made by Hewlett-Packard 
(replacement boards for this instrument are available at the factory). The part number for the 
replacement board is: 



Manual change supplements are revised as often as necessary to keep manuals as current and accurate as possible. 
Hewlett-Packard recommends that you periodically request the latest edition of this supplement. When requesting copies quote 
the manual identification information from your supplement, or the model number and print date from the title page of the 
manual. 



64621-69503 



NOTE 



Date: 7 March 1984 
Page: 1 of 1 




ISSUE A 



Printed in U.S.A. 



BiQH onoj 



HEWLETT 
PACKARD 



NO POSTAGE 
NECESSARY 
IF MAILED 
IN THE 
UNITED STATES 



BUSINESS REPLY CARD 

FIRST CLASS PERMIT NO. 1303 COLORADO SPRINGS. COLORADO 

POSTAGE WILL BE PAID BY ADDRESSEE 

HEWLETT-PACKARD 

LOGIC PRODUCT SUPPORT DEPT. 

Attn: Technical Publications Manager 

Centennial Annex — D2 
P.O. Box 617 

Colorado Springs, Colorado 80901-0617 



FOLD HERE 



Your cooperation in completing and returning this form 
will be greatly appreciated. Thank you. 



READER COMMENT SHEET 



Service Manual, Model 64621 A 
State Analysis Control Board 
64621-90903, June 1983 



Your comments are important to us. Please answer this questionaire and return it to us. Circle the number that best 
describes your answer in questions 1 through 7. Thank you. 



1. The information in this book is complete: 

Doesn't cover enough 
(what more do you need?) 



1 2 3 4 5 



2. The information in this book is accurate: 

Too many errors 1 2 3 4 5 

3. The information in this book is easy to find: 

I can't find things I need 1 2 3 4 5 

4. The Index and Table of Contents are useful: 

Helpful 1 2 3 4 5 

5. What about the "how-to" procedures and examples: 

No help 1 2 3 4 5 

Too many now 1 2 3 4 5 

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Covers everything 

Exactly right 

I can find info quickly 

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Name (optional): 

Job title: , 

Company: 

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Note: If mailed outside U.S.A., place card in envelope. Use address shown on other side of this card. 



3iQH cnod 



HEWLETT 
PACKARD 



NO POSTAGE 
NECESSARY 
IF MAILED 
IN THE 
UNITED STATES 



BUSINESS REPLY CARD 

FIRST CLASS PERMIT NO. 1303 COLORADO SPRINGS. COLORADO 

POSTAGE WILL BE PAID BY ADDRESSEE 

HEWLETT-PACKARD 

LOGIC PRODUCT SUPPORT DEPT. 

Attn: Technical Publications Manager 

Centennial Annex — D2 
P.O. Box 617 

Colorado Springs, Colorado 80901-0617 



FOLD HERE 



Your cooperation in completing and returning this form 
will be greatly appreciated. Thank you. 



READER COMMENT SHEET 



Service Manual, Model 64621 A 
State Analysis Control Board 
64621-90903, June 1983 



Your comments are important to us. Please answer this questionaire and return it to us. Circle the number that best 
describes your answer in questions 1 through 7. Thank you. 



1. The information in this book Is complete: 

Doesn't cover enough 
(what more do you need?) 



1 2 3 4 5 



2. The information in this book is accurate: 

Too many errors 1 2 3 4 5 

3. The information in this book is easy to find: 

I can't find things I need 1 2 3 4 5 

4. The Index and Table of Contents are useful: 

Helpful 1 2 3 4 5 

5. What about the "how-to" procedures and examples: 

No help 1 2 3 4 5 

Too many now 1 2 3 4 5 

6. What about the writing style: 

Confusing 1 2 3 4 5 

7. What about organization of the book: 

Poor order 1 2 3 4 5 

8. What about the size of the book: 

too big/small 1 2 3 4 5 
Comments: 



Covers everything 

Exactly right 

I can find info quickly 

Missing or inadequate 

Very helpful 
I'd like more 

Clear 

Good order 

Right size 



Particular pages with errors? 



Name (optional): 

Job title: 

Company: 

Address: 



Note: If mailed outside U.S.A., place card in envelope. Use address shown on other side of this card. 



HEWLETT 
PACKARD 



SERVICE MANUAL 



MODEL 64621A 
STATE ANALYSIS CONTROL BOARD 



REPAIR NUMBERS 

This manual applies to 6U621A State Analysis Control 
Boards with a repair number prefix of 2311A. For fur- 
ther information on repair numbers refer to 
"Instrvunents Covered by This Manual" in Section I, and 
Section VII for Backdating to earlier Models. 



© COPYRIGHT HEWLETT-PACKARD COMPANY 1982, 1983 
LOGIC SYSTEMS DIVISION 
COLORADO SPRINGS, COLORADO, U.S.A. 



ALL RIGHTS RESERVED 



Majiual Part No. 6U62I-90903 



PRINTED: June 1983 



SAFETY SUMMARY 



The following general safety precautions must be observed during all phases of operation, service, and 
repair of this instrument. Failure to comply with these precautions or with specific warnings elsewhere in 
this manual violates safety standards of design, manufacture, and intended use of the instrument. 
Hewlett-Packard Company assumes no liability for the customer's failure to comply with these requirements. 

GROUND THE INSTRUMENT. 

To minimize shock hazard, the instrument chassis and cabinet must be connected to an electrical 
ground. The instrument is equipped with a three-conductor ac power cable. The power cable 
must either be plugged into an approved three-contact electrical outlet or used with a three- 
contact to two-contact adapter with the grounding wire (green) firmly connected to an electrical 
ground (safety ground) at the power outlet. The power jack and mating plug of the power cable 
meet International Electrotechnical Commission (lEC) safety standards. 

DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE. 

Do not operate the instrument in the presence of flammable gases or fumes. Operation of any 
electrical instrument in such an environment constitutes a definite safety hazard. 

KEEP AWAY FROM LIVE CIRCUITS. 

Operating personnel must not remove instrument covers. Component replacement and internal ad- 
justments must be made by qualified maintenance personnel. Do not replace components with the 
power cable connected. Under certain conditions, dangerous voltages may exist even with the 
power cable removed. To avoid injuries, always disconnect power and discharge circuits before 
touching them. 

DO NOT SERVICE OR ADJUST ALONE. 

Do not attempt internal service or adjustment unless another person, capable of rendering first aid 
and resuscitation, is present. 

DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT. 

Because of the danger of introducing additional hazards, do not install substitute parts or perform 
any unauthorized modification of the instrument. Return the instrument to a Hewlett-Packard Sales 
and Service Office for service and repair to ensure that safety features are maintained. 

DANGEROUS PROCEDURE WARNINGS. 

Warnings, such as the example below, precede potentially dangerous procedures throughout this 
manual. Instructions contained in the warnings must be followed. 



WARNING 



Dangerous voltages, capable of causing death, are present in this Instrument. Use extreme caution when 
handling, testing, and adjusting. 



Model 6k621k - Table of Contents 



Table of Contents 

Paragraph Page 

Section I General Information 

1-1. INTRODUCTION 1-1 

1-U. SPECIFICATIONS 1-1 

1-6. INSTRUMENTS COVERED BY THIS MANUAL 1-3 

1-11. RECOMMENDED TEST EQUIPMENT 1-U 

1- 13. DESCRIPTION 1-U 

Section II Installation 

2- 1. INTRODUCTION 2-1 

2-3. INITIAL INSPECTION 2-1 

2-5. PREPARATION FOR USE 2-1 

2-7. INSTALLATION INSTRUCTIONS 2-1 

2-8. MAINFRAME CONFIGURATION 2-1 

2-13. CARDCAGE SLOT IDENTIFICATION 2-1 

2-19. SYNCHRONOUS EXPANSION BUS (SEB) 2-2 

2-21. INTER MODULE BUS (1MB) 2-2 

2- 23. STORAGE AND SHIPMENT 2-5 

2-2U. ENVIRONMENT 2-5 

2-26. PACKING 2-5 

Section III Operation 

3- 1. INTRODUCTION 3-1 

Section IV Performance Verification 

U-1. INTRODUCTION U-1 

U-7. OPERATION VERIFICATION U-1 

U-8. PERFORMANCE VERIFICATION U-1 

U-11. MANUAL TESTS U-2 

U-12. TEST 1. INPUT THRESHOLD and MINIMUM SWING U-2 

U-13. TEST 2. INPUT THRESHOLD RANGE U-2 

U-lU. TEST 3. MIN CLOCK WIDTH & QUAL SETUP & HOLD TIME U-2 

U-15. TEST U. DATA SETUP & HOLD TIME «c QUAL CLOCK RATE U-6 

U-l6. TEST 5. BNC PORT OUTPUTS U-12 

U-17. TROUBLESHOOTING U-l6 

U-25. TEST 1: MAINFRAME INTRFC. and STIMULUS. LOOP A U-l8 

U-31. TEST 2: CONTROL IC - SHIFT REGISTER. LOOP B U-20 

U-36. TEST 3: CLOCK IC - SHIFT REGISTER. LOOP C U-21 

U-Ul. TEST U: SEQUENCER. LOOP D U-22 

U-50. TEST 5: STATE COUNT. LOOP E U-25 

U-58. TEST 6: TRACE MEMORY. LOOPS F & G U-27 

U-67. TEST 7: OTHER COUNTER TESTS U-29 

U-71. TEST 8: INTERMODULE BUS U-3O 

U-75- TEST 9: STROBE GENERATOR CALIBRATION U-3I 

U-77. TEST 10: THRESHOLD CIRCUIT CALIBRATION U-3I 

U-79. TEST 11: PREPROCESSOR INTRFC. STIMULUS. LOOP H U-31 

U-8U. TEST 12: REAR PANEL PORT STIMULUS. LOOP I U-3I 

iii 



Model 6U62IA - Table of Contents 



Section V Adjustments 



5-1. INTRODUCTION 5"! 

5-U. SAFETY REQUIREMENTS 5"! 

5-6. EQUIPMENT REQUIRED 5"! 

5-7. TEST EQUIPMENT 5-1 

5-8. ACCESSORIES 5"! 

5- 9. PROCEDURE 5-1 

5-11. STROBE GENERATOR ADJUSTMENTS. (TEST 9) 5-1 

5-12. THRESHOLD ADJUSTMENTS. (TEST 10) 5-3 

Section VI Replaceable parts 

6- 1. INTRODUCTION 6-1 

6-3. ABBREVIATIONS 6-1 

6-5. REPLACEABLE PARTS LIST 6-1 

6-7. ORDERING INFORMATION 6-1 

6-10. SPARE PARTS KIT 6-2 

6- 12. DIRECT MAIL ORDER SYSTEM 6-2 

Section VII Manual Backdating 

7- 1. INTRODUCTION 7-1 

7- 3. MANUAL CHANGES 7-1 

CHANGE 1 7-1 

CHANGE 2 7-2 

Section VIII Service 

8- 1. INTRODUCTION 8-1 

8-9. STATE ANALYZER SUBSYSTEM BLOCK DIAGRAM 8-1 

8-13. DESCRIPTION 8-2 

8-3U. CONTROL BOARD BLOCK DIAGRAM 8-6 

8-36. CONTROL BOARD BLOCK DIAGRAM THEORY 8-6 

8-k6. DETAILED CIRCUIT THEORY 8-10 

8-U7. CLOCK TERM GENERATOR 8-10 

8-58. STROBE GENERATOR 8-12 

8-76. SEQUENCER 8-15 

8-95. ANALYSIS CONTROLLER 8-19 

8-116. STATE/TIME COUNTER 8-2k 

8-130. MNEMONICS 8-27 



iv 



Model 6U62IA - List of Figures and Tables 



List of Figures and Tables 

Figure or Table Page 

Section I General Information 

Figure 1-1. Model 6U621A State Analysis Control Board 1-0 

Table 1-1. Specifications 1-1 

Table 1-2. Supplemental Characteristics 1-2 

Table 1-3. Recommended Test Equipment 1-U 

Section II Installation 

Figure 2-1. State Subsystem With 20 Channel Acquisition 2-3 

Figure 2-2. State Subsystem, No 20 Chsmnel Acquisition 2-U 

Section III Operation 

Section IV Performance Verification 

Figure Clock Width Test Configuration U-3 

Figure U-2. Clock Width Rising Edge Waveform U-3 

Figure U-3. Clock Width Falling Edge Waveform U-U 

Figure U-U. Clock Probe Test Connector U-5 

Figure U-5. Setup and Hold Time Test Configuration U-7 

Figure U-6. Setup and Hold Time Waveforms U-9 

Figure U-7. Data Probe Test Connector U-11 

Figure U-8. BNC Port Output Test Configuration U-13 

Figure U-9. BNC Port 1 Waveform U-lU 

Figure U-10. BNC Port 2 Waveform U-I5 

Figure U-11. Automatic Tests U-I6 

Table U-1. Troubleshooting Configurations U-17 

Figure U-12. Mainframe Interface U-I8 

Figure U-I3. Stimulus U-I8 

Figure U-lU. Control IC - Shift Register U-20 

Figure U-I5. Clock IC - Shift Register U-21 

Figure U-I6. Sequencer U-23 

Figure U-I7. State Count U-25 

Figure U-I8. Trace Memory U-27 

Figure U-I9. Other Counter Tests U-29 

Figure U-20. Intermodule Bus U-30 

Signature Tables U-32 

Section V Adjustments 

Figure 5-I. Adjustment Locations 5"5 

Section VI Replaceable Parts 

Table 6-1. Reference Designators and Abbreviations 6-3 

Figure 6-1. Probe Cable Breakdown 6-U 

Table 6-2. Replaceable Parts List 6-5 

Table 6-3. List of Manufacturers' Codes 6-10 



V 



Model 6h621A - List of Figures and Tables 



Section VII Manual Backdating 

Table 7-1. Manual Changes 7-1 

Section VIII Service 

Figure 8-1. State Analyzer Subsystem Block Diagram 8-5 

Figure 8-2. State Analysis Control Board Block Diagram 8-9 

Figure 8-3. Clock Term Generator Block Diagram 8-11 

Figure 8-U. Strobe Generator Block Diagraun 8-12 

Figure 8-5. Strobe Timing Relationship 8-lU 

Figure 8-6. Sequencer Functions 8-I5 

Figure 8-7- Sequencer Block Diagram 8-I8 

Figure 8-8. Analysis Controller Summary 8-19 

Figure 8-9. Analysis Controller Block Diagrajn 8-23 

Figure 8-10. State/Time Counter Block Diagram 8-26 

Table 8-1. Mnemonics 8-27 

Table 8-2. Schematic Diagram Notes 8-UO 

Table 8-3. Logic Symbology 8-Ul 

Figure 8-11. Probe/Preprocessor Interface 8-U3 

Figure 8-12. Strobe Generator 8-U5 

Figure 8-13 . Sequencer 8-I47 

Figure 8-lU. Sequence Occurrence Counter/Memory 8-1+9 

Figure 8-15 • Analysis Controller 8-5I 

Figure 8-I6. Trace State/Time Coimter 8-53 

Figure 8-17 . Trace Count /Status Memory 8-55 

Figure 8-I8. Mainframe Write Interface 8-57 

Figure 8-I9. Mainfrajne Read Interface 8-59 



vi 



Model 6U62IA 



- General Information 




SAC 1-0 



Model 6U62IA - General Information 



SECTION I 
GENERAL INFORMATION 

1-1. INTRODUCTION. 

1-2. This Service Mauiual contains information required to install, test and service 
the Hewlett-Packard Model 6U621A State Analysis Control Board (SAC). Operating in- 
structions are provided in a separate Operating Manual supplied with the instrument. 
It should be kept with the instrvunent for use by the operator. 

1-3. Shown on the title page is a microfiche part number. This number can be used to 
order Ux6-inch microfilm transparencies of the manual. Each microfiche contains up 
to 96 photoduplicates of the manual pages . 

1-4. SPECIFICATIONS. 

1-5. Instrvunent specifications are listed in table 1-1. These specifications are 
the performance standards or limits against which the instrument is tested. Table 
1-2. lists supplemental characteristics. Supplemental characteristics are not 
specifications but are typical characteristics included as additional information 
for the user. 

Table 1-1. Specifications 

Includes Models 6U621A Control Board, 6i+622A 1+0 Channel Acquisition, and 6U623A 20 
Channel Acquisition Boards with General Purpose Probes. 

Unqualified Clock Rate: 25 MHz max. 

Qualified Clock Rate: 10 MHz max. 

Time Count: Accuracy 0.1% or UO ns, whichever is greater. 

Pulse Widths, Setup and Hold Times: all polarities. 
Clock Pulse Width - 20 ns min. 

Clock Qualifier Setup Time - time qualifier must be present prior to active 

edge of clock - 20 ns majc. 
Clock Qualifier Hold Time - time qualifier must remain present auid stable after 

active edge of clock - 0 ns . 
Data Setup Time - time data must be present prior to active edge of clock - 30 

ns max. 

Data Hold Time - time data must remain present and stable after active edge of 
clock - 0 ns. 

BNC Port Outputs (Mainfraune Rearpanel): programmable polarity. 
Stimulus (Port 1) - TTL pulse output into 50 Ohms. 
Occurs at each recognized event. 
Trigger Events, 

Pulse Width 50 ns +/- 20 ns . 
Delay from clock 225 ns +/- 25 ns . 
Sequencer Events , 

Pulse Width 50 ns +/- 20 ns. 



SAC 1-1 



Model 6U62IA - General Information 



Table 1-1. Specifications (Cont'd) 

Delay from clock 200 ns +/- 25 ns . 
Halt (Port 2) - TTL level output into 50 Ohms. 

False at execute, true at event recognition or halt. 
Measurement Complete, 

Delay from clock 225 ns +/- 25 ns. 
Trace Point, 

Delay from clock 225 ns +/- 25 ns. 



Table 1-2. Supplemental Characteristics 

Memory Size: 

Width - expandable to 120 chaiuiels in combinations of 20 aoid/or hO channel ac- 
quisition boards (max 3 ACQ boards). 

Depth - Trace Storage - 256 locations. 

Overview (Model 6I4623A only) - I4O96 locations. 

Sequence: Multiple function control with windows and qualifiers, occurrence, and 
restart . 

Clocks: 8 ORed clocks amd/or qualifiers. 

Interactive Read of Trace Data: up to U.75 MHz qualified clock rate. 

Run Status: 

Waiting for trigger. 
Trace in process. 
Ovei^iew in process. 
Slow clock. 
Measurement complete. 

Overview Functions: (Model 6U623A only). 
Sequencer Windowed/Controlled. 
3 Modes, 

State Data. 

Time Count, start to stop, 8.0 hrs max time within UO ns or 0.1%. 
Event Count, start to stop, count by one from 0 to 611,670; max count 750 
X lOe+9. 
3 Displays , 

Overview Histogram. 
Overview List. 
Overview Graph. 

1MB F\inctions (interconnection with other modules): 
Master Enable (drive, receive). 
Storage Enable (drive, receive). 
Trigger Enable (drive, receive). 
Trigger (drive, receive). 
Delay Clock (drive only) . 



SAC 1-2 



Model 6U62IA - General Information 



Table 1-2. Supplemental Characteristics (Cont'd) 

20 Bit Ranging (Model 6U623A only): 

Applicable to trace or overview fxinctions. 

Four trace ranges or up to 15 overview ranges . 

Range on a contiguous subset of the 20 bits (right justified). 

Trace Coxmt Measurement: 

Windowing of time or state count. 
Stored State to Stored State, 

Time Count - 8.0 hrs max time within 1+0 ns or 0.1%. 

Event Count - count by one from 0 to 611,670, max count 750 X lOe+9. 

Symbol Entry and Output: 

Definition of symbol maps in format specification. 
Use of symbols in Trace specification. 
Trace list uses symbols to present sjnnbolic display. 
Each label may have its own or use another symbol map. 

Probing Versatility: 

General Purpose Probes (Models 6U635A and 6U636A) . 
General Purpose Preprocessor with dedicated interfaces. 

See Model 61t650A General Purpose Preprocessor Manual. 

1-6. INSTRUMENTS COVERED BY THIS MANUAL. 

1-7. Attached to the instrument or printed on the printed circuit board is the 
repair number. The repair number is in the form: OOOOAOOOO. It is in two parts; the 
first four digits and the letter are the repair prefix, and the last five are the 
suffix. The prefix is the same for all identical instruments. The suffix, however, 
is assigned sequentially and is different for each instrument. The contents of this 
meoiual apply to ins+ruments with the repair number prefix (es) listed under REPAIR 
NUMBERS on the title page. 

1-8. An instrvunent manufactured after the printing of this manual may have a repair 
number prefix that is not listed on the title page. This unlisted repair niunber 
prefix indicates that the instrument is different from those described in this 
mainual. The manual for this newer instrument is accompanied by a Manual Changes 
supplement. This supplement contains "change information" that explains how to 
adapt the manual for the newer instrument. 

1-9- In addition to chsaage information, the supplement contains information for cor- 
recting errors in the manual. To keep this manual as current as possible, 
Hewlett-Packard recommends that you periodically request the latest Manual Changes 
supplement. The supplement for this manual is identified with the manual print date 
and part number, both of which appear on the manual title page. Complimentary 
copies of the supplement are available from Hewlett-Packard. 

1-10. For information concerning a repair number prefix that is not listed on the 
title page or in the Manual Changes supplement, contact your nearest Hewlett-Packard 
Office. 



SAC 1-3 



Model 6U62IA - General Information 



1-11. RECOMMENDED TEST EQUIPMENT. 

1-12. Equipment required to maintain the Model 6U621A is listed in Table 1-3 . 

Other equipment may be substituted if it meets or exceeds the critical specifica- 
tions listed in the table. 



Table 1-3. Recommended Test Equipment 

k 1/2 Digit Multimeter accurate to +/-1 mV. (Hewlett-Packard Model 3U66A or 
equivalent . ) 

Hewlett-Packard Model 5OO5A Signature Multimeter. 

Dual Chaiinel 100 MHz Oscilloscope with delta time measurement accurate to O.5 
ns. (Hewlett-Packard Model 17^3A with probes or equivalent.) 

1-13. DESCRIPTION. 

1-lU. The State Analyzer is used to monitor information flow in the data domain. 
The information may be a software program, the actions of a hardware state machine, 
or random logic signals. 

1-15. The State Analyzer consists of one Model 6H621A State Analysis Control Board, 
and from one to three State Data Acquisition Boards. The State Data Acquisition 
Boards may be the kO ChaJinel State Data Acquisition Board, the 20 Channel State Data 
Acquisition Board, or a combination of the two Acquisition Boards. The State 
Analyzer will have the necessary number of Data and Clock Probes for the Acquisition 
Boards used (Models 6U635A and 6U636A) . 

1-16. Up to three Acquisition Boards may be combined to form a State Analyzer with 
as many as 120 channels . 

1-17. Logic Analyzers within one Mainframe may be connected together using the 
Inter Module Bus (1MB). One possible use of the 1MB is to allow a State Analyzer to 
trigger a Timing Analyzer, or another State Analyzer. 



SAC 1-U 



Model 6U62IA - Installation 



SECTION II 
INSTALLATION 

2-1. INTRODUCTION. 

2-2. This section contains information for installing auid removing the Model 6U621A. 
Included are initial inspection procedures, preparation for use, and instructions 
for repacking the instrument for shipment. 

2-3. INITIAL INSPECTION. 

2-k. Inspect the shipping container for dajnage. If the shipping container or 
cushioning material is damaged, it should be kept until contents of the shipment 
have been checked for completeness and the instr\iment has been checked mechanically 
and electrically. Procedures for checking electrical performance are given in 
Section IV. If the contents are not complete, if there is mechanical damage or 
defect, or if the instrument does not pass the Performance Tests, notify the nearest 
Hewlett-Packard Office. If the shipping container is damaged, or if the cushioning 
material shows signs of stress, notify the carrier as well as the Hewlett-Packard 
Office. Keep the shipping materials for carrier's inspection. The HP office will 
arrange for repair or replacement at HP option without waiting for claim settlement. 

2-5. PREPARATION FOR USE. 

2-6. There are no specific preparation for use procedures except the actual instal- 
lation of the boards in the Mainframe cardcage. 

2-7. INSTALLATION INSTRUCTIONS. 

2-8. MAINFRAME CONFIGURATION. 

2-9. Depending on the nvimber of channels required, the State Analysis Subsystem will 
use two or more card slots of the Mainframe cardcage. 

2-10. Due to the way the Mainframe CPU identifies the boards installed in the 
cardcage, the State Control Board (6U621A) should be installed in the lowest num- 
bered card slot available. 

2-11. The 6'4622A Chamnel State Data Acquisition Boards (if any) must be in- 
stalled in the next higher niunbered card slots. See Figures 2-1 and 2-2. 

2-12. The 6k623A 20 Channel State Data Acquisition Board (if any) is installed in 
the next higher numbered slot. See Figures 2-1 and 2-2. 

2-13. CARDCAGE SLOT IDENTIFICATION. 

2-lit. When the CPU finds a State Analysis Control Board in the cardcage, the CPU 
then expects to find either a 20 Chaimel Acquisition Board or a kO Channel 
Acquisition Board in the next higher niimbered slot. 

2-15. The concept of the Control Board being in a lower numbered slot and 
Acquisition Boards in the higher slots is due to the system assigning labels (Pod 1, 
Pod 2, etc.) to the 20 bit groups of information stored in the Acquisition board's 



SAC 2-1 



Model 6I+62IA - Installation 



memory. This is important when connecting the Pods to the User's System, and in 
Preprocessor applications (the software assumes that the information on Pod 1 is the 
Addresses from the User's System). 

2-16. When connecting the Pod Cables to the State Analysis Boards, the Pods should 
be labeled as indicated in Figures 2-1 or 2-2, i.e.. Pod 1 to Pod 1, etc. 

2-17- Up to three Acquisition Boards may be installed with one Control Board forming 
one State Analysis Subsystem. 

2-18. The State Analysis Subsystem configuration must not interfere with the 
Emulation Subsystem (if any) in the highest numbered card slots (some Mainframes may 
not have room for both a State Analysis Subsystem and an Emulation Subsystem). 

2-19. SYNCHRONOUS EXPANSION BUS (SEB). 

2-20. The State Control and Acquisition Boards must be grouped together to allow the 
Synchronous Expainsion Bus (SEB) cable (W3) to connect the Control Board to the 
Acquisition Boards (J2). See Figures 2-1 and 2-2. 

2-21. INTER MODULE BUS (1MB). 

2-22. Some systems may contain more than one State Analysis Subsystem or a combina- 
tion of a State Analyzer and another type of Analysis Subsystem. If this is the 
case, the second State Subsystem is installed in the same mauiner as the first one. 
If the second Analyzer is not a State Analyzer, refer to that Analyzer's Service 
Manual for installation information. The Inter Module Bus (1MB) Cable, WU, is in- 
stalled accross the top of the boards (Jl). See Figures 2-1 and 2-2. 



SAC 2-2 



Model 6U62IA - Installation 



CARD 
CAGE 
SLOT 
NUMBER 



1MB 
CABLE 
W4 



SEB 
CABLE 
W3 



N+3 





J1 

1MB 




J2 
SEB 






DATA CABLE W2 
POD 1 
(J3) 





64623A 

20 CH ACQ 



N+2 



MAXIMUM 

FOUR 
BOARDS 





J1 

1MB 




J2 
SEB 






DATA CABLE W2 
POD 2 

(J3)(A) 




DATA CABLE W2 
POD 3 

(J4)(B) 



64622A 

40 CH ACO 



N+1 





J1 

1MB 




J2 
SEB 






DATA CABLE W2 
POD 4 
(J3)(A) 




DATA CABLE W2 
POD 5 
(J4)(B) 



64622A 
40 CH ACQ 





J1 
1MB 




J2 
SEB 




TOP OR FRONT OF CARDCAGE 


CLOCK CABLE W1 
CLOCK POD 
(J3) 



64621A 
CONTROL 



FOR PREPROCESSORS- 
POD 1 = ADDRESS 
POD 2 = DATA 



POD 5 = DATA 



Figure 2-1. State Subsystem With 20 Channel Acquisition 



SAC 2-3 



Model 6I+62IA - 



Installation 



CARD 
CAGE 
SLOT 
NUMBER 



/ 



N+3 



1MB 




SEB 




CABLE 




CABLE 




W4 




W3 






J1 




J2 






1MB 




SEB 






DATA CABLE W2 




DATA CABLE W2 




POD 1 




POD 2 




(J3)(A) 




(J4KB) 



64622A 
40 CH ACQ 



N+2 



MAXIMUM 

FOUR 
BOARDS 





J1 

1MB 




J2 
SEB 






DATA CABLE W2 
POD 3 
(J3)(A) 




DATA CABLE W2 
POD 4 
(J4)(B) 



64622A 
40 CH ACQ 



N+1 





J1 

1MB 




J2 
SEB 






DATA CABLE W2 
POD 5 
(J3)(A) 




DATA CABLE W2 
POD 6 
(J4)(B) 



64622A 
40 CH ACQ 



N 




J1 




J2 




64621 A 






1MB 




SEB 




CONTROL 



\ 



TOP OR FRONT OF CARDCAGE 

FOR PREPROCESSORS 
POD 1 - ADDRESS 
POD 2 - DATA 



CLOCK CABLE W1 
CLOCK POD 
(J3) 



POD 6 = DATA 



Figure 2-2. State Subsystem, No 20 Channel Acquisition 



SAC 2-U 



Model 6I462IA - Installation 



2-23. STORAGE AND SHIPMENT. 



2-24. ENVIRONMENT. 



2-25. This instrument may be stored or shipped in environments within the following 
limits: 



The instniment should also be protected from temperature extremes which cause 
condensation within the instrument. 

2-26. PACKING. 

2-27. Tagging for Service. If the instrument is to be shipped to a Hewlett-Packard 
Sales/Service Office for service or repair, attach a tag showing owner (with ad- 
dress), complete instnunent repair number, and a description of the service 
required. 

2-28. Original Packing. Containers and materials identical to those used in factory 
packing are available through Hewlett-Packard Offices. Mark the container FRAGILE 
to ensure careful h5indling. In any correspondence, refer to the instrument by model 
number and complete repair number. 

2-29. Other Packing. The following general instructions should be used for repacking 
with commercially available materials: 

a. Wrap instriiment in heavy plastic or paper. (If shipping to Hewlett-Packard 
Office or Service Center, attach a tag indicating type of service required, 
return address, model number, and complete repair number. 

b. Use a strong shipping container. A double wall carton made of 350 pound test 
material is adequate. 

c. Use a layer of shock-absorbing material 70 to 100 mm (3 to U inches) thick 
around all sides of the instrument to provide firm cushioning and prevent move- 
ment inside container. 

d. Seal shipping container securely. 

e. Mark shipping container FRAGILE to ensure careful handling. 

f. In any correspondence, refer to instrument by model number and complete 
repair number. 



Temperature 
Humidity. • . 
Altitude. . . 



-UO Deg C to +75 Deg C 

5% to 80% 

15000 M (50000 ft) 



SAC 2-5 



Model 6U62IA - Installation 



NOTES 



SAC 2-6 



Model 61t621A - Operation 



SECTION III 
OPERATION 

3-1. INTRODUCTION. 

3-2. The operation of the Model 6U621A is a function of the system software. 
Complete operation from the keyboard of the system is beyond the scope of the 
Service Manual. Please refer to the Operator's Manuals for the procedure. 



SAC 3-1 



Model 6U62IA - Operation 



NOTES 



SAC 3-2 



Model 6U62IA - Performance Verification 



SECTION IV 
PERFORMANCE VERIFICATION 

4-1. INTRODUCTION. 

U-2. This section describes the Performance Verification (opt_test) for Model 6h621A 
State Analysis Control Board. This Section consists of three parts; 1. Operation 
Verification, 2. Performance Verification, eaid 3- Troubleshooting. 

k-3. The Operation Verification tests are all automatic and require no test equip- 
ment or dissassembly of the Mainframe. The Operation Verification provides a 90% 
assurance that the Model 6U621A meets all specifications. 

k-k. The Performance Verification tests require test equipment and disassembly of 
the Mainframe. The Performance Verification tests involve manual testing and 
verification of specifications. Therefore, the Performance Verification Tests 
should be mm only by a qualified service person. 

The Performance Verification tests are divided into two parts; 1. automated 
tests, and 2. manual tests. The automated test must all pass before performing the 
manual tests . 



NOTE 

Before running the following tests , insure the boards are in- 
stalled as indicated in Section II of this manual. Both 
Operation Tests and Performance Tests must be run to insure that 
the Model 6U621A meets all specifications after repair. 

k-6. The Troubleshooting portion of this Section describes the tests, shows the dis- 
plays for the tests, decodes the displays, and tells how to use the tests with 
Signature Analysis for troubleshooting. 

4-7. OPERATION VERIFICATION. 

a. Press opt-test. RETURN. 

b. Enter SLOT # of State Control Board. RETURN. 

c. Press rvm all_boards . RETURN. 

d. The status line near the bottom should read "STATUS: lOMHz Verification 
PASSED" . 

e. Run the continuity tests as outlined in Section IV of the Model 
General Purpose Data Probe, and the Model 6I4636A General Purpose Clock Probe 
Service Manuals . 

4-8. PERFORMANCE VERIFICATION. 

U-9. Automated Tests. 

a. Press opt_test , RETURN. 

b. Enter SLOT# of State Control Board , RETURN. 



SAC k-1 



Model 6U62IA - Performaoice Verification 



c. Press run all_boards , RETURN. 

h-10. The status line near the bottom of the display should read "Status: lOMHz 
Verification Passed". If a failure occurred, refer to the paragraph on 
Troubleshooting in Section IV of this meuiual. This manual covers only the tests for 

the Control Board. 

4-11. MANUAL TESTS. 

4-12. TEST 1. INPUT THRESHOLD and MINIMUM SWING. 

Refer to the Model 6U635A and 6U636A Service Manuals for the procedure. 
4-13. TEST 2. INPUT THRESHOLD RANGE. 

Refer to the Model 6U635A and 6U636A Service Manuals for the procedure. 
4-14. TEST 3. MIN CLOCK WIDTH & QUAL SETUP & HOLD TIME. 
Specifications : 

Clock Width: 20 nS at threshold level. 
Qualifier Setup Time: 20 nS. 
Qualifier Hold Time: 0 nS. 
Description: 

This Test verifies that the clock input circuitry functions properly with 
an input signal having a minimum clock width. 

Equipment : 

Pulse Generator HP8OI3B 

Oscilloscope HP1722B or HPI7U3A 



SAC U-2 



Model 6U62IA - Performance Verification 



STATE ANALYZER 



PULSE 
GENERATOR 



STATE 


STATE 


CONTROL 


ACQ. 


BOARD 


BOARD 



CLOCK 
PROBE 



CLOCK 
PROBE 
TEST 
CONNECTOR 

SEE 
FIGURE 4-4. 



CHAN 0 




2.8V 



OV 



Figure 4-1. Clock Width Test Configuration 
- 200n S U 



I— 20nS 

Figure 4-2. Clock Width Rising Edge Waveform 

Procedure: (Need Control Board and at least one Acquisition Board with General 
Purpose Probes . ) 

a. Setup Pulse Generator for waveform in Figure U-2. 

b. Press meas_sys (only if more than one measurement system is installed). 

c. Press state_x. 

d. Press format_specif ication. 

e. Press clock_is rising_edge channel_0 and low_level chajinel_l aind 
low_level channel_2 atnd low_level channel_7. 

f. Press execute. 

g. Verify on trace list that "time count rel" column is .I6 uS, .20 uS, or 
.2k uS. 

h. Repeat for rising edge of chaimel 1 through 7- Set all other clock 
chaoinels to low level. 



SAC I4-3 



Model 6J+621A - 



Performance Verification 



-m 200nS 

2.8V , I 1 I— 

OV I I I I I 

20nS 

Figure 4-3. Clock Width Falling Edge Waveform 
i. Setup Pulse Generator for the waveform in Figure U-3. 

j . Press clock_is falling_edge channel_0 ajid high_level channel_l and 
high_level channel_2 and high_level chauinel_7. 

k. Press execute. 

1. Verify on trace list that "time count rel" column is .16 uS, .20 uS, or 
.2I4 uS. 

m. Repeat for falling edge of channel 1 through chamnel J. Set all other 
clock channels to high level. 



SAC U-U 



Model 6U62IA - Performance Verification 




Jumper wire on RS232 connector. Signal on pins 16, 17, 18, 19, 20, 21, 22, and 23. Signal 
ground pin 15. 



O 




REMAINING PINS OMITTED 
FOR CLARITY 

Connecting BNC to RS232 connector. 

DBM-25P TRW cinch 

BNC connector 

Figure 4-4. Clock Probe Tesi Connector 



1251-0063 
1250-1032 



SAC U-5 



Model 6U62IA - Performauice Verification 



4-15. TEST 4. DATA SETUP & HOLD TIME & QUAL CLOCK RATE. 

Specifications : 

Data Setup Time: 30 nS maximum. 

Data Hold Time: 0 nS. 
Description: 

Since the data inputs are sampled with selected transitions of the clock, 
they must remain stable at the time of the clock to ensure that the 
desired input state is sampled. Data setup and hold time specifications 
define the time period that data inputs must remain stable. Data setup 
time is the time prior to the clock that data inputs must begin to be 
stable; data hold time is the time after the clock when data inputs are no 
longer required to remain stable. This test is to verify that the correct 
state is saunpled when data inputs with minimum setup auid hold time 
requirements are presented to the State Analyzer. 



Equipment: 



Pulse Generators (2) 



HP8OI3B 



Oscilloscope 



HP1722B or HPI7U3A 



SAC U-6 



Model 6U62IA - 



Performance Verification 



STATE ANALYZER 



STATE 


STATE 


ACQ 


CONTROL 


BOARD 


BOARD 



CLOCK 
PROBE 



CHAN 0 



CHAN 7 
GND 



DATA 
PROBE 



CHAN 0 



CHAN 19 
GND 



PULSE 
GEN #1 



PULSE 
GEN #2 



OSCILLOSCOPE 



TRIG + 
IN OUT 



10:1 
PROBE 



4 — » 



TRIG 
OUT 



OUT 



50!! 



CLOCK 
PROBE 
TEST 
CONNECTOR 

SEE 
FIGURE 4-4. 



10:1 PROBE 



<) » 



50!! 



DATA 
PROBE 
TEST 
CONNECTOR 

SEE 
FIGURE 4-7. 



Figure 4-5. Setup and Hold Time Test Configuration 



SAC U-7 



Model 6U62IA - Performance Verification 
Procedure : 

a. Press meas_sys (only if more than one measurement system is installed.) 

b. Press state_x. 

c. Press format_specif ication. 

d. Adjust Pulse Generators 1 and 2 for waveforms A and B respectively as 
in Figure U-6. 



SAC U-8 



Model 6U62IA - Performamce Verification 



h2.8V 



ov 



r2.8V 



ov 



. 100nS- 



lOOnS ^ 



OnS 

HOLDTIME 



200nS 



170nS 



30nS 

SETUP TIME 



100nS- 



lOOnS- 



Figure 4-6. Setup and Hold Time Waveforms 



SAC U-9 



Model 6U62IA - Performance Verification 

e. Press execute. 

f. Verify "lllllH" for data probe under test. 

g. Change Pulse Generator 2 to waveform C. 

h. Press execute. 

i. Verify "OOOOOH" for data probe under test, 
j. Change Pulse Generator 1 to waveform D. 

k. Press format_specif ication. 

1. Press clock_is falling_edge channel_0. 

m. Press execute. 

n. Verify "OOOOOH" for data probe under test, 
o. Chauige Pulse Generator 2 to waveform B. 
p. Press execute. 

q. Verify "lllllH" for data probe under test, 
r. Press clock_is both_edges channel_0. 
s. Press execute. 

t. Verify alternating "OOOOOH" and "lllllH" for data probe under test and 
"time count rel" column is .08 uS or .12 uS. 



SAC U-10 



Model 6U62IA - Performance Verification 



SOLDERED JUMPER 




BNC 
GND 



)jtK><><>00<>C>(>0 c 



o 




-BNC SIGNAL 



Back view, looking at solder cups. Jumper wire on RS232 solder connector. Signal on 
pins 2-6, 8-12, 15-24. Signal ground on pin 25. 



o 



PIN 25- 



r-TT 




PIN 24 



REMAINING PINS OMITTED 
FOR CLARITY 



Side view, connecting BNC to RS232 connector. 



DBM-25P TRW cinch. 
BNC connector 



1251-0063 
1250-1032 



Figure 4-7. Data Probe Test Connector 



SAC I4-II 



Model 6U62IA - Performance Verification 



4-16. TEST 5. BNC PORT OUTPUTS. 
Specifications : 

Stimulus (Port 1): 
Pulse Width: 

Trigger Events: 50 nS +/-20 nS. 
Sequencer Events: 50 nS +/- 20 nS. 
Delay From Clock: 

Trigger Events: 225 nS +/-25 nS, 
Sequencer Events: 200 nS +/-25 nS. 

Halt (Port 2): 

Delay From Clock: 

Measurement Complete: 225 nS +/-25 nS. 
Trace Point: 225 nS +/-25 nS. 

Description : 

Input clock, measure delay to BNCs using am Oscilloscope. 
Equipment: 

Pulse Generator HP8013B 

Oscilloscope HP1722B or HPI7U3 



SAC U-12 



Model 6U62IA - Performance Verification 



STATE ANALYZER 



PULSE 
GEN 



STATE 


STATE 




BNC 


ACQ. 


CONTROL 


1 

0 


PORTS 


BOARD 


BOARD 


2 

9 




CHAN 0 



CHAN 7 
GND 



10:1 
PROBE 



5011 



OSCILLOSCOPE 



(501!) 




A 


B 



CLOCK 
PROBE 
TEST 
CONNECTOR 

SEE FIGURE 4-4. 



Figure 4-8. BNC Port Output Test Configuration 

Procedure for Stimulus (BNC Port 1): 

a. adjust Pulse Generator for 100 KHz (10 uS) square wave, with amplitude 
from 0 V. to +2.8 V. (Clock Threshold is automatically set for TTL = +1.U 
V.) 

b. Press meas_system (only if more than one measurement system is 
installed) . 

c. Press state_x. 

d. Press assert bnc_port_l on all_triggers . 

e. Press execute repetitively. 

f. Press trace_specif ication. 

g. Set Oscilloscope to measure td and tw,as shown in Figure I+-9. 



SAC U-13 



Model 6U62IA - Performance Verification 



SCOPE 
CHAN B 



+ 2.8V 



ov 



225nS +/-25nS 
td 



SCOPE 
CHAN A 



1.4V 



tw 



50nS +/-20nS 
Figure 4-9. BNC Port I Waveform 

h. Verify that Port 1 output for Trigger Events has a time delay (td) of 
225 nS +/-25 nS, and a pulse width (tw) of 50 nS +/-20 nS measured at TTL 
levels (+1.U V. threshold). 



i . 


Press 


halt. 




j- 


Press 


sequence term number 


1 find any state enable. 


k. 


Press 


sequence term number 


2 find any_state disable. 


1. 


Press 


assert bnc_j)ort 1 on 


sequence enable and disable. 


m. 


Press 


trigger on nothing. 




n. 


Press 


execute repetitively. 




0. 


Press 


trace specification. 




P- 


Using 


the Pulse Generator 


set up of previous measurement. 



and tw with the Oscilloscope. 

q. Verify that Port 1 output for Sequence Events has a time delay (td) of 
200 nS +/-25 nS and a pulse width (tw) of 50 nS +/- 20 nS measured at TTL 
levels (+1.U V. threshold). 

Procedure for Fait (BNC Port 2): 

a. Move channel A of the Oscilloscope to Port 2. 

b. Adjust Pulse Generator for square wave of 50 Hz with amplitude from 0 
V. to +2.8 V. (Clock Threshold is automatically set for TTL = l.U V.) 

c. Press halt. 

d. Press trigger on amy_state. 

e. Press trigger position is end of trace. 



SAC U-lU 



Model 61t621A - Performance Verification 



f. Press assert bnc_port_2 on measurement_complete . 

g. Press execute repetitively. 

h. Press trace_specif ication. 

i. Set Oscilloscope to measure td. (Turn Intensity up to see chaamel A.) 

h2.8V 



SCOPE 
CHAN B 
(CLK) 



OV 



225nS +/ 25nS 
td 



SCOPE +^ 4V 

CHAN A 

Figure 4-10. BNC Port 2 Waveform 

j. Verify that Port 2 output for Measurement Complete has a time delay 
(td) of 225 nS +/-25 nS. 

k. Press halt. 

1. Press assert bnc_port_2 on trace_point. 
m. Press execute repetitively, 
n. Press trace_spec if ication. 

o. Using Oscilloscope set up of previous measurement, measure time delay 
(td). 

p. Verify that Port 2 output for Trace Point has a time delay (td) of 225 
nS +/-25 nS. 



SAC k-13 



Model 6U621A - Performance Verification 



4-17. TROUBLESHOOTING. 

4-18. General Comments. If the operation verification failed, troubleshoot the first 
test that failed, then re-mn operational verification. The automatic tests listed 
in Figure U-11 are interdependent so that all tests preceeding a given test must 
pass for the given test to pass. 

10 MHz State Test: Board in Slot ?. Pa<;.<;, lested! 1 f-a:i.ifd! 0 



Test Slot 2! State Control and Clock 
AutoMatic Tests 

1 Mainframe interface and stiMulus 

2 Control IC - shift reqlster 

3 Clock IC - shift register 

4 Sequencer 

5 State count 

6 Trace MeMory 

7 Other counter tests 

8 Intermodule Bus 
Manual Tests 

9 Strobe generator calibration 

10 Threshold circuit calibration 

11 Preproc interface data bus stimulus 

12 Rear panel PORT stimulus 



rested Failed 



0 
0 
0 
0 



0 
0 
0 
0 
0 
0 
0 
0 



Figure 4-11. Automatic Tests 



U-19. Tests 9 and 10 are used in Chapter V, Adjustments. 



NOTE 



There are many TTL-ECL amd ECL-TTL Translators in this product. 
A had TTL level can be mistaken for a good ECL level 1 Please 
pay close attention to the levels when troubleshooting using the 
schematics. Also, a bad TTL input level can cause the entire 
TTL chip to output bad information. 

U-20. Each automatic test is now described, and a signature ajialysis path provided. 
Each SA path works its way from the test output back towards the inputs. To run a 
particular test, press opt_test then RETURN. Press "SLOT #" of the State Control 
board, then RETURN. Finally, press run, "SLOT #" , test, "test # (of first failing 
test)", repeat, then RETURN. Examples of valid commands while operating the State 
Analysis Performance verification are as follows: 

a. "run 1 test 3 repeat RETURN". This runs test 3 repeatedly on the board in 
slot 1, ajid allows signatures to be taken. 

b. "display 2 test 9 RETURN". This displays the results of test 9 for the board 
in slot 2. It does not cause test 9 to run. Various other commands are prompted 
by the softkeys, e.g., "stop" stops the test in progress; "list file_name" 
writes the display to the designated file; "end" causes the prograun to leave 
State Analysis PV and go to option_test PV. 

U-21. VAien a bit pattern is given (e.g. data 00000100) the 1 indicates that bit 2 
has failed. In all cases, a 0 indicates pass and a 1 indicates failure; the msb is 
to the extreme left; all patterns start with bit 0 unless otherwise noted. 



SAC U-16 



Model 64621A - Performauxce Verification 



U-22. The Synchronous Expamsion Bus (SEB) connects the State Control board to State 
Acquisition boards. The SEB is not tested here; it is tested by the automatic tests 
for the State Acquisition boards. Also, the overview functions for the Analysis 
Controller chip are not tested here. 

4-23. Configuration. For the purpose of running P.V. during fault isolation, the 
State Analysis Subsystem can be run in a minimum configuration. The minimum con- 
figuration for the various boards is shown in the following table: 

Table 4-1. Troubleshooting Configurations 

Board Under Test 



Need 


64621A 


64622A 


64623A 


6U62IA 


YES 


YES 


YES 


6U622A 


NO 


YES 


YES 


6U623A 


NO 


NO 


YES 


Clock Probe 


NO 


NO 


NO 


Data Probe 


N/A 


NO 


NO 


SEB 


NO 


YES 


YES 


1MB 


NO 


NO 


NO 


Other Boards 


NO 


NO 


NO 



k-2h. After repairing individual boards, the system must be configured to a standard 
configuration per Section II and pass the "r-un_all_boards" test. This will xincover 
system interaction problems or failures if they exist. Note that the 1MB test using 
a Timing (6U6OOS) Subsystem will pass only if the Timing Subsystem is completely in- 
stalled and correctly cinfigured. 



SAC lt-17 



Model 6U62IA - Performance Verification 



4-2S. TEST 1: MAINFRAME INTRFC. and STIMULUS. LOOP A 

U-26. Purpose -the purpose is two-fold, to verify that the mainframe can control the 
State Control board, and to stimulate the Sequencer and the Clock Threshold D/A 
Converters (DACs). The Strobe Generator is also exercised. 

U-27. How -the Slow Clock Dectector is reset, then a Performance Verification Strobe 
(PPVSTB) is written to the Strobe Generator. This triggers the Slow Clock Detector 
monostable and its status is read at the Analysis Status Buffer. 

U-28. Results -Strobe Request passes if the monostable is read high. Release data 
bus is a read of the mainframe data bus when nothing is addressed. Failure indi- 
cates that a card in the cardcage is causing problems on the data bus. The stimulus 
portion of this test is write only, therefore, no results are given for it. 

10 MHz State test! Board in Slot Z Pass Tested: 1 Failed: 0 

Slot 2; State Control and Clock 

Test 1; MainfraMe interface and stiMulus 

Strobe Request Pass 

Release data bus OQOOOOflOOOOOOOOO 

Figure 4-12. Mainframe Interface 

U-29. Stimulus -A staircase ramp is produced by the DACs (TPll & TP12) during this 
test. See Figure U-I3. The DACs are also stimulated by test 10. The Sequencer is 
exercised in a write-only mode during this test in order to break its feedback 
loops. This test loads the Sequence Transition Memories and the Sequence Occurrence 
Coxinter Memories, then stimulates the Sequencer by operating the Sequence State 
Latch/Counter in the count mode (HLD asserted). Loopback occurs when the State 
Latch/Counter latch the next state from their parallel inputs (HLD is not asserted) . 



20 MS 




+4.2 V 




0 V 



Figure 4-13. Stimulus 



SAC U-18 



Model 6U62IA - Performance Verification 



k-30. Loop A Signature Path for Strobe Request : U121 , U122, U117, U65. 
Loop A signature Path for Release Data Bus: U121, U122. 
Loop A Signature Path for Strobe Generator: U2U, U52, U8, UlOl. 
Loop A Signature Path for DACs: U55, U102, U121. 

Loop A Signature Path for Sequencer: UI6, U80, Occurrence Counter, Occurrence 
Covint Memories, Transition Memories, Sequence State Latch/Counter, Mainframe 
Interface . 



SAC it-19 



Model 6U62IA - Performance Verification 



4-31. TEST 2: CONTROL IC - SHIFT REGISTER. LOOP B 

U-32. Purpose - to verify that the shift register within the Analysis Controller, 
Ul, can be loaded correctly. 

U-33* How -Serial Data is loaded into Ul through pin 20. Pin I8 is the enable and 
pin 19 is the clock. Pin 17, NHC, outputs the sane data 39 clock cycles later. 

U-3U. Results -Register data passes if the shift register overflowed correctly. The 
data is read by the Analysis Status Buffer as the signal NMC (memory complete). 
Shift control refers to the testing of the signal LLD. 

10 MHz State Test: Board in Slot ?. Pass Tested: 1 F-ailed: 0 

Slot 2: State Control and Clock 
Test 2: Control IC - shift register 

Register data 

All O's Pass 

All I's Pass 

Patterns Pass 

Shift control Pass 

NOTE: This tests only the shift register, 

Figure 4-14. Control JC - Shift Register 
lt-35. Loop B Signature Path - U121, U122, Ul, U103, U102. 



SAC U-20 



Model 6U62IA - Performance Verification 



4-36. TEST 3: CLOCK IC - SHIFT REGISTER. LOOP C 

Purpose - to verify that the Clock Term Generator, U25, can be loaded 
correctly. 

U-38. How - Serial Data is loaded into U25 pins 13 and 15 • Pin ik is the clock. 
Pins 26 and 28 output the same data several clock cycles later, and the results are 
read at the Status Buffer. 

U-39' Results -Register input bits passes if the shift register overflowed correct- 
ly. The bits are read as HCDO and HCDl at the Analysis Status Buffer. External 
Clocks is an indirect test which shows that U25 is not activating the Strobe 
Generator . 

10 MHz State Test! Board in Slot 2 Pass Tested-. 1 Failed! 0 

Slot 2! State Control and Clock 
Test 3: Clock IC -• shift register 

Register input bits 10 



All O's 



0 0 



<1 ~ Error) 



All I's 



00 



Patterns 



00 



External Clocks 



Pass 



Figure 4-15. Clock IC - Shift Register 



k-kO. Loop C Signature Path - U121, U122, U25, U102. 



SAC it -21 



Model 6U62IA - Performance Verification 



4-41. TEST 4: SEQUENCER. LOOP D 

k-k2. Purpose - to verify operation of the Sequencer. 

NOTE 

This test contains two feedback loops -UI6 pin 3 to UI7 pin 11 
(LOCCRY) amd Uk2 outputs to UI8 parallel inputs. Signature 
Analysis of feedback loops might fail to isolate the failed com- 
ponent. In that case, use Test 1 which stimulates the Sequencer 
without allowing loopback. Also, all locations of the Sequence 
Transition Memories are not tested. If a Tramsition Memory 
failure is suspected, use Test 1 because it exercises all memory 
locations . 

U-U3. How -With the Sequence State Latch/Counter in the count (load) mode. 
Transition Memories and the Occurrence Memories are loaded. The Analysis Controller 
and the Sequence State Latch/Counter are then put into the run mode, and strobes are 
generated via PPVSTB. The events that follow are complex aaid only an overview is 
given here. The Sequence State Latch/Counter is clocked by PPLS (pipeline strobe) 
which is enabled by the Analysis Controller at U5. The Sequence State is the output 
of the Sequence State Latch/Counter, and is read as TSSO-7 (Trace Sequence State) by 
the Sequence Read Register. 



U-UU. Next, the Sequence Occurrence Counter and Counter Memories are tested. The 
Counter is clocked by PSOCINC. PSOCINC in the run mode is enabled by the Analysis 
Controller at U5. The only output of the Occurrence Counter is Occurrence Carry 
(LOCCRY) it is latched by the Pipeline Latch/Counter auid read as TSSU, using the 
Sequence Read Register. RAM address in Figure U-I6 refers to the output of Ul+2; it 
is also latched by the Pipeline Latch/Coxmter and then read as TSSU-7 by the 
Sequence Read Register. 

Now the plot thickens. The Trace Count/Status Memory Address Counter (MAC) 
and Trace Point bit (LTRCP) are needed to test the outputs of memories U36 and U38 
which are processed by the Analysis Controller. The MAC is cleared, incremented by 
HQWRITE, and read by the Trace MAC Read Register; Figure U-I6 reports this as Memory 
Address. Trace Point is tested by clearing U98, then setting it by having the 
Analysis Controller issue an NTRIG (Trigger). The result, LTRCP, is read by the 
Analysis Status Buffer. 

U-U6. Sequence Addressing in Figure U-I6 is a test of the address lines of the 
Transition Memories. RAM U36 auid the Analysis Controller are loaded so that a walk- 
ing ones address pattern causes U36 to output Sequence Store Qualify (LSSQ) . This 
causes the Analysis Controller to enable HQWRT, provided other Analysis Controller 
inputs are good. Also, HBOTF can cause failures in HSTR signal. HQWRT increments 
the MAC. Now that the Transition Memories and the MAC and LTRCP are known to work, 
additional functions of the Analysis Controller can be tested. The Analysis 
Controller inputs tested are HSTR (Sequencer Trigger), LSTE (Sequencer Trigger 
Enable), LSSE (Sequencer Store Enable), and LSME (Sequencer Master Enable). The 
results are obtained from the NTRIG and HQWRITE outputs of the Analysis Controller. 

U-U7. Results - all results of this test are read at one of three places: the 
Sequence Read Register, the Trace MAC Read Register, or LTRCP at the Analysis Status 
Buffer . 



SAC U-22 



Model 6U62IA - Performance Verification 



10 MHz Slate Test! Board in Slot 2 fass Tested! 1 Failed: 0 

Slot 2! State Control and Clock 
Test 4i Sequencer 

54321 „98765432 10 
State Register Count 00000000 
Load 00000000 

Occur Counter Bits True 0000000000000000 

False 0000000000000000 
RAM Address 00 00 

Mewory Address 00000000, Trace Point Pass 

Sequence Addressing Pass 

Functions 0000 (HSTR ,I.STE,LSSE,L£ME> 

Figure 4-16. Sequencer 

U-U8. Figure k-l6 Interpretation. 

State Register Count 00000000 

(eight bit Sequence State output by U17 and UI8 when clocked by 
NINCSS) 

Load 00000000 
(eight bit Sequence State latched by Ul? and UI8 when HLD is 
not asserted) 

Occur Counter Bits True 0000000000000000 *(No Carry Load) 
False 0000000000000000 
(sixteen bits loaded from U58-U6I into U78,U79,U8l,U82, then 
unloaded through each pin U and gated by U80 and UI6 to 
become LOCCRY) 

RAM Address 0000 
(four bit input to U58-U6I on lines AO -A3) 

Memory Address 00000000, Trace Point Pass 

(outputs of UlOU and UIO5 read at U68, Trace Point is the output 
of U98 read at U122) 

Sequence Addressing Pass 

(bits A0-A7 of U36 tested by output at pin U, LSSQ) 

Functions 0000 (HSTR,LSTE,LSSE,LSME) 

(Ul input pins 2, 37, 36 » 38 tested at Ul output pins U,35) 

* appears on failure of c arry bit on U78 pin k only. 

U-U9- Loop D Signature Path for State Register: U121, U89, U83, U8U, UI7, UI8, U85, 
U52, UlOl. 



SAC U-23 



Model 6U62IA - Performance Verification 



Loop D Signature Path for Occurrence Counter: UI6, U78-U82, U58-U6I, UU2, 
U62-U6U, UI7, UI8. (Note: go to Test 1 for test without loopback) 

Loop D Signature Path for Memory Address: U121, U122, U68, U98, UlOU, UI05, 
U5, Ul. 

Loop D Signature Path for Sequence Addressing and Functions :U1, U36, U38. 



SAC k-2k 



Model 6U62IA - Performance Verification 



4-50. TEST 5: STATE COUNT. LOOP E 

lt-51. Purpose - verify operation of the Trace State/Time Counter U112 in the state 
count mode. 

U-52. How -The Counter temporarily stores data in location 00 (Hex) of the Trace 
Count/Status Memory. That location is read at the Trace Data Read Register. 

U-53- One difficulity with this test is that it requires the Trace Count/Status 
Memory to work before it is tested (Test 6). In particular, the address used to 
write data to the RAMs is not sampled in Test 5 because RAM outputs are sajnpled at 
read time. If Test 5 fails and only RAM outputs are bad, test the Trace 
Coxint/Status Memory Address Selector ajid the Memory Address Counter using signature 
analysis, or run Test 6 and take signatures in both the main loop and the write 
loop. 

lt-5^< The Counter uses the following controls: HQWRT which resets the Counter; PINC 
which increments the count states; LSTATE which puts the Counter in the count states 
mode; HCTST which selects between a 20 bit mode and two 10 bit modes; HCQ T<^ich en- 
ables the Counter; and 25MHz which is used internally by the Covmter. 

U-55- Results -all results for this test are read by the Trace Data Read Register. 
That register receives data from the memory bank selected by the signals LTCSMSO-3 
(Low Trace Count/Status Memory Select). U70, U73 and U90 are not used by this test. 

10 MHz State Tt^st ; Board m Blot Z f'a<-^<-:. 'Ie<:^ted; i l"a;i .lrdi 0 

Slot 2: State Control and Clock 
Test 5: State count 



Reset to 0 



9876543210 9 8 7 6 5 4 3 ? 1 0 
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 



( 1 



Err or ) 



Count enable 



Pass 



10/10 



coont 



Pass 



20 bit count 



Pass 



Output test 
O's 
1 's 



0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 



Figure 4-17. State Count 



SAC it-25 



Model 6U62IA - Performance Verification 



U-56. Figure U-17 Interpretation. 

Reset to 0 00000000000000000000 

(twenty output bits of U112 read from memory: bl9 - bl6 = U93 

bl5 - bl2 = U72 
bll - b8 = U92 
b7 - hk = U71 
b3 - bO = U9I 

Coxint enable Pass 

(test of HCOUNTQUAL) 
10/10 count Pass 

(two ten bit counter mode, selected by HCTST) 
20 bit count Pass (20 bit counter mode) 
Output test 

O's 00000000000000000000 

I's 00000000000000000000 

(same outputs as Reset to 0 above) 

lt-57. Loop E Signature Path: U69, U87, U88, UlOU, UIO5, UIO6, memory RAM's, ECL/TTL 
translators, U112, Ul, U120, UlOO, U102. 



SAC U-26 



Model 6U62IA - Performance Verification 



4-58. TEST 6: TRACE MEMORY. LOOPS F & G 

k-39- Purpose -test Trace Covinter /Status Memory, Tracepoint Register, Wrap bit, and 
Post Trace Point Counter which is a circuit intemal to the Analysis Controller. 

k-60. How -The Memory is 32 bits wide. 20 bits are Counter data, 8 bits are 

Sequence State data and the remaining U bits are for flags. In addition to the 

RAMs, the Memory contains an Address Counter (MAC), and an Address Selector. The 
MAC can be read through the Tracepoint Register and the Trace MAC Read Register. 

U6I. Write Loop. The main loop, loop F, of this test takes signatures when the RAMs 
are being read, and while the RAM addresses are being selected from the CPU via U86 
and a high on the select line of the Trace Count/Status Memoery Address selector. 
The write loop, loop G, allows the RAM addresses to be tested when the Memory 
Address Counter is selected. 

k-62. Previous tests have verified the functioning of the MAC and its associated 
Trace MAC Read Register. Test 3 used the Address Selector and location 00 Hex of 
the memory. Therefore, the most likely failures detected by this test are the 
remaining memory locations, particularly U70, U73» and U90 which were not tested in 
Test 5. 

U-63. Other circuitry tested for the first time include U67 Tracepoint Register, U98 
-Wrap bit, aoid Post Trace Point Counter function of Ul. 

k-6k. Results - all testing results are read at the Analysis Status Buffer U122 
and the CPU Data Buffer U121. 

10 MH7. State Test! Board in Slot 2 Pa<>s 1 tested: 1 failed! 0 

Slot 2: State Control and Clock 
T e s t 6 ! T r ace we « 0 r y 

Error) A d d r e s s B :i t M e f 1 0 r y C h a n e i 

7654321 0 1 0987654321 0987654321 0987654321 0 

AddresB Counter 0000 000 0 

Trace Point Reci 00000000 

Trace Point; Wrap 00 

Store seq state 00000000 

M 0 s t "J. y 1 ' 0 0 0 0 0 0 (•) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 

« 0 1 1 y 0 ' s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 

Ad d r ess 1 es t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 «) 0 0 0 0 

Index Counter Pass 

Figure 4-18. Trace Memory 



SAC I4-27 



Model 6U62IA - Performance Verification 



I1-65. Figure U-I8 Interpretation. 

Address Counter 00000000 

(outputs of UlOU and UIO5 read at U68) 
Trace Point Reg 00000000 

(U67) 

Trace Point, Wrap 00 

(U98 pin 7 and U103 pin 9 respectively) 
Store seq state 00000000 
mostly I's 000000000000000000000000000000 
mostly O's 000000000000000000000000000000 
(32 bit memory read at U69. Bit pattern: b31 - b28 = U71 

b27 - b2lt = U9I 
b23 - b20 = U72 
bl9 - bl6 = U92 
bl5 - bl2 = U73 
bll - b8 = U93 
b7 - bU = U70 
b3 - bO = U90 

Address Test 00000000 OOOOOOOOOOOOOOOOOOOOOOOOOOOOOO 

(indirect test of RAM address bits A0-A7) 
*Index Counter Pass 

(strobe inputs to Ul cause counter to overflow at Ul pin 17) 

*The Index Counter is shown as the Post Trace Point Counter on the 
Block Diagram. 

U-66. Loop F Signature Path:U121, U122, U67-U69, U98, UIO3-UIO5, U86-U88. 
Loop F signature Path for Trace Count/Status Memory: U112, Ul. 



SAC U-28 



Model 6U62IA - Performaoice Verification 



4-67. TEST 7: OTHER COUNTER TESTS. 

U-68. Purpose - verify operation of prescale function and count time mode of Trace 
State/Time Counter. 

lt-69. How - The Counter is incremented by the 25 MHz clock and the count is 
stored in the Trace Count /Status Memory location 00 Hex. 

k-JO. Results - Signature Analyis is impractical because the interval is greater 
than 9 seconds. The only untested signals are HTIMS and LSTATE. HTIMS is a Strobe 
Generator output. LSTATE should oscillate. If all other tests pass, replace the 
Coimter, U112, and rerun the test. 

"1 0 MHz St a t e T e s t ; Boar <:l 1 n S 1 0 1 ',}>. P a <i. s ( e <h ted: 1 P a :i ;i e- d : t) 

S 1. 0 1 2 ! S t <^ t e C 0 n t r 0 1. and C 1 0 c k 
Test 7: Other counter tests 

Prescale 1 Pass 



Pass 



3 



Pass 



Time enable 



Pass 



TiMe reset 



Pass 



Prescale 4 



Pass 



Figure 4-19. Other Counter Tests 



SAC U-29 



Model 6U62IA - Performance Verification 



4-71. TEST 8: INTERMODULE BUS. 

U-72. This test has two parts: internal test using loophack in the i^aljrsis 
Controller, and exteraal test which requires that amother system be connected via 
the Intermodule Bus (1MB) . 

l*-73. Assuming all cables, connections and configurations are correct and working 
properly, failure of this test indicates that the Analysis Controller of one of the 
systems is failing. If no external system is connected, the test will still indi- 
cate pass, provided the internal test passes. 

The State Analysis PV software provides the test 1MB softkey for 1MB testing. 
It selects the board that is to be the Intermodule Bus Driver. 

10 H\-\7. St<3tE? Test! Board in SJot 3 Pass lested: 1 ha;iled: 0 

Slot 3; State Control, and Clock 
Test 81 InterModole-? Bus 

Internal tests 

Master Enable Pass 

Trigger Enable Pass 

Storage Enable Pass 

Tests with 1MB test board No 1MB test board (1 Error) 

Receive ( ME , TE , SE , TR ) 

Drive ( P 0 r 1 1 p 11 1 ses , DC X l< , P 0 r t , P 0 r t i , ME , Tt. , St , I R ) 

1MB test board liwi tat ions (1 -= Not tested) 

Drive < ME , TE , SL , TR ) 

Receive (Portl p u Lses , OCl k , P or t2 , P or t I ,ME,TE,SE.,TR ) 

Figure 4-20. Intermodule Bus 



SAC U-30 



Model 6U621A - 



Performaince Verification 



4-75. TEST 9: STROBE GENERATOR CALIBRATION. 

k-76. This test is a stimulus to the Control Board only. It is used in Section V 
for calibration of the Strobe Generator. See Section V. 

4-77. TEST 10: THRESHOLD CIRCUIT CALIBRATION. 

U-78. This test is a stimulus to the Control Board only. It is used in Section V 
for calibration of the Threshold Circuit. See Section V. 

4-79. TEST 11: PREPROCESSOR INTRFC. STIMULUS. LOOP H 

lt-80. Purpose - to verify that the Control Board can write to the Preprocessor. No 
data is read from the Preprocessor. 

k-81. How -When LMS is activated, the address and data information on the CPU bus is 
loaded into U26 and U53 and read at the outputs of U26 auid U53. At the same time 
the control signals are read at the outputs of UI29. 

U-82. Results - All results of this test are read at the Address Latch UllB, or the 
CPU Data Buffer U121. 

U83. Loop H Signature Paths: 

U26, UII8, UI27, U53 

ui, U123, U65, UI16, U96, UI19, U127, U120, U99, U129. 

4-84. TEST 12: REAR PANEL PORT STIMULUS. LOOP I 

U85. Purpose - to verify that the control board writes to PORTl and P0RT2 on the 
rear panel of the Mainframe. 

U86. How - there are two sections to this test: 

1. The PHALT signal is activated and sent to BNC2 when the control signal, PWRUN, 
goes high. This latches LABI, Low Address Bus 1, into the Port Latches (U97) • 

2. The PSTIM signal is activated and sent to PORTl when NTRIG, Negative Trigger, 
from Ul goes low. This occurrs each time the trigger event is encountered. 

U-87. Loop I Signature Path: 

Ul, U97, UI23, UII6, UI26. 



SAC U-31 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 Test 1: Loop A - VH = 8U24 



MODE: 


EDGES: 




THRESHOLDS: 




CONNECTIONS: 








Normal 


Clock - 


Positive 


Data - High ** 


ST/SP/Start 


- TPI9 








Start - 


Positive 


Data - Low 


#» 


Qual/Stop - 


TPI9 








Stop - 


Negative 


Clock - TTL 


Clock - U99 pin 3 












ST-SP-QL - 


TTL 




1 (TP) 






** = levels are 


TTL except where noted. 










U 1- 7 


PHI5 


ECL 


U 18- 2 


62FC 


ECL 


U 21-10 


nnnn 




u 1-30 


PHI5 


ECL 


U 18- 3 


65A6 


ECL 


TOTLZ = 


1 

X 




u 1-36 


PHI5 


ECL 


u 18- 5 


high 


KPT. 




nnnn 


EPT. 


U 1-37 


I4778 


ECL 


U 18- 6 


1A92 


ECL 




1 

X 




u 1-38 


U778 


ECL 


U 18- 7 


7FCH 


ECL 




nnnn 




U 1-39 


high 


ECL 


u 18- 9 


99U6 


ECL 


TOTT.7 = 


1 

X 




U 1-UO 


U778 


ECL 


u 18-10 


082C 


ECL 

i-l Vx iJ 


U 21-lh 


ftTT9li 










u 18-11 


PHAC 


ECL 


TOTLZ = 


1 
X 










u 18-12 


22FU 


FPT. 


TI ?1 -1 R 


nnnn 


TTPT 


U 6- 3 


72C0 


ECL 


u 18-13 


PP3U 


ECL 








U 6- 6 


UH9U 


ECL 


u 18-iU 


762F 


FPT. 








U 6- 7 


0000 


ECL 


u 18-15 


H02H 


ECL 


TT 22- 2 


nnnn 


EPT 


TOTLZ = 


1 










TT 22- 


ftTI9L 


EPT 


U 6- 9 


8HF9 


ECL 








TT 22- li 


nnnn 


PPT 


U 6-12 


0000 


ECL 


u 19- 9 


1A92 




TOTLZ = 


1 

X 




u 6-13 


8HF9 


ECL 


u 19-11 


080P 




TT 99- 


nnnn 


PPT 








u 19-12 


low 
















u 19-iU 


PCHO 


FPT. 


TT 99- 7 


nnnn 


PPT 


U 8- 1 


UF8C 




u 19-15 


high 


J_i V' U 


TfVrT.7 = 


1 




U 8- 2 


UF8C 










TI 99-1 n 


UUUU 




U 8- 3 


73AU 
















U 8- U 


73AU 




U 20- 9 


8U2U 


FPT. 


II 99-11 
U £. £ XX 


nnnn 
uuuu 


PPT 


U 8- 5 


73AU 




U 20-10 


0000 


FCT. 


Trfl'T.7 = 

X V-^X Ij u 


1 

X 




U 8- 6 


UF8C 




TOTLZ = 


1 




IT 99-1 


nnnn 

UUUU 










U 20-11 


0000 


FPT. 


X V/X If u 


1 

X. 










TOTLZ = 


1 




II 99-1 U 


filT9li 


PPT 


U 16- 3 


18F3 


ECL 


U 20-12 


8U2U 


FPT. 


IT 99-1 ^ 

U X^ 


nnnn 
uuuu 


PPT 


U 16- 6 


0965 


ECL 


TOTLZ = 


1 








U 16- 7 


PltF6 


ECL 


u 20-13 


0000 


FPT. 














TOTLZ = 


1 




TT 9 •5— 9 


nnnn 


PPT 








U 20-lU 


8U2U 


FPT. 


TI 91- "3 


flTT9li 


PPT 


U 17- 2 


03P7 


ECL 


u 20-15 


0000 


FPT. 


TI 9'3- li 


nnnn 
uuuu 


PPT 


U 17- 3 


CU27 


ECL 








TOTLZ = 






u 17- 


IA92 


ECL 








U 23- 6 


nnnn 

uuuu 




U 17- 5 


high 


ECL 


U 21- 2 


0000 


ECL 


TOTLZ = 


1 




U 17- 6 


low 


ECL 


U 21- 3 


8U2U 


ECL 


U 23- 7 


high 


PPT 


U 17- 7 


low 


ECL 


U 21- h 


0000 


ECL 


TOTLZ = 


1 




U 17- 9 


low 


ECL 


TOTLZ = 


1 




u 23-10 


high 


ECL 


u 17-10 


high 


ECL 


U 21- 6 


0000 


ECL 


u 23-11 


73AU 


ECL 


u 17-11 


18F3 


ECL 


TOTLZ = 


1 




u 23-13 


0000 


ECL 


u 17-12 


22FU 


ECL 


U 21- 7 


0000 


ECL 


u 23-iit 


8U2U 


ECL 


u 17-13 


PP3U 


ECL 


TOTLZ = 


1 




TOTLZ = 


1 




u 17-iU 


F6IU 


ECL 








u 23-15 


0000 


ECL 


u 17-15 


78AA 


ECL 















SAC U-32 



Model 6U62IA - Performance Verification 



Board # 6k621-66303 

MODE: EDGES: THRESHOLDS: 

Normal Clock - Positive Data - High ** 

Start - Positive Data - Low ** 

Stop - Negative Clock - TTL 

ST-SP-QL - TTL 



= levels are TTL except where noted. 



TT 0)1- 0 


ATT 




IT 
U 


30-X5 


7ft A A 


II oil- li 


7*5 ATT 


vex 


TT 
U 


JO XD 


Vf^t TT 

r oxu 


TT oil- 


high 




IT 
U 


oQ_l 7 
JO X ( 


OpiiD 








TT 

U 


jo-xo 










TT 

u 


oft 1 d 

JO-X9 


"3 C 7D 
J5 ('^ 


IT "i 


PUOJr 




TT 

U 


JO-tX 


li77ft 
(O 


u 25-15 


DJU/: 




TT 

U 


oft 00 
Jo t J 


DtTI C 

rxlXp 


TI o(\ -1 0 






TT 

U 




PPTIP 
rtrnr 


m/VPT •? — 
l.\Ji.UU - 


U 




TT 

U 












TT 

U 


hu d 










TT 
U 


liO- 7 


lift 71 
HO f X 


TT 0 


4f (O 




TT 

U 


kn- ft 

4U 0 


TTTTTTO 


TT T^C- li 


DTJ1 c: 




TT 
U 






TT "^^^ ^ 
U JO- 0 


A59i' 




TT 
U 


hu-xu 


tinou 


TT Q^- T 
U JO- f 


lift 71 
hO I X 


TTPT 


TI 
U 


lU XX 


1 Ocr 


IT "5^- W 
U Jo 0 


y uun 




TT 
U 


4U-X J 




TT 0^ n 

U 3d- 9 


Drir L 




TT 
U 


}i n 1)1 


OJPT 


TT _i n 
U JD J.U 


TTnou 
nucn 




TT 

U 


«4U-X5 


7fi A A 
t OAA 


TT O^C 1 1 
U JD-XX 






TT 

U 


4U-XD 


1?^1 TT 

r OXU 


TT "^Cl 1 0 

U 3° li 


n)i 07 




TT 
U 


li n 17 


^c: A^ 
05 AD 


TT 0^ 1 )i 

U 3D-14 


OJPf 




TT 


li A 1 0 

1U-XO 


131 )|TT 


TT 0^ 1 C 

u 30-15 


7P A A 

( OAA 




TT 
U 


40-19 


U4oC 


TT •3^\ -1 (\ 
U jO-XD 


X05H 


vet 


TI 

u 


tu- tX 


onr y 


IT "3^^ -1 7 
U JD-Xf 


OpHO 


ypT 


TT 
U 


4U-t J 


TTHoli 


TI -1 ft 
U 3D XO 


ftPPQ 


rjCLi 








IT -1 n 
u 30 xy 


UHOL 


T*T*T 








u 00 ^x 




CiV/Jj 


IT 
U 




TTTPH 

f r 


u 36-23 


PCHO 


ECL 


u 


U2- U 


99'+6 








u 


U2- 6 


508P 








u 


U2- 7 


6302 


U 38- 2 


14778 


ECL 


u 


U2- 8 


FFU9 


u 38- I4 


PHI5 


ECL 


u 


U2- 9 


62FC 


U 38- 6 


5O8P 


ECL 


u 


U2-IO 


H02H 


U 38- 7 


6302 


ECL 


u 


I42-II 


762F 


U 38- 8 


9U0H 


ECL 


u 


1+2-13 


CU27 


U 38- 9 


62FC 


ECL 


u 


U2-IU 


03P7 


u 38-10 


H02H 


ECL 


u 


U2-I5 


78AA 


u 38-11 


762F 


ECL 


u 


1*2-16 


F6IU 


u 38-13 


CU27 


ECL 


u 


1*2-17 


65A6 


u 38 -lit 


03P7 


ECL 


u 


I42-I8 


99F7 








u 


1*2-19 


357P 








u 


1*2-21 


082C 








u 


1*2-23 


PHAC 



Test 1: Loop A - VH = 8U24 

CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 





TT 
U 




T'O ATT 






TT 
U 




nign 






TT 

U 


CO i 


nign 














CiCli 












TT 

U 


CO 1 

52- 1 


high 


£iCL 


ECL 


u 


52- 2 


TO ATT 

73AU 


T?^T 

ECL 




u 


52- 3 


low 


ECL 




TT 

u 


52- 4 


high 


ECL 


ECL 


TT 

u 


CO 1 0 

52-12 


TO ATT 

73AU 


ECL 




TT 
U 


CO 1 c 

52-15 


nign 
























C<CL 


TT 

U 


c)i 0 

54- 2 






EiCL 


TT 

U 


c )■ 0 

54- 3 


OPC9 




CiLL 


TT 

U 


c:)i )i 
54- 4 






fiCL 


TT 

U 


54- 5 


A59P 




ECL 


u 


54- D 


357P 




ECL 


u 


5I*- 7 


99F7 




ECL 


u 


54- 0 


6302 




ECL 


u 


51*- 9 


508P 




ECL 


TT 

u 


54-12 


on* IT"! 

2FF1 














ECL 










ECL 


u 


55- 2 


048c 






TT 

U 


55- 3 


Or09 






u 


55- H 


1+871 






u 


55- 5 


A59P 




ECL 


u 


55- 6 


357P 




ECL 


u 


55- 7 


99F7 




ECL 


u 


55- 8 


6302 




ECL 


u 


55- 9 


508P 




ECL 


u 


55-12 


9153 




ECL 










ECL 










ECL 


u 


58- 1 


IC85 


ECL 


ECL 


u 


58- 2 


1*2C2 


ECL 


ECL 


u 


58- U 


1*871 


ECL 


ECL 


u 


58- 5 


A59P 


ECL 


ECL 


u 


58- 6 


PHAC 


ECL 


ECL 


u 


58- 7 


082c 


ECL 


ECL 


u 


58- 9 


99^*6 


ECL 



ECL 
ECL 
ECL 



SAC l*-33 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 Test 1: Loop A - VH = 8U24 



MODE: EDGES: THRESHOLDS: CONNECTIONS: 



Normal 


Clock - 


Positive 


Data 


- High 


«« 


ST/SP/Start 


- TPI9 










Start - 


Positive 


Data 


- Low 


»» 


Qual/Stop - 


TPI9 












Stop - 


Negative 


Clock - TTL 




Clock - U99 pin 3 
















ST-SP-QL - TTL 


Groiind - GND (TP) 










** = levels are 


TTL except where noted. 














u 58-10 


7FCH 


ECL 


U 


61-11 


99F7 


ECL 


U 


67 
0 1 


- 1 


hifirh 




u 58-11 


8PC9 


ECL 


U 


61-12 


357P 


ECL 












u 58-12 


0U8C 


ECL 


U 


61-13 


25HU 


ECL 












u 58-13 


5A59 


ECL 


U 


61-lU 


U5C3 


ECL 


u 


6R 


- 1 






u 58-iU 


IC85 


ECL 


U 


61-15 


PFH9 


ECL 












u 58-15 


U2C2 


ECL 


































u 


69 


- 1 












u 


62- 5 


FFU9 














U 59- 1 


U5C3 


ECL 


u 


62- 7 


9U0H 














U 59- 2 


PFH9 


ECL 


u 


62-10 


5A59 




u 


78 


- It 


0965 


ECL 


U 59- U 


U87I 


ECL 


u 


62-11 


25HU 




u 


78 


- 5 


PPHP 


ECL 


U 59- 5 


A59P 


ECL 










u 


78 


- 6 


PUf6 


ECL 


u 59- 6 


PHAC 


ECL 










u 


78 


- 7 


U2C2 


ECL 


U 59- 7 


082C 


ECL 


u 


62- 1 


9U0H 


ECL 


u 


78 


- 9 


IC85 


ECL 


U 59- 9 


99 1+6 


ECL 


u 


62- 2 


FFU9 


ECL 


u 


78 


-10 


U2C2 


ECL 


U 59-10 


7FCH 


ECL 


u 


62-lk 


25HU 


ECL 


u 


78-11 


IC85 


ECL 


U 59-11 


8PC9 


ECL 


u 


62-15 


5A59 


ECL 


u 


78-12 


low 


ECL 


U 59-12 


0I+8C 


ECL 










u 


78-13 


08OP 


ECL 


u 59-13 


25HU 


ECL 




















u 59-1^+ 


U5C3 


ECL 


u 


63- 5 


508P 




















u 


63- 7 


6302 




u 


79- 


- 3 


8U2U 


ECL 








u 


63-10 


357P 




u 


79- 


- k 


pUf6 


ECL 


u 60- 1 


IC85 


ECL 


u 


63-11 


99F7 




u 


79 


■ 5 


PPHP 


ECL 


u 60- 1+ 


6302 


ECL 










u 


79- 


- 6 




F.CT. 


u 60- 5 


508P 


ECL 










u 


79- 


- 7 


PPHQ 


PCT. 


u 60- 6 


PHAC 


ECL 


u 


63- 1 


6302 


ECL 


u 


79- 


- 9 




ECL 


u 60- 7 


082c 


ECL 


u 


63- 2 


508P 


ECL 


u 


79- 


-10 


PFHQ 


ECL 


u 60- 9 


99^+6 


ECL 


u 


63-lU 


99F7 


ECL 


u 


79- 


-11 






u 60-10 


7FCH 


ECL 


u 


63-15 


357P 


ECL 


u 


79- 


-12 






u 60-11 


99F7 


ECL 










u 


79-13 




FPT. 


u 60-12 


357P 


ECL 




















u 60-13 


5A59 


ECL 


u 


6U- 5 


A59P 














u 60-iU 


IC85 


ECL 


u 


6k- 7 


I4871 




u 


80- 


- 2 




FPT. 


u 60-15 


U2C2 


ECL 


u 


6U-10 


0U8C 




u 


80- 


- 3 


pUf6 


ECL 








u 


6U-11 


8PC9 




u 


80- 


- k 


pUf6 


ECL 
















u 


80- 


- 5 


5HA1 


ECL 


u 61- 1 


U5C3 


ECL 










u 


80- 


- 6 


pUf6 


ECL 


U 61- 2 


PFH9 


ECL 


u 


6k- 1 


kSjl 


ECL 


u 


80- 


- 7 


UCC2 


ECL 


u 61- k 


6302 


ECL 


u 


6k- 2 


A59P 


ECL 


u 


80- 


-10 


pUf6 


ECL 


U 61- 5 


508P 


ECL 


u 


6U-llt 


8PC9 


ECL 


u 


80- 


-11 


ltCC2 


ECL 


U 61- 6 


PHAC 


ECL 


u 


6U-15 


OkQC 


ECL 


u 


So- 


-12 


UCC2 


ECL 


U 61- 7 


082c 


ECL 










u 


so- 


-13 


5HA1 


ECL 


U 61- 9 


99 U6 


ECL 




















u 61-10 


7FCH 


ECL 


u 


65-13 


0000 















TOTLZ = 1 



SAC k-3k 



Board # 6U62I-66503 

MODE: EDGES: THRESHOLDS: 

Normal Clock - Positive Data - High ** 

Start - Positive Data - Low ** 

Stop - Negative Clock - TTL 

ST-SP-QL - TTL 



= levels are TIL except where noted. 



u 80-iU 


P21+A 


ECL 


U 99- 


■11 


77*55 


u 80-15 


14CC2 


ECL 


U 99- 


•12 


8U2U 








TOTLZ = 


70^1+7 








II QQ- 




U87I 


U Bl- k 


pUf6 


ECL 








U 81- 5 


PPHP 


ECL 








U 81- 6 




ECL 


Til 00- 


. 1 


lUPP 


U 81- 7 


U2C2 


ECL 


UIOO- 


. 2 


CUf8 


IT 81 - Q 


ICRs 


ECL 

u u 


UIOO- 


. -i 
•J 


A1Q2 

AX J7 C- 


u 81-10 


k2C2 


ECL 


UIOO- 


■ k 


8877 


u 81-11 


IC85 


ECL 


UIOO- 




7755 

1 1 yy 


u 81-12 


low 


ECL 


UlOO- 


■ 7 
1 


8877 


u 81-13 


O8OP 


ECL 


tn nn- 




hi &rh 








TTi nfi- 


■1 0 










UIOO- 


■11 


hicrh 


u 82- k 


UCC2 


ECL 


uxuu 


x^ 


**Xgll 


u 82- 5 


PPHP 


ECL 








U 82- 6 


5HA1 


ECL 








IT ft?- 7 


PFHQ 




UlOl- 


. 1 


1 TIPP 


U 82- 9 




ECL 


UlOl- 


2 


CUf8 


u 82-10 


PFH9 


ECL 


UlOl- 

\J u. \J ^ 




AI92 


u 82-11 




ECL 


ux wx 


u 


07'53 

^ 1 


u 82-12 


low 


ECL 


UlOl- 


J 


U871 


u 82-13 


O8OP 


ECL 


Ul 01- 


6 


1U07 








UlOl- 


7 


AHPO 








UlOl- 


9 


6110 




AHPO 




UlOl- 


10 


872A 


u 85-10 


872A 




UlOl- 


11 


FFU9 


u 85-11 


6110 




UlOl- 


12 


9U0H 








UlOl- 


13 


25HU 








UlOl- 


lU 


5A59 


u 85- >+ 


22FU 


ECL 


UlOl- 


15 


73AU 


u 85-12 


O8OP 


ECL 








u 85-13 


PP3i'* 


ECL 














U102- 


1 


lUPP 








U102- 


2 


CUF8 


u 89- 1 


high 




U102- 


3 


AI92 








U102- 


It 


0753 








U102- 


5 


U87I 


u 96-11 


7755 




U102- 


6 


9C23 


u 96-12 


U87I 




U102- 


7 


7H09 


u 96-13 


high 




U102- 


9 


high 








U102- 


10 


6C7U 



Model 6U62IA - Performance Verification 



Test 1: Loop A - VH = 8U24 

CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



U102- 


11 


8U2U 


U102- 


12 


hiffh 


U102- 


1^ 

X J 


hiffh 

*AXgA* 


U102- 


lU 




U102- 


15 

^y 


2FF1 


UIO3- 


2 


8U2U 


TOTLZ 




OFLO 


UIO3- 


3 


8U2I4 


UIO3- 




6C7U 


UIO3- 


6 


high 


UIO3- 


7 


low 


UIO6- 


2 


8877 


UIO6- 


3 


8U2U 


TOTLZ 




DFLO 


UIO6- 


U 


8U2U 


TOTLZ 




U61;l 


UIO6- 


5 


8U2U 


TOTLZ 




OLFO 


UIO6- 


6 


8877 


UIO6- 


7 


0753 


ini5- 


8 


U871 


UII5- 


9 


7755 



UII5-12 1»407 
UII5-I3 9C23 



UII7- 2 0000 
TOTLZ = 1 
UII7- 3 7H09 
UII7-I3 $$$$ 



UII8- 2 8U2U 
UII8- 3 8U2it 
TOTLZ = OFLO 
UII8-II 0000 
TOTLZ = 703U7 



SAC it-35 



Model 6U62IA - Performance Verification 



Board # 6I+621-66503 






MODE: 


EDGES: 




THRESHOLDS: 




Normal 


Clock - 


Positive 


Data - High 






Start - 


Positive 


Data - Low ' 






Stop - 


Negative 


Clock - TTL 










ST-SP-QL - ■ 


PTL 


** = levels are 


TTL except where noted. 


UII9- 2 


lUPP 




UI2O-I8 


508P 


UII9- 3 


lUPP 




UI2O-I9 


low 


U119- u 


cUfS 








UII9- 5 


CkF8 








UII9- 6 


AI92 




U121- 1 


7755 


UII9- 7 


AI92 




U121- 2 


508P 


UII9- 8 


9C23 




U121- 3 


6302 


UII9- 9 


9C23 




U121- U 


99F7 


UII9-II 


0000 




U121- 5 


357P 


UII9-I2 


8877 




U121- 6 


A59P 


UII9-13 


8877 




U121- 7 


U871 


UII9-IU 


8U2U 




U121- 8 


8PC9 


TOTLZ = 


OFLO 




U121- 9 


0U8C 


UII9-I5 


8U2I4 




U121-11 


0U8C 


UII9-I6 


U87I 




U121-12 


8PC9 


UII9-I7 


U87I 




UI2I-I3 


U871 


UII9-I8 


high 




U121-llt 


A59P 


UII9-I9 


high 




UI2I-I5 


357P 








UI2I-I6 


99F7 








UI2I-I7 


6302 


U120- 2 


high 




UI2I-I8 


508P 


U120- 3 


0U8C 




UI2I-I9 


0000 


U120- U 


8PC9 








U120- 5 


low 








U120- 6 


low 




U122- 1 


8877 


U120- 7 


J4871 




U122- 2 


high 


U120- 8 


A59P 




U122- 3 


0U8C 


U120-11 


high 




U122- I4 


high 


UI2O-I3 


357P 




U122- 5 


8PC9 


UI20-IU 


99F7 




U122- 6 


low 


UI2O-I6 


high 




U122- 7 


U87I 


UI2O-I7 


6302 




U122- 8 


$$$$ 








U122- 9 


A59P 



Test 1: Loop A - VH = 8U24 

CONNECTIONS : 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



TTI 99 


-1 1 


high 


III ??■ 


X c 


J? 1 1 


III ??■ 


xj 




in 00- 


XH 


QQF7 


TT1 00 ■ 
\jXc.c. 


-1 


low 








U122 


-17 


high 




xu 




U122- 


-19 


8877 


UI23 


- 1 


high 




- d. 


low 


U123 


- 3 


high 


U123- 


- u 


pHUX 


U123- 


- 5 




U123- 


- 6 


low 


UI23 


- 7 


high 


U123- 


- 9 


high 


UI23 


-11 


high 


U123- 


-12 


C3HA 


UI23 


-13 


9361 


U123- 


-lU 


high 


U125- 


- 1+ 


0000 


U127- 


- u 


0000 


TOTLZ = 


703U7 


U127- 


- 5 


U8Y1 


U127- 


- 6 


U87I 



SAC U-36 



Model 6U62IA - Performance Verification 



Board # 6I+62I-66503 



Test 2: Loop B - VH = 0418 



MODE: EDGES: 

Normal Clock 

Start 

Stop 



Positive 
Positive 
Negat ive 



THRESHOLDS: 
Data - High ** 
Data - Low ** 
Clock - TTL 
ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



= levels are TTL except where noted. 



u 1-17 


99CA 


U102-10 


PPl+6 


U121- 1 


ahUi 


u 1-18 


A22H 


U102-12 


F513 


m21- 2 


3831 


u 1-19 


F513 






U121- k 


ACHH 


U 1-20 


3831 






UI2I-I6 


ACHH 






UIO3- 2 


2HUF 


UI2I-I8 


3831 






UI03- 3 


2HUF 


UI2I-I9 


0000 


U102- 1 


82OF 


U103- u 


PPU6 






U102- 2 


PPU6 


UI03- 7 


A22H 






U102- 3 


F513 






U122- 1 


ahUi 


U102- U 


A959 






U122- 6 


99CA 


U102- 5 


A959 


UII8- 2 


2HUF 


UI22-IU 


ACHH 


U102- 6 


0U18 


UII8- 3 


2HltF 






TOTLZ = 


6027 


UII8-II 


0000 










TOTLZ = 


982 







SAC lt-37 



Model 6k621A - Performance Verification 



Board # 6U62I-66503 Test 3: Loop C - VH = C811 



MODE: 


EDGES: 




THRESHOLDS: 




CONNECTIONS : 






Normal 


Clock - 


Positive 


Data - High 


«« 


ST/SP/Start 


- TPI9 






Start - 


Positive 


Data - Low 


»« 


Qual/Stop - 


TPI9 






Stop - 


Negative 


Clock - TTL 




Clock - U99 pin 3 










ST-SP-QL - ' 


rrL 


Ground - GND (TP) 




** = levels are 


TTL except where noted. 








u 25-13 


993U 




u 52-12 


C851 


ECL 


U121- 8 


0HH9 


u 25-iU 


6H99 




u 52-15 


C80P 


ECL 


U121- 9 


lool 


u 25-15 


92PC 










U121-11 


lobl 


u 25-16 


0F97 










U121-12 


6HH9 


u 25-26 


0F97 




U102- 1 


09H2 




UI2I-I7 


92PC 


u 25-28 


A38U 




U102- 2 


0A7F 




UI2I-I8 


993U 








U102- 3 


6HH9 




UI2I-I9 


A A 

0000 








U102- I4 


CC76 




TOTLZ = 


213 


U 25- 9 


high 


ECL 


U102- 5 


CC76 














U102- 6 


C65I 














UIO2-I3 


6h99 




U122- 1 


0367 


U 52- 5 


C85I 










U122- 3 


1861 


u 52-10 


C8OP 










U122- 5 


6HH9 








U121- 1 


0367 




UI22-I5 


A38it 








U121- 2 


993U 




UI22-I7 


0F97 


U 52- 2 


C85I 


ECL 


U121- 3 


92PC 








u 52- It 


C8OP 


ECL 













SAC U-38 



Model 6k621A - Performance Verification 



Board # 6U62I-66503 



Test 4: Loop D - VH = AU30 



MODE: EDGES: THRESHOLDS: 

Normal Clock - Positive Data - High ** 

Start - Positive Data - Low ** 

Stop - Negative Clock - TTL 

ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



levels are TTL except where noted. 



u 1-18 


CAUH 




U 


D-11 


low 


ECL 


U 


20- 3 


PCCF 


ECL 


u 1-19 


ou6h 




u 


6-14 


high 


ECL 


U 


20- 6 


UUoF 


ECL 


U 1-20 


6297 












U 


20- 7 


0000 


ECL 


u 1-3U 


2277 




u 


15- 2 


49 2F 


ECL 


TOTLZ = 


67701 




U 1-35 


AU30 




u 


16- 3 


f6uc 


ECL 










TOTLZ = 


283 




u 


lb- 5 


low 


ECL 


U 


36- 2 


3U7o 


ECL 








u 


16- 6 


a6oa 


ECL 


U 


36- U 


AU88 


ECL 


U 1- 1 


U613 


ECL 


u 


16- 7 


uhU1+ 


ECL 


U 


36- 6 


5U93 


ECL 


U 1- 2 


1+9 2F 


ECL 










U 


36- 7 


70CH 


ECL 


U 1- 3 


0000 


ECL 


u 


17- 2 


9UFH 


ECL 


U 


36- 8 


pf6c 


ECL 


TOTLZ = 


67701 




u 


17- 3 


7^1A 


ECL 


U 


36- 9 


H772 


ECL 


U 1- u 


TUCk 


ECL 


u 


17- k 


8505 


ECL 


U 


36-10 


FFO8 


ECL 


u 1- 5 


80C7 


ECL 


u 


17- 5 


I5FH 


ECL 


U 


36-11 


7933 


ECL 


U 1- 6 


fhUa 


ECL 


u 


17- 6 


CAUH 


ECL 


U 


36-13 


7'+lA 


ECL 


U 1- 7 


AU88 


ECL 


u 


17- 7 


low 


ECL 


U 


36-lu 


9I+FH 


ECL 


U 1- 8 


lUCU 


ECL 


u 


17- 9 


low 


ECL 


U 


36-15 


Ufuf 


ECL 


U 1- 9 


H026 


ECL 


u 


17-10 


high 


ECL 


U 


36-16 


0837 


ECL 


U 1-10 


1164 


ECL 


u 


17-11 


f6uc 


ECL 


U 


36-17 


3500 


ECL 


U 1-11 


126c 


ECL 


u 


17-12 


7CC8 


ECL 


U 


36-18 


6U93 


ECL 


U 1-12 


H026 


ECL 


u 


17-13 


5U5I 


ECL 


U 


36-19 


8U01 


ECL 


u 1-16 


0000 


ECL 


u 


17-lU 


0837 


ECL 


U 


36-21 


U92F 


ECL 


TOTLZ = 


67701 




u 


17-15 


1+fUf 


ECL 


U 


36-23 


high 


ECL 


U 1-21 


7F2F 


ECL 


















u 1-30 


3U78 


ECL 


u 


18- 2 


H772 


ECL 


u 


38- 2 


2020 


ECL 


U 1-33 


0000 


ECL 


u 


18- 3 


3500 


ECL 


u 


38- k 


FP73 


ECL 


TOTLZ = 


67701 




u 


18- U 


AU30 


ECL 


u 


38- 6 


6297 


ECL 


u 1-36 


FP73 


ECL 


TOTLZ = 


0 




u 


38- 7 


H^tlO 


ECL 


u 1-37 


FA12 


ECL 


u 


18- 5 


1 IT TT'TT 

I5FH 


ECL 


u 


38- 8 


PFoC 


ECL 


u 1-38 


2020 


ECL 


u 


18- 6 


8505 


ECL 


u 


38- 9 


H772 


ECL 


U 1-39 


69PI 


ECL 


u 


18- 7 


pc6l 


ECL 


u 


38-10 


FFO8 


ECL 


U 1-UO 


3U78 


ECL 


u 


18- 9 


7F78 


ECL 


u 


38-11 


7933 


ECL 








u 


18-10 


A2UF 


ECL 


u 


38-13 


7UIA 


ECL 


U 5- 2 


0000 


ECL 


u 


18-11 


H31H 


ECL 


u 


38-11* 




ECL 


TOTLZ = 


66382 




u 


18-12 


7CC8 


ECL 


u 


38-15 


UfUF 


ECL 


U 5- 3 


0000 


ECL 


u 


18-13 


5U5I 


ECL 


u 


38-16 


0837 


ECL 


TOTLZ = 


66382 




u 


18-lU 


7933 


ECL 


u 


38-17 


3500 


ECL 


U 5- ^ 


0000 


ECL 


u 


18-15 


FF08 


ECL 


u 


38-18 


FPU9 


ECL 


U 5- 5 


H026 


ECL 










u 


38-19 


0C9C 


ECL 


U 5- 6 


0000 


ECL 


u 


19- 9 


8505 


ECL 


u 


38-21 


PA12 


ECL 


U 5- 7 


H026 


ECL 


u 


19-12 


CAUH 


ECL 


u 


38-23 


3U78 


ECL 


U 5-10 


0000 


ECL 


u 


19-15 


69PI 


ECL 










U 5-11 


7UCI+ 


ECL 










u 


UO- 2 


UI5C 


ECL 


U 5-1^ 


0000 


ECL 










u 


Uo- U 


3357 


ECL 


TOTLZ = 


531 












u 


i*0- 6 


5U93 


ECL 



SAC U-39 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 



Test 4: Loop D - VH = AU30 



MODE: EDGES: 

Normal Clock 

Start 

Stop 



Positive 
Positive 
Negative 



THRESHOLDS: 
Data - High ** 
Data - Low ** 
Clock - TTL 
ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



levels are TTL except where noted. 



IT hn- 7 
U f 




PPT 


TT 
u 


po X 


fifiiin 


RPT. 


TJ 


61- 1 


IQIJP 


ECL 


TT liD- ft 
U HU 0 


t\'?ftft 




TT 

u 




1 UjO 


PPT. 


TT 
u 


61- 2 


8CCC 


ECL 


IT liD- 0 

u mj y 


TI77!3 
"lit 


PPT 


TT 
U 


'=;ft- ^ 


XOW 


PPT. 


TT 

u 


61- •\ 


1 CWJ 


ECL 


IT iin-i n 


r r uo 


PPT 


TT 




7nPH 


PPT. 


IT 


61- u 


hUio 


ECL 


TT hn -1 1 




PPT 


IT 
u 


po p 


puyj 




TI 


61- ^ 
ox p 


6207 


ECL 




( HXA 


PPT 


IT 
U 


po 0 


njxn 




TT 


61- 6 


n^xxi 


F.PT. 


TT )in 1 )i 


n)iTrTj 


PPT 


IT 

U 


cift- 7 

po t 


ri^ ur 




TT 

u 


61-7 
ox 1 




PPT. 


TT c: 

u mj j-p 




PPT 


IT 
U 


c;ft- Q 
po y 


(r ( 0 




TI 


f^l - Q 
ox y 


(r 1 0 


FPL 


IT lin-i<\ 


UO J f 


PPT 


IT 


^ft-1 n 

pt) XU 


t vox 




TT 


61 -1 0 

UX XV/ 


PC6l 
* vux 


ECL 


TT )in-i 7 




PPT 


TT 

U 


po XX 


Duy J 


FPT. 


TT 


61 -1 1 

UX XX 


FPllQ 
f rHj7 


KPT. 


IT iin-i ft 
u hu xo 




PPT 


TT 

U 


po ± ^. 


ftL.ni 




TT 


61 -1 ? 

V/X X t 


OPOP 


EPL 


IT lin-1Q 

u xy 


OHUX 


PPT 


IT 

u 


po X J 


pov^y 




TT 
u 


^1 -1 

UX X J 


HOC. C. 


PPL 


IT lin-91 

U HU ^x 




PPT 


II 


•=18-1 U 


H7TI0 




IT 


61-lU 


?A78 


ECL 


IT hn-?"? 


Jim I 


PPT. 


II 

(J 


po xp 


6261 




u 


61-15 




ECL 


TT JiO 0 


rv^DX 


PPT 


TT 
U 


py- X 


r upp 


PPT 


TI 

u 


o<; p 


^'^ftft 

PJOO 




TT )lO )l 


71? 7ft 


PPT 


IT 
U 


py ^: 


HDOp 


PPT 


TI 

u 


o<- 1 






TT )lO_ ^ 
U Ht D 




PPT 


TT 

U 


py J 


low 


PPT 


TI 


oc xu 


pooy 




TT liO- 7 


will n 


PPT 


TT 

U 


py 4 


1 uvn 


PPT 


TI 


1 

U£ XX 


HUcfc 




IT ft 
U 0 


i^'iftft 
PjOO 


PPT 


IT 

u 


py P 


puyj 


PPT. 

£ivlj 










TT )iO r» 


117*70 

H772 




TT 

U 


py 0 


njxn 


PPT 


TT 
U 


Dt X 




PPT 


TT )iO 1 n 


r r UO 




TT 
U 


py ( 


A 01 IP 


PPT 


IT 
U 




c;')ftft 
pjoo 


PPT 


TT )lO_1 1 
U XX 


70 "o*^ 


PPT 


TI 
U 


py y 


7P7ft 

(e (O 


PPT 


IT 
U 


XH 




PPT 
£iV^Ij 


U Xj 


1 HXK 


PPT 


IT 

u 


py xu 


PP^il 


PPT. 


IT 
u 


xp 


^ftPQ 


PPT. 


IT h 


yH£ n 


PPT 


TT 

U 


py XX 


^^ITQ■^ 

Duyj 


PPT 










TT )iO -1 C 
U 4t Xp 




PPT 


TT 
U 


py-X/i 


fthm 

OHUX 


PPT 


TT 
U 


DJ- P 


Dty f 




TT )iO_1 ^ 

U XD 


nft'^ 7 


PPT 


TT 

U 


py J-j 


HUcc 


PPT 


II 
U 


^^■3- 7 
Dj 1 


Tilii n 

XIHXU 




TT li9-17 




PPT. 


n 


^Q-1 h 
py xH 


8?P0 


EPL 


IT 


U J J- \J 


OCOC 




u U2-18 


FPU9 


ECL 


u 


59-15 


fp66 


ECL 


u 


63-11 


FPlt9 




u U2-19 


0C9C 


ECL 


















u U2-21 


A2UF 


ECL 


u 


60- 1 


A2H9 


ECL 


u 


63- 1 


HUIO 


ECL 


u U2-23 


H31H 


ECL 


u 


60- 2 


hp6a 


ECL 


u 


63- 2 


6297 


ECL 








u 


60- 3 


low 


ECL 


u 


63-lU 


FPU9 


ECL 


U U3- 3 


PCCF 


ECL 


u 


60- 1+ 


hUio 


ECL 


u 


63-15 


0C9C 


ECL 


U J43- 5 


0000 


ECL 


u 


60- 5 


6297 


ECL 










TOTLZ = 


67701 




u 


60- 6 


H31H 


ECL 


u 


6U- 5 


5U93 




U U3- 6 


0000 


ECL 


u 


60- 7 


A2UF 


ECL 


u 


61*- 7 


70CH 




TOTLZ = 


67701 




u 


60- 9 


7F78 


ECL 


u 


6I1-10 


8U01 




U U3- 7 


1+U8F 


ECL 


u 


60-10 


PC6l 


ECL 


u 


6i4-ll 


6U93 










u 


60-11 


FPI49 


ECL 










U 52- 7 


I5FH 




u 


60-12 


0C9C 


ECL 


u 


6U- 1 


70CH 


ECL 








u 


60-13 


58C9 


ECL 


u 


61+- 2 


5U93 


ECL 


u 52- 1 


I5FH 


ECL 


u 


60-1I4 


2708 


ECL 


u 


6U-1U 


6U93 


ECL 


U 52- 3 


CAUH 


ECL 


u 


60-15 


F7P6 


ECL 


u 


614-15 


8U01 


ECL 



SAC lt-l40 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 

MODE: EDGES: THRESHOLDS: 

Normal Clock - Positive Data - High ** 

Start - Positive Data - Low ** 

Stop - Negative Clock - TTL 

ST-SP-QL - TTL 



** = levels are TTL except where noted. 



U 65- 5 


PCCF 




TT Trt 1 -1 

u 79-11 


o2P0 








TT '7C\ "1 

u 79-13 


lb2o 


U 05- D 




ECL 






U 65- 7 


PCCF 


ECL 


TT Q 0 

U oO- 2 


0F4o 








U 80- 3 


UHUU 


U 66- 4 


PCCF 




U 80- U 


UHl+U 


TT /T/T r- 

U 66- 5 


PCCF 




u 80- 5 


3357 


U 66-12 


AU30 




u 80- 6 


8390 








U 80- 7 


UF98 


U 68- 1 


CA14 




u 80- 9 


AU30 


U 68- 2 


81+01 




TOTLZ = 


0 


U 68- 3 


33C6 




T T 0 ^ A 

U oO-lO 


8390 


TT /^Q )• 

U 60- 4 


ohp6 




u 80-11 


0H42 


TT /TO IT 

U 60- 5 


6U93 




u 00-12 


4F90 


TT Z^Q C 

U 68- 6 


70CH 




u 80-13 


3357 


U 68- 7 


FC20 




U 80-llt 


uU6f 


TT ^0 0 

U 68- 8 


65U9 




u 80-15 


OHl+2 


U 68- 9 


5U93 








U 68-11 


PCCF 




U 81- 4 


UH44 


U 68-12 


0C9C 




U 81- 5 


UI5C 


u 68-13 


I9PU 




U 81- 6 


UU6F 


U 68-lU 


83H3 




U 81- 7 


hp6a 


u 68-15 


FPU9 




u 81- 9 


A2H9 


TT ZTO 1 ^ 

U 68-16 


hUio 




u 81-10 


F7P6 


u 68-17 


0C71 




u 81-11 


2708 


U 68-18 


O7HO 




u 81-13 


1628 


u 68-19 


6297 














U 82- 4 


4F98 


TT li 

U fo- 4 




ECL 


TT Q 0 C 

U o2- 5 


TT1 17 

UlpC 


U 78- 5 


U15C 


ECL 


u 82- 6 


3357 


U 78- 6 


OF»48 


ECL 


U 82- 7 


8CCC 


U 78- 7 


7038 


ECL 


U 82- 9 


19UP 


U 78- 9 


88U0 


ECL 


u 82-10 


113c 


u 78-10 


6261 


ECL 


u 82-11 


2A78 


u 78-11 


H7U0 


ECL 


u 82-13 


1628 


u 78-13 


1628 


ECL 












U 83- U 


7UIA 


U 79- k 


8390 


ECL 


U 83- 5 


9J4FH 


U 79- 5 


UI5C 


ECL 


U 83-12 


l+Fl+F 


U 79- 6 


OHI42 


ECL 


u 83-13 


0837 


U 79- 7 


1+685 


ECL 






U 79- 9 


FC55 


ECL 


U 83- 3 


7UIA 


U 79-10 


FP66 


ECL 


U 83- 7 


9UFH 








u 83-11 


i*fUf 








u 83-15 


0837 



Test 4: Loop D - VH = AU30 

CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



17 /-IT 

ECL 


TT 

U 


04- 4 


0 C A 

3500 




ECL 


TT 

U 


all c 
04- 5 


TJ'7"70 

HT72 






TT 

U 


04- J.t 


r r UO 




ECL 


TT 

u 


04-13 


7933 




ECL 










ECL 


TT 

U 


o4- 3 


0 C rt 

3500 


ECL 


ECL 


TT 

U 


o4- 7 


H772 


ECL 


ECL 


u 


o4-ll 


FFO8 


ECL 


£iUL 


TT 
U 


04-lp 


7933 


ECL 


ECL 












TT 
U 


He c 

05- 5 


n400 




ECL 


TT 

U 


05- 7 


4'+Or 




ECL 


TT 

U 


op-lU 






ECL 


TT 

U 


05-11 


UCbl 




ECL 










TT" /-I T 

ECL 


TT 

U 


Qc 1 
05- 1 


44cSF 


ECL 


ECL 


U 


05- 4 


7CC8 


ECL 




TT 

U 


05-12 


lb2o 


ECL 


ECL 


u 


85-13 


5U5I 


ECL 


ECL 










ECL 


u 


0 1 

09- 1 


1 Q r" 

I052 




ECL 


u 


89- 2 


8UOI 




ECL 


u 


89- 3 


7933 






TT 

u 


fin )i 
09- 4 


rr Uo 




ECL 


TT 

u 


09- 5 


6U93 




ECL 


u 


89- 6 


7OCH 






u 


89- 7 


n( {d 




ECL 


u 


89- 8 


3500 




ECL 


u 


89- 9 


5U93 




ECL 


u 


89-11 


PCCF 




ECL 


u 


89-12 


0C9C 




ECL 


u 


89-13 


0837 




ECL 


u 


89-lU 


»+fUf 




ECL 


u 


89-15 


FPU9 




ECL 


u 


89-16 


Hl+10 






u 


89-17 


9i4FH 






u 


89-18 


7UIA 






u 


89-19 


6297 






u 


98- 1 


29HU 






u 


98- 5 


AU30 




ECL 


TOTLZ = 


583 




ECL 


U 98- 7 


C6U5 





ECL 
ECL 

SAC U-l+l 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 Test 4: Loop D - VH = AU30 

MODE: EDGES: THRESHOLDS: CONNECTIONS: 

Normal Clock - Positive Data - High ** ST/SF/Start - TPI9 

Start - Positive Data - Low ** Qual/Stop - TPI9 

Stop - Negative Clock - TTL Clock - U99 pin 3 

ST-SP-QL - TTL Ground - GND (TP) 



= levels are TTL except where noted. 



u 98-10 


2277 


U102- 3 


F89F 


U118-11 


0000 


u 98-12 




U102- U 


6F58 


TOTLZ = 


98693 


TI Q8-1 


66 UF 


U102- 5 


28hU 






u 98-iU 


66 Hf 


U102- 6 


HF93 


U121- 1 


87PU 






U102- 7 


29HU 


U121- 2 


6291 


iTinn- 1 




U102- 9 




U121- 3 


hUio 


in 00- ? 


QIU7 

^XH 1 






U121- k 


FPl»Q 




f8qf 


UlOU- 1 


29Hl* 


U121- 5 


0C9C 






III oU- ? 


Aino 


U121- 6 






87PU 


TOTLZ = 


^ J-*- 


U121- 7 


70CH 


in nn- 7 




TT1 nU-1 1 

UXV/*T XX 


1 QPII 


in 21- 8 

UXCX 




UlOO- 9 


1852 


U1014-12 


8'^H3 


U121- 9 


8UOI 


TT1 nn-1 n 


IlXgll 


UlOll-l"^ 

IJXV/*t X J 


0C71 


U121-11 


8UOI 


TT1 nn-1 1 


high 


TTI nli-1 h 

UXWt X*t 




in 21 -1 ? 

wx^x x^ 


61 IQ? 


in 00-12 


CAlU 


UlOU-15 


P17F 


U121-13 


7OCH 










U121-1U 


SUQ^ 
j^yj 


UlOl- 1 


PAC5 


UI05- 1 


29HU 


U121-15 


0C9C 


UlOl- 2 


91^7 


UIO5- 2 


AU30 


U121-16 


FPI49 


UlOl- 3 


F89F 


UIO5-IO 


P17F 


U121-17 


hUio 


UlOl- U 


6F58 


UIO5-II 


33C6 


U121-18 


6297 


UlOl- 5 


28hU 


UIO5-I2 


0HP6 


U121-19 


0000 


UlOl- 6 


73A3 


UIO5-I3 


FC20 






UlOl- 7 


Hl+88 


UIO5-IU 


65U9 


U122- 1 


25A2 


UlOl- 9 


uc6l 


UIO5-I5 


F0H5 


U122- U 


C6U5 


UlOl-10 


C918 






UI22-I6 


Hl+lO 


UlOl -11 


5388 


UIO6- 2 


F368 






UlOl-12 


pf6c 


UIO6- 3 


PCCF 


UI25- 1 


kkSF 


UlOl -13 


^4022 


UIO6- k 


PCCF 


UI25- 2 


28Hl* 


uioi-iU 


5CC9 






UI25- 3 


PCCF 


ulol-15 


U22A 


UII8- 2 


66UF 










UII8- 3 


66UF 


U127- 6 


28HI+ 


U102- 1 


PAC5 










U102- 2 


91^7 











SAC U-lt2 



Model 6U621A - Performance Verification 



Board # 6I462I-66503 

MODE : EDGES : THRESHOLDS : 

Normal Clock - Positive Data - High ** 

Start - Positive Data - Low ** 

Stop - Negative Clock - TTL 

ST-SP-QL - TTL 



Test 5: Loop E - VH = U16U 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



levels are TTL except where noted. 



II 1-17 


C'^'^0 




U 20- 2 


6852 


ECL 


U 


71- 6 




II 1 -1 8 


1 /-\T.T 
XV-IW 




U 20- 5 




ECL 


U 


71- 7 


lAXgll 


II 1 -1 Q 


JXX J 










U 


71- 9 


65^6 


II l-?0 


60FU 




u U5-12 


0000 


ECL 


U 


71-10 


762c 


u i-'^U 


3U01 




TOTLZ = 


6550 




u 


71-11 


9U15 




XiXgll 




U U'S-l^ 

V-l X J 


6852 


ECL 


u 


71-12 


C23U 








u x^ 


0000 


ECL 


u 


71-13 


6960 


II 1 - ? 


w 


ECL 

u v./ JJ 


TOTLZ = 


65^1 

vJ^JX 




u 


71-lu 




II 1 - ^ 

U X J 


0000 


ECT. 








u 


71-15 


POUH 


T0TT,7 = 

X U Lt — 






U 66- I4 






u 


71-16 


9PAU 


IT 1 - U 
U X H 




Frr. 


U 66-1"^ 

U V W X J 


Ul6u 




u 


71-18 


0U7P 


11 1-7 

U X ( 




FPT. 








u 


71-20 


ui6u 


IT 1 - ft 

U X VP 


■^1 7ft 

jx 1 0 




II 66- ? 


fqq6 


ECI. 


TOTLZ = 


6sio 


u 1-16 

\J -1- XW 


0000 


ECL 


u 66- 3 




ECL 


U 


71-21 


hierh 








u 66-iU 


0000 


ECL 








TI 1 -?1 

U X CiX 


81 F1 

V/XIT X 


ECL 


u 66-15 


Ul6U 


ECL 


U 


72- 1 


xixgxi 


IT 1 -"^n 


xv w 


FPL 


TOTLZ = 

X VyX iJ lU 


65S0 




U 


72- 2 


llXgXi 


IT 1 -"S"? 
u X J J 


w u u w 










U 


72- 3 










IT 6Q- 1 


fl'^OA 

VJ J V^rt 




U 


72- U 


III 6tt 


II 1 -"^fi 

U X 


ft7AF 


ill ^ u 


u 6q- 2 


ooUq 




U 


72- 5 


iixgxi 




9U6U 


ECL 


u 6q- ? 


9PAU 




U 


72- 6 


ixxgxi 


TI 1 -"^ft 

U X 


QI16U 




U 6Q- U 






U 


72- 7 


xxxgxx 


U 1-39 


high 


ECL 


U 69- 5 


0140P 




U 


72- 9 


7020 


u 1-Uo 


9u6U 


ECL 


u 69- 6 


'^7Q7 




U 


72-10 


762c 








u 6q- 7 


C2'^U 

Vi* J "T 




u 


72-11 


71Q0 

1 x^w 


II "i-lO 

VJ ^ xu 


0000 


ECL 


U 69- 8 


762c 




u 


72-12 


C23U 


u 5-11 




ECL 


U 69- 9 


P7U2 




u 


72-13 


Ufau 


U 5-12 


ui6u 


ECL 


u 69-11 


38U9 




u 


72-lU 


5380 


TOTLZ = 


6550 




u 69-12 


OOPH 




u 


72-15 


cpc6 


u 5-13 


ui6u 


ECL 


u 69-13 


905U 




u 


72-16 


9PAU 


U ^-Ik 


0000 


ECL 


u 69-iU 


FCCP 




u 


72-18 


U35F 


TOTLZ = 


19 




u 69-15 


71 7H 




u 


72-20 


Ul6U 


u 5-15 


Ul6U 


ECL 


u 69-16 


3U21 




TOTLZ = 


19 








u 69-17 


8U36 




U 


72-21 


high 


U 16- 9 


Ul6U 


ECL 


u 69-18 


Al+83 










u 16-12 


0000 


ECL 


u 69-19 


6OFU 




U 


77- I4 


7020 


TOTLZ = 


6550 










U 


77- 5 


7190 


u 16-13 


0000 


ECL 


u 71- 1 


high 




U 


77-12 


Ufau 


TOTLZ = 


6550 




U 71- 2 
U 71- 3 


high 
high 




U 


77-13 


cpc6 


U 19- 3 


38U9 


ECL 


u 71- U 


Ul6U 




U 


77- 3 


7020 


U 19- 6 


F996 


ECL 


TOTLZ = 


6510 




U 77- 7 


7190 


U 19- 7 


F996 


ECL 


u 71- 5 


high 




U 


77-11 


Ufau 



u 77-15 CPC6 



ECL 
ECL 
ECL 
ECL 



SAC U-U3 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 



Test 5: Loop E - VH = U16U 



MODE: EDGES: THRESHOLDS: 

Normal Clock - Positive Data - High ** 

Start - Positive Data - Low ** 

Stop - Negative Clock - TTL 

ST-SP-QL - TTL 



CONNECTIONS : 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



levels are TTL except where noted. 



U Op- I 




IT Q1 -11 

u yx-xx 


QQTlli 

yyu*t 


TT Q'? -1 T 










TI Q1 -1 9 




II Q'^-l h 
u y J XH 


VCCP 
r i^^^r 




u 05- X 




TI Q1 -1 

u yx-xj 


iinro 


IT Q7-1 


fli 70 

ox f J 








TT 01 1 )i 


r l^Cr 


TT no -1 ^ 


nnt^ )i 
yup4 




U Of- J. 


TT1 ^Ctt 

uxou 


IT 01 _1 C 

u 9X-X5 


1 TT'^l 

XnjX 


IT Q'3 -1 R 

u yj xo 


r uup 




TOTLZ = 


0550 


TT 01 1 £i 

U 9X-X0 


nnc )i 
yupH 


TT no on 
U yo d\j 


TTI ^TT 
UXDU 




TT 0 
U 0 ( ^ 




TT Q1 -1 R 

u yx xo 


yu ff 


TfYPT 7 — 


1 Q 

-Ly 




TT ft7 0 
U Of- J 


low 


TT 01 - on 


TTI ^TT 
UXOU 


IT 00-01 


high 




TT fl'7 )i 

U 0 f - 4 


TTi ^CtT 

UXoU 


m/VPT *7 — 

XCjIL^ — 


1 n 
19 








U 0 f - ? 




TT 01 - 01 

u yx cx 


high 


TT oil- )l 

u y H 4 


7n^ A 




IT 

U Of- 0 


low 






TT Q)i- t; 

u y4 p 


DO f £ 




TT fl*/- 7 

U 0 f- f 


high 


TT OO- 1 

u y^- X 


high 


TT n)i -1 0 
U y4-Xi: 


noRn 
U£.Or 




TT fl7 n 

u Of- 9 


high 


TT no 0 
U yd- d. 


high 


TT n)i 10 


Ri 70 

01(3 




TT ft7 1 rj 

U 0 f xu 


low 


TT OO- "J 


high 








TT R7 1 1 

u Of -XX 


low 


TT n 0 - )i 


TT1 ^\TT 
UXDU 


TT nil- 0 

u 94- J 


70^ A 




TT Q7 ■! 0 


high 


m/VTlT 7 — 


^ci n 
bpXU 


TT n)i 7 

U 94- 7 


DO f 


£iLL 


TT flV-l "3 

U Of-XJ 


low 


TT QO- t; 


high 


TT q1i-1 1 

u y4 XX 


noRn 


FPT 


u 0 f Xl 


low 


TT QO- ^^ 

u y D 


high 


TT q1i-1 

u y** xp 


Rl 70 
OX f J 


ITPT 






TT OO- 7 

u y^i- f 


high 








TT Q Q -1 

u 00- 1 


TTi ^TT 

uxou 


TT no n 

U 92- 9 


DDr4 




D f UC/ 




TT QP 0 

U 00- 


xow 


TT no in 

u y^f-xu 




TT1 n n 0 
UXUu- d 


5dU3 




u 00 0 


low 


TT no-1 1 

u y^-xx 


TTliTTD 


TT1 nn - 0 
UXUu J 


n^*'i r* 

UUXly 




TT ftft- h 
U 00 H 


high 


TT QO-1 0 


OUJD 


TTI nn_ )i 

UXUU- 4 


0 ( f X 




TT RR- t: 

u 00 5 


low 


TT no_i 


XU f 5 


TTI nn _ t; 
UXUU p 


D 1 r X 




TT flft <C 
U 00- D 


xow 


TT no 1 )i 
U yd-m 




TTI no 1 n 
UXUU -XU 


Q 0 n A 
oJUA 




TT Q p .7 

U Do- f 


high 


TT no 1 c 


1 Cr*fi 
1.0K,d 








IT QP n 

u 00- 9 


high 


TT no 1 ^ 

u 92-iD 


n n c li 
9034 


TTi no i 

U102- 1 


DfuC 




u 00 XU 


low 


TI QO-1 R 

u yc xo 




TTI no - 0 
UXUii- e. 


C^TTO 
pDUJ 




U 88-11 


low 


u 92-20 


UI6U 


U102- 3 


OCIC 




U 88-12 


high 


TOTLZ = 


19 


U102- k 


5U38 




u 88-13 


low 


u 92-21 


high 


U102- 5 


96AP 




U 88-lU 


low 






U102- 6 


CH62 








U 93- 1 


high 


U102- 7 


U023 




u 91- 1 


high 


U 93- 2 


high 


U102-11 


F37F 




U 91- 2 


high 


U 93- 3 


high 








U 91- 3 


high 


U 93- ^ 


Ul6U 


UlOU- 1 


UO23 




u 91- 1+ 


Ul6U 


TOTLZ = 


6510 


UlOU- 2 


U16U 




TOTLZ = 


6510 


U 93- 5 


high 


TOTLZ = 


19 




U 91- 5 


high 


U 93- 6 


high 


UIOI+-II 


low 




U 91- 6 


high 


U 93- 7 


high 


UlOU-12 


low 




U 91- 7 


high 


U 93- 9 


796A 


UlOU-13 


5CF3 




U 91- 9 


35»tP 


U 93-10 


Ai+83 


UlOU-lU 


F9PC 




u 91-10 


Ait83 


U 93-11 


6872 


UlOU-15 


low 








U 93-12 


8U36 









SAC U-UU 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 



Test 5: Loop E - VH = U16U 



MODE: EDGES: THRESHOLDS: 

Normal Clock - Positive Data - High ** 

Start - Positive Data - Low ** 

Stop - Negative Clock - TTL 

ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



= levels are TTL except where noted. 



TT1nl^- 1 




Til no- 
uxuy J 


op JO 




TfYrT.7 = 


opjx 






TT1 ^ilT 
UXDU 


III HQ- 7 
UXU}7 1 


QTT1 ^ 

yuxp 




TT1 1 O-'KO 
uxx^ 


fli F1 
oxr X 




TT1 nt^-i n 


low 


TT1 no-i 1 
uxuy XX 


oyou 




TT1 1 O-'Xfs 
UXX^ JO 


1 TT7R 
XU ( p 


FPT. 


TT1 (T^-l 1 


low 


Til no-i ^ 
uxuy A.J 


pniTH 




in 1 o-xi 
uxx<; j( 




FPT 


TT1 0 

uxup Xt 


low 








TT1 1 !?-'?ft 
uxx^ JU 


7n9n 


FPT. 


TT1 0>;-1 '3 

uxup X^ 


low 


TT1 1 n - li 

UXXU H 


UUt H 




TT1 1 •P-'^O 

uxxc jy 


71 on 
f xyu 


FPT 


III nt^ -1 li 

UXUp XH 


low 


Til 1 D- R 
UXXU p 


TlhlTP 




TT1 1 9-lin 

UXXt *tU 


llFiTT 
Hr iiU 


FPT 






UXXU-Xc 


1 TT7R 










TT-i f\C. _ n 

uxuD y 


f lHyO 


UXXU Xj 


Xq(^^ 




Ux^U'XX 


IPO 71? 




UJ-UU xu 


t uup 








UXfcU XD 


A1 llF 




UXUD XX 




in 1 rt- "5 

UXXU J 






TT1 on-i 7 

UXcU X ( 


■5TT91 
jUtX 




TT1 0 


QTT7P 

yu f V 


in 1 D- 7 

UXXU f 


IlhlTP 
UHUr 




TT1 9n-i R 

UXcU xo 


our u 




Ill -1 

UXUD X J 


qhLh 
ynHn 


TT1 10-11 
UXXU XX 


1 TT?"^ 
XU ( p 


VfT 


TT1 9ri-1 Q 

uxcu xy 


low 




UXUD X«4 




TT1 1 n-1 R 
UXXU xp 




FPT 


















UXcX- X 


0 (f X 




TT1 n7 0 


DUOp 


UXXc 0 


low 






our u 




TT1 n7- "5 
UiU f J 


DUO 5 


III 1 9 - Q 
UXXc y 


ai Lt? 




TT1 91 - 
UXtX J 






UxUf- '+ 










TT1 01 )i 


71 7tl 




III n7- f\ 

UXU f D 


Rppli 


III 1 o_ 0 

UXX C c 


fpr<<; 


FPT 


TT1 91 - 
UXcX p 


nnpw 




TT1 n7-i n 

UXU f xu 


QWLW 
yiiHn 


UXXc J 


7Q^?il 

tyoii 


FPT 


in 91 - (\ 

UXcX 0 


P7TT9 




TT1 07-1 ? 
UXU f xc 




TT1 1 ?- li 

UXX C H 


^ifl7? 




TT1 91 - 7 


J 1 y 1 




UXU f xo 




mi'?- 
uxxc p 


n5ftp 

UcOir 


PPT 


in 91 - 


nlinp 




U107-1U 


79H2 


U112- 6 


8173 


ECL 


U121- 9 


001*9 








UII2-1I4 


35^+? 


ECL 


U121-11 


00I+9 




UI08- u 


35^P 


UII2-15 


99UU 


ECL 


U121-12 


OUOP 




UIO8- 5 


99UU 


UII2-16 


2HP6 


ECL 


UI2I-I3 


3797 




U108-12 


2HP6 


UII2-I7 


1H31 


ECL 


UI2I-II4 


P7U2 




U108-13 


1H31 


UII2-I8 


6536 


ECL 


UI2I-I5 


OOPH 








UII2-19 


9U15 


ECL 


UI2I-I6 


71 7H 




U108- 3 


35^P ECL 


U112-20 


6960 


ECL 


UI2I-I7 


3U21 




UIO8- 7 


99UU ECL 


U112-21 


POUH 


ECL 


U121-18 


6OFU 




U108-11 


2HP6 ECL 


U112-22 


66pU 


ECL 


UI2I-I9 


0000 




U108-15 


1H31 ECL 


UII2-23 


UI4UP 


ECL 


TOTLZ = 


3UU88 








UII2-25 


0000 


ECL 








U109- u 


6536 


TOTLZ = 


19 




UI25- 1 


F996 




U109- 5 


9U15 


UII2-26 


0000 


ECL 


UI25- 2 


96AP 




U109-12 


6960 


TOTLZ = 


6550 




UI25- 3 


38U9 




U109-13 


POUR 


UII2-27 


0000 


ECL 









SAC 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 



Test 6: Loop F - VH = 894H; QUAL - VH = PFA4 



MODE: EDGES: THRESHOLDS: 

Normal Clock - Positive Data - High ** 

Start - Positive Data - Low 

QUAL: Stop - Negative Clock - TTL 

High ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 
Qual - UlOO pin 7 



«« 



levels are TTL except where noted. 



TT 1 - h 

U X H 


1 /^TiT 
XU W 




II 16-1"^ 

U XU X J 


nnnn 


ECT. 

Ill Jj 


u 67-11 


8qUH 




TI 1-17 






TOTI.Z = 


OFLO 




TOTLZ = 


OFLO 




IT 1 -1 R 
U X xo 












TT 

U 


^^7_1 0 
D f Xc. 


1 in A 

XUXA 


QTIAT 


TT 1 -1 Q 
U X Xy 


\jXyC. 




TT 1 Q- 9 
U Xy C 


r r DO 




TT 
U 




HOI Q 




IT 1 -on 
U X^U 


vvih. 




TI 1 Q- 'X 

u xy 0 






TT 

U 


D ( XH 


Q1 P7 




IT 1 
U X 


"aliFR 
jHr 0 




II 1Q- ll 
U X^ H 


h>=;o'^ 


FPT. 


TT 
U 


D f-lP 


6U1? 




IT 1 _'3c; 
U X- 






II 1 Q- K 


4pi^p 




TT 

u 


D ( XD 


A1 np 










TT 1 Q- (\ 
U xy D 


r r DO 




TT 
U 


dl 1 7 

07-17 


pnin? 




IT 1 _ 0 
U X t 






II 1 Q- 7 

u xy- ( 


r r DO 




TT 
U 


D ( -10 


1 1 pj 




TT 1 _ Q 

u J.- J 


nnnn 


vex 








TT 
U 


D 1 19 


PIT "ah 




TTWT 7 — 
XUxJj^ — 


ULr u 




TT on- 0 


hp 7 7 


TTPT 










II 1 - li 
U X H 






IT on- R 

U cU p 






TT 
U 


DO- J. 


1 Qnp 

xy UV^ 




TT 1 7 

U 1- f 












TT 


<R- 0 
DO c. 


RniiT 

OUU f 




TT 1 - R 
U X 0 


r uuw 


PPT 


II llR-1 0 
U H^} X t 


nnnn 
uuuu 




TT 
U 


DO- 3 


HirXjy 




TI 1 - Q 
U X y 


Hf 111 

nv^ Hx 




u 45 X J 


LP77 




TT 
U 


DO *♦ 


f yoy 




TT 1-10 
U X XC 


TIP hi 

HX 


ITPT 


U 4? Xp 


nnnn 
uuuu 


TTPT 
£iL>ij 


TT 
U 


DO- p 


1 1 nfl 
xxuo 




TT t 

U X XD 


uuuu 


TiTT 


TrTPT 7 - 


niTT n 
ur IjU 




TT 
U 


^^R ^; 

DO 0 


r f oy 




TT "1 01 
U X-/lX 


( Hrc 










TT 

U 


DO- ( 


UUnU 




IT 1 -"in 

U X jU 


1 QFO 

x^r 4C 




IT ^^R-1 "5 

u op XJ 


nnnn 
uuuu 




TT 
U 


DO- 0 


f '^jJ 




IT 1 _oo 

u J.- Jj 


nnnn 
uuuu 




TfYPT 7 — 


nFT n 
ur JjU 




TT 

U 


DO- y 


OrUO 




THTT 7 — 


niri n 
ur iiU 










TT 

U 


DO J.± 


ht^Ot; 

4p^:p 




TT 1 -T^^ 
U X jD 






U DO H 


4p^P 




TT 
U 


CR i 0 
DO-Xt 


1 m A 

XUXA 


niTAT 


IT 1 _07 
U J. J f 




im 


U p 






TT 

U 


DO-13 


HOI Q 




TI 1 -•Jfl 
U X 00 


I^ATI^ 




II ^^^^-1 0 


oy *-En 




TT 
U 


DO X H 


Q1 P"? 

yxuj 




TT 1 -'ao 




I?PT 


TfYPT 7 — 


1 7Q^ 

X lyo 




u 


68-15 


^\hl 0 
DtXc 




11 1-Uo 




ECL 


u 66-13 


89UH 




u 


68-16 


Al OC 
















u 


68-17 


COUF 




U 5- 3 


0000 


ECL 


u 66- 2 


FF68 


ECL 


u 


68-18 


7753 




TOTLZ = 


OFLO 




U 66- 3 




ECL 


u 


68-19 


FF3U 




U 5- 6 


0000 


ECL 


U 66- 6 


FF68 


ECL 










U 5- 7 


HCUl 


ECL 


U 66- 7 


i*525 


ECL 


u 


69- 1 


U27i+ 




U 5-10 


0000 


ECL 


u 66-15 


89UH 


ECL 


u 


69- 2 


80U7 




U 5-11 


F23A 


ECL 


TOTLZ = 


OFLO 




u 


69- 3 


AC8P 




u 5-12 


89 UH 


ECL 








u 


69- 1* 


9520 




TOTLZ = 


OFLO 




u 67- 1 


U16P 




u 


69- 5 


1108 




u 5-13 


89I+H 


ECL 


U 67- 2 


80U7 




u 


69- 6 


F789 




U 5-1^ 


0000 


ECL 


U 67- 3 


UP69 




u 


69- 7 


F82U 




TOTLZ = 


OFLO 




u 67- i+ 


F989 




u 


69- 8 


6UIC 




u 5-15 


89l4H 


ECL 


U 67- 5 


1108 




u 


69- 9 


8PU8 










u 67- 6 


F789 




u 


69-11 


^♦525 




U 16- 9 


89i4H 


ECL 


U 67- 7 


OUHO 




u 


69-12 


lUlA 


QUAL 


u 16-12 


0000 


ECL 


U 67- 8 


7233 




u 


69-13 


FFFP 




TOTLZ = 


OFLO 




u 67- 9 


8PU8 




u 


69-1I4 


U87C 





SAC U-U6 



Model 6U62IA - Performaaice Verification 



Board # 6U62I-66503 



Test 6: Loop F - VH = 894H; QUAL - VH = PFA4 



MODE: EDGES: 

Normal Clock 

Start - Positive 

QUAL: Stop - Negative 
High 



THRESHOLDS: 
Positive Data - High ** 
Data - Low ** 
Clock - TTL 
ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 
Qual - UlOO pin 7 



levels are TTL except where noted. 



u 69-15 


61+12 


TOTLZ = 


1796 


U 7^- 5 


FUOC 




u 69-16 


AlOC 


u 71-21 


3781 


U ik-12 


UHAU 




u 69-17 


PUC6 






u 7^-13 


high 




u 69-18 


0F8U 












u 69-19 


FFSU 


u 72- 1 


8989 


U 7*+- 7 


FUOC 


ECL 






U 72- 2 


50P9 


U 7^-10 


7'+P2 


ECL 


u 70- 1 


8989 


U 72- 3 


93A5 


u 74-iU 


low 


ECL 


U 70- 2 


5OP9 


u 72- k 


APFl* 








U 70- 3 


93A5 


U 72- 5 


c6ho 


u 77- 4 


8F6A 




U 70- U 


APFI4 


U 72- 6 


fpUi 


U 77- 5 


IF56 




U 70- 5 


c6ho 


U 72- 7 


6HF0 


U 77-12 


HU5A 




u 70- 6 


FPJ4l 


U 72- 9 


8F6A 


u 77-13 


A0C7 




U 70- 7 


6HF0 


u 72-10 


6UIC 








U 70- 9 


AAF2 


u 72-11 


IF56 


U 77- 3 


8f6A 


ECL 


u 70-10 


6UlC 


u 72-12 


F82U 


U 77- 7 


IF 56 


ECL 


u 70-11 


9501 


u 72-13 


HU5A 


u 77-11 


HU5A 


ECL 


u 70-12 


F82U 


u 72-iU 


9520 


u 77-15 


A0C7 


ECL 


u 70-13 


3733 


u 72-15 


A0C7 








U JO-lk 


9520 


u 72-16 


AC8P 


u 83- k 


H9C2 




u 70-15 


POAU 


u 72-18 


05C7 


u 83- 5 


5ApU 




u 70-16 


ac8p 


u 72-20 


89UH 


u 83-12 


881+A 




u 70-18 


63PH 


TOTLZ = 


1796 


u 83-13 


E2kk 




u 70-20 


89!4H 


u 72-21 


3781 








TOTLZ = 


1796 






U 8U- k 


AAF2 




u 70-21 


3781 


U 73- 1 


8989 


U 8U- 5 


9501 








U 73- 2 


50P9 


U 8U-12 


3733 




u 71- 1 


8989 


U 73- 3 


93A5 


u 8U-13 


POAU 




U 71- 2 


5OP9 


U 73- U 


apfU 








U 71- 3 


93A5 


U 73- 5 


c6ho 


U 85- 7 


FF68 




U 71- h 


APF1+ 


U 73- 6 


FPkl 








U 71- 5 


c6ho 


U 73- 7 


6HF0 


u 85- 1 


FF68 


ECL 


u 71- 6 


FPl+1 


U 73-10 


6i+lC 








U 71- 7 


6HF0 


U 73-11 


FUOC 


U 86- 2 


PU8H 




U 71- 9 


HU5A 


U 73-12 


F82U 


U 86- 3 


8A99 




u 71-10 


61+lC 


u 73-13 


UHAU 


U 86- U 


7920 




u 71-11 


A0C7 


U 73-lU 


9520 


U 86- 5 


U7OF 




u 71-12 


F82U 


u 73-15 


high 


U 86- 6 


3U9H 




u 71-13 


k2lk 


u 73-16 


AC8P 


U 86- 7 


8965 




U 71 -lU 


9520 


u 73-18 


PP9C 


U 86- 8 


80H9 




u 71-15 


16UU 


U 73-20 


89UH 


U 86- 9 


CPFF 




u 71-16 


AC8P 


TOTLZ = 


1796 


U 86-11 


FF68 




u 71-18 


018F 


U 73-21 


3781 


U 86-12 


OOFU 




u 71-20 


89UH 













SAC k-kj 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 



Test 6: Loop F - VH = 894H; QUAL - VH = PFA4 



MODE: EDGES: 

Normal Clock 

Start 

QUAL : Stop 
High 



Positive 
Positive 
Negative 



THRESHOLDS: 
Data - High ** 
Data - Low ** 
Clock - TTL 
ST-SP-QL - TTL 



CONNECTIONS : 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 
Qual - UlOO pin 7 



= levels are TTL except where noted. 



U OD J.J 


rOtr 


TT on- (\ 
u yu D 


J: rtx 


u yc xu 


ur ou 




TT Q<C 1 )i 

U OD-X4 


Hyj? X 


TT nn v 
u yu- f 


Dnr U 


TT 1 

u yt XX 


juyo 




TT fl^C "1 C 


Tin A )i 


TT nn_ n 
u yu y 




TT QO-I 0 
U yc.-Lc. 


rUUD 




U OD-ID 


XArO 


TT 1 n 

u yu-xu 


Ur oU 


TT no 10 


UHUp 




TT Q/C 1 T 


Hi.- (I? 


TT on_i 1 

u yu-xx 




u yt x** 


ttRtp 

UO 1 K> 




u 00 XO 


or 'tL/ 


TT QD-I 0 
U yU ±eL 


DTTP^ 

irUVyD 


TT QO-1 

u yt X5 


UHT n 




TT fl^ 1 n 

u oD-iy 


f 09 


TT fin 1 0 

u yu xj 


00 hA 


TT no 1 ^ 
u y/1 XD 


rr r r 








TT nfy 1 )i 

u yu-x*! 


UO {\, 


TT no 1 ft 

u yt-xo 






TT R7_ 1 

u 0 ( - X 


ftoLw 
oy+n 


u yu 




TT QO-On 
U y c. c.\j 


oy mi 




fp/VTlT "7 — 


AITT n 

Ur LU 


u yu-XD 


r rr r 




1790 




TT fl7 0 

U Of- C 


f (PJ 


TT nn_i A 

u yu XO 


Djrn 


TT no-oi 
U ye. c.1. 


3 f 01 




U 0 f - J 


<: (oy 


TT on_on 
u yu <lU 


oy tn 








U 0 f- •+ 


Arr 4 


XuXJj^ - 


1 7ri<^ 

1790 


TT n 0 1 

u 93- 1 


0909 




U 87- 5 


COUF 


TT ^1 

u 90-21 


370I 


TT 0 0 

U 93- 2 


50r9 




TT QT 


lArO 






TT no 0 

U 93- 3 


n 0 A c 

9jA5 




TT £5 "7 T 

U 07- 7 


93A5 


TT l^i "1 

u yi- X 




TT r^o li 

u 93- 4 


Arr U 




TT Q r\ 

u 07- 9 


50P9 


TT A1 0 

u yx- <: 


5OP9 


TT 0 C 

U 93- 5 


Q/DnU 




U o7"10 


H9A4 


TT 1^1 0 

U 91- 3 


93A5 


TT 0 0 ^ 

U 93- 6 


FFUl 




TT Q'7 1 T 

U Of -11 


91C3 


TT r^l )i 


ArJ? 4 


TT r\ O *7 

U 93- 7 


/'T TT7I fK 




U 0 ( -111 




u yi- 




TT no n 

u 93- 9 






TT Q '7 10 

u 07-13 




TT ni ^ 

u yi- D 


r r41 


TT 00 1 

U 93~l0 


acQtt 

Or OU 




TT fl7 1 )i 

U 0 ( -Xh 


iiiixy 


TT 1 

u 91- f 


Dnr U 


TT no 11 

u 93-11 


1 ^TT)i 

xduh 








Tim c\ 

u 91- 9 


A A 

UAUp 


TT no i 0 

u 93-12 


rUUD 




TT QQ 1 

u 00- X 


09 411 


u yi-iu 


Ur OU 


TT r\o 10 

u 93-13 


UOFP 




TUxhZ, = 


Ur LrU 


TT m -1 1 

u 91-11 


TT Air»Tl 

UArn 


TT no -1 )i 

U 93-1'* 


TTQ 

UO7C 




TT ftR- 0 

u 00 C 




TT 01 -1 0 

u yx-iii 




TT no 1 c 

u yj-xp 


no )i D 
yjHf 




U 88- 3 


CPFF 


u 91-13 


8f6a 


u 93-16 


FFFP 




U 88- k 


3781 


u 91-11+ 


U87C 


U 93-18 


PP9C 




U 88- 5 


OIJHO 


u 91-15 


IF56 


U 93-20 


89UH 




U 88- 6 


3U9H 


u 91-16 


FFFP 


TOTLZ = 


1796 




U 88- 7 


c6H0 


u 91-18 


OI8F 


U 93-21 


3781 




U 88- 9 


fpUi 


u 91-20 


89i+H 








U 88-10 


1470F 


TOTLZ = 


1796 


u 9U- It 


it2lU 




U 88-11 


F989 


u 91-21 


3781 


U 9U- 5 


16UU 




U 88-12 


6hfo 






U 9^-12 


UOFP 




u 88-13 


PU8H 


u 92- 1 


8989 


u 9^-13 


93UP 




U 88-lU 


ltP69 


U 92- 2 


5OP9 












U 92- 3 


93A5 


U 91*- 3 


1*21 U 


ECL 


u 90- 1 


8989 


U 92- U 


apfU 


U 7 


16UU 


ECL 


U 90- 2 


50P9 


u 92- 5 


c6ho 


u 9i*-ii 


UOFP 


ECL 


U 90- 3 


93A5 


U 92- 6 


FPltl 


u 9U-15 


93'4P 


ECL 


U 90- U 


apfU 


U 92- 7 


6HF0 








U 90- 5 


c6ho 


u 92- 9 


UOFP 









SAC U-U8 



Model 6I462IA - Performauice Verification 



Board # 6U62I-66503 



Test 6: Loop F - VH = 894H; QUAL - VH = PFA4 



MODE : EDGES : 

Normal Clock 

Start • 

QUAL : Stop 
High 



Positive 
Positive 
Negative 



THRESHOLDS: 
Data - High ** 
Data - Low ** 
Clock - TTL 
ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 
Qual - UlOO pin 7 



= levels are TTL except where noted. 



U 96- 8 


89UH 


UIO5- 1 


5UUD 


TT1 in "1 0 


UAUp 




TOTLZ = 


OFLO 


UIO5- 2 




uliu-xj 


UAr n 




U 96- 9 


AF2A 


TT1 rtc "y f\ 

ui05"io 


9510 








u 96-10 


0000 


TT1 rtC 1 I 

ui05"ii 




TTi 1 n 0 


UUr r 




TOTLZ = 


OFLO 


UIO5-I2 


r 909 


I'M 1 T 

UllO- 7 


3U90 


CjCL 






TT*i r 1 ^ 

U105-13 


OUHO 


UllO-11 


n A AC 
OAO5 




u 98- 1 


5UU6 


TT*1 rt C ill 

UIO5-I4 


7233 


uiiu-ip 


TT Atrii 




U 98- 5 


A336 


UIO5-I5 


FbHl 








u 98- 7 


AF2A 






U112- 0 


low 








U106- 9 


63PH 


U112- 9 


high 




UlOO- 1 


8OH9 


UlOb-lO 


PP9C 








UlOO- 2 


8965 


UIO6-II 


0507 


U112- 2 


A0C7 


ECL 


UlOO- 3 


7920 


UlOb-12 


OloF 


U112- 3 






UlOO- k 


U89A 


UIOd-13 


oH7d 


U112- 4 


IbUU 


ECL 


UlOO- 5 


489A 


UlOo-14 


bo 5 A 


U112- 5 


UOFP 


ECL 


UlOO- 6 


high 






U112- 6 


93^P 


ECL 


UlOO- 7 


6cf6 


Ul 0 7 - 2 


CoAri 


TT1 1 0 1 )i 

uii2-m 


n A n C 

UAOp 


CiCL 


UlOO- 9 


high 


UI07- 3 


CbAH 


UII2-I5 


TT A TPTI 


ECL 


UlOO-10 


U27'4 


UIO7- H 


ff68 


UII2-I6 


oFdA 


ECL 


UlOO-11 


41dP 


UI07- 6 


bb5A 


UII2-I7 


IF 56 


ECL 


UlOO-12 


190c 


U107-10 


8H76 


T T'1 *\ /'\ 't 0 

UII2-I0 


HU5A 


ECL 






UIO7-I2 


FF68 


UII2-I9 


A0C7 


ECL 


U102- 1 


8OH9 


UIO7-I3 


CHOP 


U112-20 


U21U 


ECL 


U102- 2 


0 ^ r> 

8965 


UIO7-IU 


CHOP 


T T^ «4 ^ '4 

U112-21 


l6uU 


ECL 


U102- 3 


7920 






T T^ ^ A ^ 

U112-22 


UOFP 


ECL 


U102- U 


OHCU 


UlOo- U 


OAO5 


UII2-23 


3U98 


ECL 


U102- 5 


F 1H7 


uxuo- p 


UAr n 




UUUU 


PPT 


U102- 6 


8A99 


UIO8-I2 


8f6a 


TOTLZ = 


1796 




U102- 7 


5UU6 


UIO8-I3 


IF56 


UII2-26 


0000 


ECL 










TOTLZ = 


1796 




UI03- 9 


HA7A 


UIO8- 3 


OAO5 ECL 


UII2-27 


0000 


ECL 


U103-12 


89UH 


UIO8- 7 


UAFH ECL 


TOTLZ = 


1796 




TOTLZ = 


1796 


UIO8-II 


8f6A ECL 


UII2-32 


7UP2 


ECL 


UIO3-IU 


f6hi 


UIO8-15 


IF56 ECL 


UII2-36 


OAO5 


ECL 


UIO3-I5 


5UU6 






U112-37 


UAFH 


ECL 






UI09- U 


HU5A 


UII2-38 


8f6a 


ECL 


UlOU- 1 


5UU6 


UI09- 5 


A0C7 


U112-39 


IF 56 


ECL 


UlOU- 2 


89ltH 


UIO9-12 


U21U 


UII2-U0 


HU5A 


ECL 


TOTLZ = 


1796 


UIO9-13 


16UU 








UlOU-11 


H219 






UII8- 2 


C6AH 




UlOU-12 


91C3 


UllO- I4 


UOFP 


UII8- 3 


C6AH 




UlOU-13 


COUF 


Ulio- 5 


3U98 


UII8- U 


CHOP 




UlOU-lU 


7753 






UII8- 5 


CHOP 




UlOU-15 


9518 













SAC U-U9 



Model 6I462IA - Performance Verification 



Board # 6U62I-66503 



Test 6: Loop F - VH = 894H; QUAL - VH = PFA4 



MODE: 


EDGES: 




THRESHOLDS: 




CONNECTIONS: 






Normal 


Clock 


- Positive 


Data - High 




ST/SP/Start - TPI9 








Start 


- Positive 


Data - Low 


«« 


Qual/Stop - TPI9 






QUAL: 


Stop 


- Negative 


Clock - TTL 




Clock - U99 pin 3 






High 






ST-SP-QL - 


TTL 


Ground - GND (TP) 
















Qual - UlOO pm 7 






** = levels are TTL except where noted. 








UII8-II 


0000 




U121-11 


80U7 


U122 




AF2A 


TOTLZ = 


OFLO 




U121-12 


1108 


U122 


- 6 


2362 








UI2I-I3 


F789 


U122 


- 9 


8pu8 


U121- 1 


I489A 




UI2I-IU 


8PU8 


U122 


-11 


1+525 


U121- 2 


FF3U 




UI2I-I5 


lUlA 


QUAL U122 


-m 


6U12 


U121- 3 


AlOC 




UI2I-I6 


6i4l2 


U122 


-16 


AlOC 


U121- k 


6U12 




UI2I-I7 


AlOC 


U122 


-18 


FF3U 


U121- 5 


lUlA 


QUAL 


UI2I-I8 


FF3I+ 








U121- 6 


8PU8 




UI2I-I9 


0000 


UI25 


- 1 


ff68 


U121- 7 


F789 




TOTLZ = 


OFLO 


UI25 


- 2 


F1H7 


U121- 8 


1108 








UI25 


- 3 


»+525 


U121- 9 


80U7 




U122- 1 


6cf6 














U122- 2 


HA7A 









SAC U-50 



Model 64621A - Performance Verification 



Board # 61+621-66503 



Test 6: Loop G - VH=62A5 



MODE: EDGES: 

Normal Clock 

Start 

Stop 



Positive 
Positive 
Negative 



THRESHOLDS: 
Data - High ** 
Data - Low ** 
Clock - TTL 
ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U66 pin 13 
Ground - GND (TP) 



levels are TTL except where noted. 



u 70- 1 


87P8 


U 07- 1 0000 


U 90- 9 


O3OC 


U 70- 2 


I40U0 


TOTLZ=OFLO 


u 90-11 


no9o 


U 70- 3 


7702 


TT 0 ^9 ^ 9 A ^tTT 

U 87- 2 6ACH 


u 90-13 


HAHA 


u 70- k 


0818 


U 87- 3 d2A5 


u 90-15 


5HC6 


u 70- 5 


Hl+73 


TOTLZ=D'+0 


u 90-18 


56I+A 


U 70- 6 


8P0U 


U 07- 4 Oolo 






U 70- 7 


62HU 


U 07- 5 15A7 


U 91- 9 


C83O 


U 70- 9 


52C6 


U 87- 6 62A5 


u 91-11 


7391 


u 70-11 


8u8U 


TOTLZ=320 


u 91-13 


21AC 


u 70-13 


956C 


U 87- 7 7702 


u 91-15 


HI73 


u 70-15 


CI49U 


u 07- 9 4040 


u 91-18 


3I+PU 


u 70-18 


56 UA 


U 07-10 o2A5 






u 70-20 


736c 


TOTLZ=160 


u 92- 9 


FA68 


u 70-21 


995U 


U 07-11 22P5 


u 92-11 


2UUA 






U 07-12 o7Po 


u 92-13 


C83O 


U 71- 9 


h62P 


U 07-13 d2A5 


U 92-11+ 


FH56 


u 71-11 


H23C 


TOTLZ=80 


u 92-15 


7391 


u 71-13 


ll+UU 


T T ^ \ ± T^ ^ ^ . TT 

U 87-14 P54H 


u 92-18 


62A5 


u 71-15 


A2HC 




TOTLZ=768 


u 71-18 


3I+PU 


U 88- 1 0000 










TOTLZ=0I' LO 


U 93- 1 


87P8 


U 72- 9 


21AC 


U 88- 2 UCUA 


U 93- 2 


l+Ol+O 


u 72-11 


HI 73 


U 88- 3 62A5 


U 93- 3 


7702 


u 72-13 


H62P 


TOTLZ=U0 


U 93- 1+ 


0818 


u 72-15 


H23C 


U 88- U 995U 


U 93- 5 


Hl+73 


u 72-18 


62A5 


U 88- 5 c6h6 


U 93- 6 


8P8U 


TOTLZ=768 


U 88- 6 62A5 


U 93- 7 


62Hlt 






TOTLZ=20 


U 93- 9 


11+1+1+ 


U 73- 9 


low 


U 88- 7 Hl+73 


U 93-11 


A2HC 


U 73-11 


325U 


U 88- 9 8P81t 


u 93-13 


FA68 


U 73-12 


oci+9 


U 88-10 62A5 


u 93-15 


FFAH 


u 73-13 


6lP7 


TOTLZ=^10 


u 93-18 


62A5 


u 73-15 


high 


U 88--11 PF21 


TOTLZ=768 


u 73-18 


62A5 


U 88-12 62H1+ 


U 93-20 


736c 


TOTLZ=768 


U 88-13 62A5 


U 93-21 


995U 






T0TLZ=5 










u 88-1I4 0071 







SAC I+-5I 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 



Test 11: Loop H - VH = 7339 



MODE: EDGES: 

Normal CLOCK - Positive 

START - Positive 

STOP - Negative 



THRESHOLDS: 
Data - High ** 
Data - Low ** 
Clock - TTL 
ST-SP-QL - TTL 



CONNECTIONS: 
ST/SP/Start - TPI9 
Qual/Stop - TPI9 
Clock - U99 pin 3 
Ground - GND (TP) 



NOTE: Remove the clock pod connector from J3. 
** = levels are TTL except where noted. 



TT 1 1 *7 

u 1-17 


low 


U b5- 3 


iiign ciCL 


U120- 


U 


TOO 

733c 




u 1-35 


high 


TT Czi )i 


nign riCL 


U120- 


5 


low 












U120- 


6 


low 




TT 1 

u 20- 1 


OOUP 


TT r\i^ li 

U 9o~ ^ 


<7 T7» "7 

73F7 


U120- 


7 


T'O TT 

733H 




U 26- 2 


7338 


TT C 

u 9°- 5 


OOUP 


U120-11 


high 




U 26- 3 


7333 


U D 


7339 










U 26- h 


733H 


TOTLZ = 


24 


UI23- 


1 


high 




TT 0^ C 


7331 






UI23- 


2 


XOW 




TT C 

U 2b- b 


7329 


TT r\ T 0 

U 97- 2 


•5T7TTrt 

3FU9 


UI23- 


3 


high 




U 2b- 7 


'71-1 0 

7319 


U 97- 4 


high 


UI23- 


6 


low 




TT 0 

U 2b- 0 


7379 


TT rt T 

U 97- 5 


high 


UI23- 


7 


high 




TT 0^ C\ 

u iiD- y 


73Co 


TT ri7 7 

U 97- 7 


low 


UI23- 


9 


hign 




TT 0^ -1 1 

U 2b-ll 


73Co 


TT T 

U 97- 9 


low 










TT 0^ "1 0 

U 2b-12 


7379 


TT '7 11 

u 97-11 


low 


UI27- 


1 


0000 




TT 1 '5 

U 2b-13 


7319 






TOTLZ 








TT O^^ ill 

U 2b-14 


7329 


TT li 

u 99- ^ 


low 


UI27- 


2 


0000 






f JjX 


TT QQ- c: 


high 


TOTLZ 








u 26-16 


733H 


u 99- 6 


high 


UI27- 


3 


0000 




u 26-17 


733c 


U 99- 8 


high 


TOTLZ 




2U 




u 26-18 


7338 


U 99- 9 


low 


UI27- 


8 


0000 




u 26-19 


0000 


U 99-10 


low 


TOTLZ 




21+ 




TOTLZ = 


2U 






UI27- 


9 


0000 








UII6- 6 


high 


TOTLZ 




2lt 




U 53- 2 


73F7 


UII6- 8 


low 










U 53- 3 


8HUa 


UII6- 9 


high 


UI29- 


1 


high 


ECL 


U 53- 5 


659P 






UI29- 


2 


0000 


ECL 


U 53- 7 


3FU9 


UII8- 2 


A285 


TOTLZ 




2U 




U 53- 9 


A285 


UII8- 5 


3FU9 


UI29- 


3 


low 


ECL 


U 53-11 


A285 


UII8- 6 


659P 


UI29- 


U 


7339 


ECL 


u 53-13 


3FU9 


UII8-II 


0000 


TOTLZ 








u 53-15 


659P 


TOTLZ = 


2U 


UI29- 


5 


high 


ECL 


u 53-17 


8HltA 






UI29- 


6 


high 


ECL 


u 53-18 


73F7 


UII9-I6 


73F7 


UI29-I3 


low 


ECL 










UI29-IU 


high 


ECL 



SAC U-52 



Model 6U62IA - Performance Verification 



Board # 6U62I-66503 Test 12: Loop I - VH = 9524 



MODE: EDGES: THRESHOLDS: CONNECTIONS: 



Normal 


Clock - 


Positive 


Data - High ** 


ST/SP/Start 


- TPI9 








Start - 


Positive 


Data - Low 


«« 


Qual/Stop - 


TPI9 








Stop - 


Negative 


Clock - TTL 


Clock - U99 pin 3 












ST-SP-QL - 


TTL 


Ground - GND (TP) 






** = levels are 


TIL except where noted. 










U 1- 3 


952U 


ECL 


U 97-11 


87UI 




UI23- 


3 


nign 


U 1- U 


high 


ECL 


U 97-12 


F8C7 




UI23- 


. h 


AT r f 


u 1-17 


87U1 




U 97-lk 


0505 




UI23- 


P 




U 1-35 


952U 










UI23- 


0 


L/Or H 


TOTLZ = 


Uoo 




UII6- 1 


952U 




UI23- 


f 










TOTLZ = 


Uoo 




UI23- 


9 


HH12 


U 97- 2 


0505 




UII6- 6 


952U 




UI23- 


11 


C6fU 


U 97- h 


F8C7 




TOTLZ = 


200 




UI23- 


12 


I26F 


U 97- 5 


952U 




UII6- 8 


0000 




UI23- 


13 


6UP2 


TOTLZ = 


I4OO 




TOTLZ = 


Uoo 




UI23- 


lU 


C6fU 


U 97- 7 


0000 




UII6- 9 


high 










TOTLZ = 


200 










UI26- 


5 


52F8 


U 97- 9 


0000 




UI23- 1 


high 




UI26- 


7 


F7PF 


TOTLZ = 


1 




UI23- 2 


low 




UI26- 


11 


F7PF 



SAC U-53 



Model 6I462IA - Performauice Verification 

NOTES 



SAC U-5U 



Model 6U62IA - Adjustments 



SECTION V 
ADJUSTMENTS 

5-1. INTRODUCTION. 

5-2. This section describes adjustments and checks required to return the instrument 
to peak operating capability after repairs have been made. 

5-3. The Strobe Generator Adjustment procedure is Test 9 of the Perforraaince 
Verification, and the Threshold Adjustments procedure is Test 10. 

5-4. SAFETY REQUIREMENTS. 

5-5- Although this instrument has been designed in accordance with international 
safety standards , general safety precautions must be observed during all phases of 
operation, service, and repair of the instrviment. Failure to comply with precau- 
tions listed in the Safety Summary at the front of this mamual or with specific 
warnings given throughout the manual could result in serious injury or death or 
damage to equipment. Service adjustments should be performed only by qualified ser- 
vice personnel. 

5-6. EQUIPMENT REQUIRED. 

5-7. TEST EQUIPMENT. 

1. U 1/2 Digit Multimeter accurate to +/-1 mV. (Hewlett-Packard Model 3^66A or 
equivalent . ) 

2. Dual Channel 100 MHz bandwidth Oscilloscope with delta time measurement 
capabilities accurate to 0.5 ns. (Hewlett-Packard Model I7U3A with probes.) 

5-8. ACCESSORIES. 

1. Hewlett-Packard Model 6^000 series Mainframe with extender board and SEB 
Extender Cable. 

5-9. PROCEDURE. 

5-10. This procedure assumes that all other modules of this system are working prop- 
erly, and are calibrated and meet or exceed their respective specifications. 

NOTE 

Installation and removal of P.O. Boards must be done with the AC 
Power for the Mainframe turned off. 

5-11. STROBE GENERATOR ADJUSTMENTS. (TEST 9) 

a. Place the State Analysis Control Board on an extender board. The SEB Bus 
Cable must be connected to the Acquisition Boards. Use the extreme ends of the 
cable to avoid reflections. 

b. Select opt_test , press RETURN . The display will indicate the option 
modules present and the card slot number in which they are located. 



SAC 5-1 



Model 6U621A - Adjustments 



c. Press "slot number" , RETURN . "Slot number" is a number from 0 to 9 equal 
to the location of the State Analysis Control Board. 

d. Press nan , "slot number" , test , 9 , repeat , RETURN . The CRT should now 
display "Test 9' Strobe Generator Calibration". 

NOTE 

All of the following Strobe Generator measurements must be made 
within +/-0.5 ns of the indicated value. All transitions are 
measured at the ^0% level (ECL Level) . 

e. Connect channel A of the scope to TP2 (State Recognition Strobe), and trig- 
ger on channel A. Connect channel B to TP3 (Pipeline Strobe) . Using adjust- 
ment Tl, (R8), adjust the rising edge of channel B as indicated in the follow- 
ing diagram: 



CH A, TP2 ^ 



CH B, TPS 



|<« 95nS »J[ 

y v_ 



f. Connect chaiinel A to TP3 (Pipeline Strobe), and trigger on channel A. 
Connect channel B to TPIO (Overview Strobe). Using adjustment T2 (R7) » adjust 
the falling edge of channel B as indicated in the following diagram: 



CH A, TP3 




1^ 18nS ^ 

I 



CH B, TPIO 




g. Connect channel B to TP5 (Qualified Write Strobe). Channel A remains on TP3, 
and is the trigger for the scope. Using adjustment T3, (R6) , adjust the rising 
edge of channel B as indicated in the following diagram: 



OH A, TPS 




[m 42nS mJ{ 

I 



CH B, TPS 




SAC 5-2 



Model 6U62IA - Adjustments 



h. Connect chaimel A and B to TP5 (Qualified Write Strobe). Trigger on channel 
A. Using adjustment Tk, (R3)« adjust the pulse width as indicated in the fol- 
lowing diagram: 



CH A&B, TPS / * \. 

\ I 
48nS »-| 



i. Connect channel B to TP9 (data Valid Strobe). Channel A remains on TP5, and 
is also the trigger. Using adjustment T5 (RU), adjust the falling edge of 
channel B as indicated in the following diagram: 



CH A, TPS 



■120nS- 



CH B, TP9 



j. Pressing stop , end , RETURN , end will end the Strobe Generator Calibration 
Performance Verification. 

k. This completes the Strobe Generator Calibration. 
5-12. THRESHOLD ADJUSTMENTS. (TEST 10) 

a. Place the State Analysis Control Board on an extender board. The 1MB and 
SEB Bus Cables do not need to be connected. 

b. If it is not already disconnected, disconnect the Clock Probe Cable from J3. 

c. Connect the ground lead of the DMM to the GND TP near U70. See Figure 5-I. 

d. Using a jumper wire, connect TPll and TP12 together. 

e. Connect the positive lead of the DMM to Testpoint 11. 

f. Select opt_test , press RETURN . The display will indicate the option 
modules present and the card slot number they are located in. 

g. Press "slot number", RETURN . "Slot number" is a number from 1 to 9 equal 
to the location of the State Analysis Control Board. 

h. Press run , "slot number" , test ,1,0, RETURN . The CRT should now dis- 
play "Test 10:Threshold Circuit Calibration". 

i. Each time the RETURN key is pressed, the D/A Converter will be set to a new 
value. Press RETURN until "Reference = -k.267 V Negative Limit" is displayed. 

SAC 5-3 



Model 6k621A - Adjustments 



j. Adjust -FS, R2I4, to -U.267 V +/- 1 mV. See Figure 5-I. 

k. Remove the jumper from TPll and TP12. Positive lead of the DMM remains on 
TPll. 

1. Continue pressing RETURN xintil "Reference = +1*33 mV ECL (-1.3 V)" is 
displayed. 

m. Adjust +FS2, R25, to +^33 mV, See Figure 5-I. 

n. Each time RETURN is pressed, the D/A Converter will be set to a different 
value. Press RETURN six times and verify that the value measured on the DMM is 
within +/-33 mV of the value displayed for all six DAC levels. (If the voltages 
are not correct, there is most likely a problem in the DAC and must be correc- 
ted using the Performance Verification.) 

o. Connect the positive lead of the IMl to TP12. 

p. Continue pressing RETURN until "Reference = +U33 mV ECL (-1.3 V)" is 
displayed. 

q. Adjust +FS1, R23, to +U33 mV. See Figure 5-I. 

r. Each time RETURN is pressed, the D/A Converter will be set to a different 
value. Press RETURN six times and verify that the value measured on the DMM is 
within +/-33 mV of the value displayed for all six DAC levels. (If the voltages 
are not correct, there is most likely a problem in the DAC and must be correc- 
ted using the Performance Verification.) 

s. Press end, RETURN, end to exit the State Analysis Control Performance 
Verification. 



SAC 5-U 



Model 6U62IA - Adjustments 




3 5 

GNon □ Q Dp ^ 



T5 T4 T3 T2 T1 



STATE CONTROL BOARD REV A (64621-66501) 

r—\ CLOCK POD 




□ 

13 

TEST POINTS 

1 NBSRS 

2 PBSRS 

3 PBPLS 

4 HBOWRT 

5 HBQWRT 

6 LMACS 

7 PBOVRST □ 

8 LBOVEN 

9 LDV 

10 HOVS 

11 UTHSH2 

12 UTHSH1 

13 NO NAME 

14 SA CLOCK 

15 LSCLK 

16 LRUN 

17 LMS 

18 LPPSTB 

19 LMAP2 



□ 
11 

n 



□ 

14 



□ 

15 

□ 
GND 



□ 



□ 



64621A STATE CONTROL 
ADJUSTMENT LOCATIONS 



Figure 5-1. Adjustment Locations 



SAC 5-5 



Model 6I+62IA - Adjustments 



NOTES 



SAC 5-6 



Model 6U62IA - Replaceable Parts 



SECTION VI 
REPLACEABLE PARTS 

6-1. INTRODUCTION. 

6-2. This section contains information for ordering parts. Table 6-1 lists ab- 
breviations used in the parts list and throughout the manual. Table 6-2 lists all 
replaceable parts in reference designator order. Table 6-3 contains the names and 
addresses that correspond to the manufacturers' five-digit code numbers. 

6-3. ABBREVIATIONS. 

6-U. Table 6-1 lists abbreviations used in the parts list, the schematics ajid 
throughout the manual. In some cases, two forms of the abbreviation are used: one 
all in capital letters, and one partial or no capitals. This occurs because the ab- 
breviations in the parts list are always capitals. However, in the schematics and 
other parts of the manual, other abbreviation forms are used with both lowercase and 
uppercase letters. 

6-5. REPLACEABLE PARTS LIST. 

6-6. Table 6-2 is the list of replaceable parts and is organized as follows: 

a. Chassis -mounted parts in alphamvunerical order by reference designation. 

b. Electrical assemblies sind their components in alphanumerical order by 
reference designation. 

c. Miscellaneous parts. 

The information given for each part consists of the following: 

a. The Hewlett-Packard part nvunber and the check digit. 

b. The total quantity (Qty) in the instmiment. 

c. The description of the part. 

d. A five-digit code that indicates the manufacturer. 

e. The msuiufacturers ' part number. 

The total quantity for each part is given only once - at the first appearance of 
the part ntimber in the list. 

6-7. ORDERING INFORMATION. 

6-8. To order a part listed in the replaceable parts table, quote the 
Hewlett-Packard part number and check digit, indicate the quaoxtity required, and ad- 
dress the order to the nearest Hewlett-Packard office. 

6-9. To order a part that is not listed in the replaceable parts table, include the 
instriament model number, instrument repair number, the description and fianction of 



SAC 6-1 



Model 61t621A - Replaceable Parts 



the part, and the number of parts required. Address the order to the nearest 
Hewlett-Packard office. 

6-10. SPARE PARTS KIT. 

6-11. A spare parts kit is not available at this time. 
6-12. DIRECT MAIL ORDER SYSTEM. 

6-13. Within the USA, Hewlett-Packard can supply parts through a direct mail order 
system. Advantages of using the system are as follows: 

a. Direct ordering and shipment from the HP Parts Center in Mountain View, 
California. 

b. No Maximiun or minimum on any mail order (there is a minimum order amount, 
for parts ordered through a local HP office when the orders require billing and 
invoicing) . 

c. Prepaid transportation (there is a small handling charge for each order). 

d. No invoices -to provide these advantages, a check or money order must accom- 
pany each order. 

6-lU. Mail-order forms and specific ordering information are available through your 
local HP office. Addresses and phone numbers are located at the back of this 
manual. 



SAC 6-2 



Model 6U62IA - Replaceable Parts 



Table 6-1. Reference Designators and Abbreviations 









REFERENCE DESIGNATORS 








A 


- assembly 


F 


- fuse 


MP 


- mechanical part 


U 


integrated circuit 


B 


= motor 


FL 


= filter 


P 


- plug 


V 


vacuum, tube, neon 


BT 


- battery 


IC 


= integrated circuit 


Q 


^ transistor 




bulb, photocell, etc 


C 


^ capacitor 


J 


= jack 


R 


- resistor 


VR 


voltage regulator 


CP 


= coupler 


K 


- relay 


RT 


- thermistor 


W 


- cable 


CR 


- diode 


L 


= inductor 


S 


= switch 


X 


socket 


DL 


= delay line 


LS 


= loud speaker 


T 


- transformer 


Y 


- crystal 


DS 


- device signaling (lamp) 


M 


= meter 


TB 


- terminal board 


z 


tuned cavity network 


E 


- misc electronic part 


MK 


= microphone 


TP 


=- test point 












ABBREVIATIONS 








A 


- amperes 


H 




N/0 


normally open 


RMO 


rack mount only 


AFC 


= automatic frequency 


HDW 


— hsrcfwBrG 


NOM 


- nominal 


RMS 


root-mean square 




control 














AMPL 


" amplifier 


HEX 


- h ' 

— nsxBQonsi 


NPO 


- negative positive zero 


RWV 


- reverse working 






HG 


= msrcury 




(zero temperature 




voltage 


BFO 


- beat frequency oscillator 


HR 


- hourls! 




coefficient) 






BE CU 


beryllium copper 


HZ 


- hertz 




- negative-positive- 


5-B 


slow-blow 


BH 


- binder head 








negative 


SCR 


screw 


BP 


bandpass 








- not recommended for 


SE 


selenium 


BRS 


- brass 


IF 


— intermeuiste ttsq 




field replacement 


SECT 


section! St 


BWO 


backward wave oscillator 


IMPG 




NSR 


■ not separately 


SEMICON 


semiconductor 






INCD 


— inc3noesc6n t 




replaceable 


SI 


silicon 


COW 


- counter-clockwise 


INCL 


^ include's' 






SIL 


silver 


CER 


ceramic 


INS 


insulationied) 


OBD 


^ order by description 


SL 


slide 


CMO 


- cabinet mount only 


INT 


- internal 


OH 


oval head 


SPG 


- spring 


COEF 


coeficient 






OX 


^ oxide 


SPL 


- special 


COM 


common 


K 


kilo 1000 






SST 


stainless steel 


COMP 


= composition 










SR 


■ split ring 


COIHPL 


^ complete 


LH 


= left hand 


P 


- peak 


STL 


steel 


CONN 


- connector 


LIN 


= linear taper 


PC 


^ printed circuit 






CP 


= cadmium plate 


LK WASH 


= lock washer 


PF 


=^ picofarads- 10 12 


TA 


tantalum 


CRT 


- cathode-ray tube 


LOG 


= logarithmic taper 




farads 


TD 


time delay 


CW 


^ clockwise 


LPF 


^ low pass filter 


PH BRZ 


- phosphor bronze 


TGL 


toggle 










PHL 


^ Phillips 


THD 


thread 


DEPC 


- deposited carbon 


M 


- mitli-10--3 


PIV 


^ peak inverse voltage 


Tl 


titanium 


DR 


- drive 


MEG 


- meg^ioe 


PNP 


^ positive-negative- 


TOL 


tolerance 






MET FLM 


- metal film 




positive 


TRIM 


trimmer 


ELECT 


- electrolytic 


MET OX 


^ metallic oxide 


P/0 


^ part of 


TWT 


traveling wave tube 


ENCAP 


encapsulated 


MFR 


= manufacturer 


POLY 


- polystyrene 






EXT 


" external 


MHZ 


= mega hertz 


PORC 


porcelain 


U 


micro- 10 6 






MINAT 


- miniature 


POS 


- position's' 






F 


-- farads 


MOM 


"- momentary 


POT 


■ potentiomoter 


VAR 


variable 


FH 


- flat head 


MOS 


= metal oxide substrate 


PP 


- peak-to-poak 


VDCW 


dc working volts 


FIL H 


- fillister head 


MTG 


- mounting 


PT 


= point 






FXD 


- fixed 


MY 


= "mylar" 


PWV 


^- peak working voltage 


W/ 


" with 














w 


watts 


G 


=^ giga 1109) 


N 


= nano (10-91 


RECT 


- rectifier 


WIV 


working inverse 


GE 


" germanium 


N/C 


- normally closed 


RF 


= radio frequency 




voltage 


GL 


glass 


NE 


^ neon 


RH 


=■ round head or 


WW 


- wirewound 


GRD 


= ground(ed) 


Nl PL 


-- nickel plate 




right hand 


W/O 


without 



SAC 6-3 



Model 6I+62IA - Replaceable Parts 




Figure 6-1. Probe Cable Breakdown 



SAC 6-U 



Model 6U62IA - Replaceable Parts 



Table 6-2. Replaceable Parts List 



Reference 
Designation 


HP Part 
Number 


c 

D 


uty 


Description 


II MX.. 

Mfr 
Code 


IVIir rari IMUlTIDcr 




L 46''1 A 






siaif; analysi. 


S I.ONTRIiL 






I B 58 0 


64621 A 


Al 








10HH7 state; analysi 


1 CONIROI 


BOARD 




2 1 1 4 i 1 0 


64621-66503 




0 1 M) "» (1 




5 0 


CAPAIi^ITOR rXD 


. nioF 


(BO ,''0':i 


1 OOUDC 


CIR 


2FI480 


01 60-2055 


A l 


U X 0 U (1 11 J J 






CAPAr.:iTOR-rxi) 


. OlUF 


-fBO-2 0 7. 


lOOUDC 


CFR 


213480 


0 1 6 0 -2055 


A ICS 


11 i60-;;of.iS 


9 




CAPACITDR FXD 


. II 1 OF 


iflO 2 OX 


1 OOUDC 


CFR 


2843 0 


0 16 0-2055 


A1C4 


0 160 2(15S 


9 




CAPACITOK-FXD 


. OlUF 


-FE10-2 0y. 


lOOWDC 


CFR 


28480 


016 0--2055 


Al Cj» 


u 1 0 11 / 7 0 






CAP At: [TOR FXI) 


6U0PF 


1-1% lOOVDC MICA 


21:148 0 


0 1 6 0-3793 










SAPACITOR-FXI) 


470PF 


-v-57. SOOWDC MICA 


7'>1 ^6 


DM1 !."'r47 1 J 0 0 0 uy 1 CP 


Air? 








r.AP AC f Tl JR FXl) 


<I7I)PF 


-1-57. .iOO'v'DC MICA 


721 36 


i)H 15f'47 1 J 030 OUy 1 CR 


A IC8 


0 160--3(167 


5 


1 


CAPACITOR-FXD 


20 OPF 


-1—57. 300UDC MICA 


21348 0 


0160 3067 


Air:9 


II16I)-;!7V3 


4 




CAPACnilR FXI) 


(jflOPF 


-1-17. 1 ilOUDC MICA 


I'lMBO 


0160-379:5 


A 1 Cl 0 


U ^ *T U — U 1 H f 






CAP ACT TOR -F'XD 


47 OPF 


-1--57. JlUiyDC MICA 


7 :' I .16 


DM1 5t" 47 1 J 0 0 OUVl CR 




(lie 0 '■>[)'^'-" 






CAPACTltlR T X D 


, II 1 UF 


IBO I'd 7 


t OOUDC 


a. R 


■■R4'10 


D 1 6 0 2 055 


A 1 C 1 


U >. OU J) - J u tl 






CAP AC f TftR -FXI) 


ttr +aii-?ii7. sovpr. cf:r 


''0480 


n 1 /.I n .T=i n n 

U I (.) 11 11 1.1 


AlCKi 


l)l/,0-t'05S 


9 




CAPAl: 1 TOR F XD 


. H I OF 


i i;io ;i0 7 


1 0 O'JDC 


CER 


:>n4Go 


9 1 60-2055 


AlCM 


0160-2055 


9 




CAPACITUR-FXl) 


. 0 1 UF 


-1-130-207 


lOOWDC 


CFR 


28480 


0160-2055 


Al Clo 


11 1 0 u *_ 11 iJ 






CAP AC f TI'iR F XI) 


. 0 1 1 IF 


-itlO -2 07 


1 aouDC 


CER 


.1348 0 


0160-20.K,i 




n '1 ^ n n i\ 






CAPACITOR -FXI) 


. 0 1 UF 


-1-0 0-2 07. 


lOOVDC 


CIR 




0 1 ^> 0 ■"■ 0 ^'i '"^i 


A 1 r 1 7 


IJ J 0 U — ,."> / / ,1 






CAPACITDR FXI) 


.'.HDPF 


1-17 lonyoc MICA 


^-IMRtl 




A1C18 


11160-2 055 


9 




CAPACITOR-FXD 


. 0 1 UF 


+80-207 


lOOVDC 


CI R 


28480 


0160 -2055 


Alt: 19 


II U, 0-2 055 


9 




CAPACITIIR- FXI) 


. Ill OF 


-IBO-PO'X 


1 OOUDC 


CER 


2F148 0 


0160-2055 


A I C20 


tl II 0 2 () 5 J 






CAP AC I TOR - FXD 


. 0 1 UF 


+B0-207 


1 OOUDC 


CFR 


28 480 


0160 -20-.K.( 


A 1 f ^ t 1 


[) 1 /j 1) ... 2 (J^.i'tj 


9 




CAP AC T T 1 iR F KI) 


, i) 1 1 IF" 


-100 2»X 


1 OOUDC 


PER 


21340 0 


0 16 0-2 0 55 


A 1 Cui? 


0 ). 60 "12 0 55 






CAP AC I TOR -F XD 


. inuF 


-i-BO-JMIZ, 


1 OOUDC 


CI 10 




0 1 6 II ■ 2 0 5'"1 


Aic?:i 


l)l/^.0"20SS 


9 




CAPACtTIIR FXD 


. II 1 UF 


-i-ao fill 7 


1 0 OUDC 


CFR 


2848 0 


0160-2055 


A1C24 


())60-2O55 


9 




CAPACITOR-FXD 


. OlUF 


-l-f3 0-2 0 7 


1 OOUDC 


ecu 


28480 


016 0 2055 


Al Lr-.-.j 


Illi'iO ^.0..>.,i 


9 




CAPAl; I TliR FXD 


, 111 OF 


iBO ?:.v/. 


1 OOUDC 


CER 


' 




A 1 C^b 


() 1 60 — 2055 






CAPACITOR FXD 


. 0 1 UI 


-l-aO-207 


lOQUDC 


CF V 


-> (} i-> 0 


0 1 M' 0 " " 


A 1 [' ? 7 


!) 1 A H — 2 0 h ft 


9 




CAP AC TTIiR FXD 


, II lOF 


IBO 2 0 7 


1 OOUDC 


IT-R 


2 11 4 Fi 0 


0 16 0-2 055 


AlC2t) 


()160-2()55 


9 




CAPACITOR-FXD 


. 0 1 UF 


+80-207 


10 OUDC 


CFR 


211480 


0160-2055 


AU.;29 




9 




CAPACITOR FXD 


. Ill OF 


+8 0-2 07 


1 OOUDC 


CER 


284B0 


0160-2055 


A 1 C 3 0 


0 1 60--2055 






CAPACITOR-FXD 


. 0 1 UF 


+80-207 


1 OOUDC 


CFR 


,..8 480 


0 1 /:.(, L.O,.i,.j 




'MM) 






CAPACITOR FXD 


. 01 OF 


+80-207 


1 OOUDC 


Ct-R 




fi 1 £. n 'In ^ 
U 1 0 U 1: IJ . J ij 


A l CS"' 


tl t OU 1:; '.1 






CAPACITOR-FXD 


. 0 1 UF 


+ 80-207. 


10 OUDC 


CFR 


'■'11480 


0160 ""2 055 


A1C.?3 


0160-2055 


9 




CAPACITOR FXD 


. 0 1 OF 


+B0-2 07. 


1 OOUDC 


CFR 


2B4B0 


0160-2055 


A1C34 


0160-2055 


9 




CAPACITOR-FXD 


.OlUF 


+80-207 


10 OUDC 


CFR 


28480 


016 0 -2055 


Al C35 


0 1 60-2055 


9 




CAP AiC C TOR ■■ F'XD 


. OlUF 


+ 8 0-2 0 7 


1 OOUDC 


CER 




\} I c> u c. 11 *j 0 


Al C36 


(i 1 tn .... 11 1 no 






CAPACITOR-FXD 


SVPF -1 


-57 HQOVDC MICA 


-' 


U 1 f • I) U 1 / 


A 1 f ; 7 


11 1 n — ri 1 711 






CAP AC I TOR F XD 


?7PF 


-57 30IIUDC MICA 


''114811 


II I fl - n 1 '7P 


AlC3a 


0160-20SS 


9 




CAPACI rOR -FXD 


. 11 1 1 IF 


+80-207 


10 OUDC 


CFR 


28480 


0160 -2055 


Ati:3V 


1)160-2055 


9 




rflPACTiriR FXD 


. II lOF 


+80 207 


1 OOUDC 


CER 


284811 


0160-2055 


A 1. C40 


u 1 ou <; u 






CAPACITOR-FXD 


, OlUF 


+80-207 


1 OOUDC 


CtR 


213480 


01 60-3055 




n 1 ^ 0 '"»(!•■■•=" 






CAP AC t TtJR F XI) 


. OlUF 


180 207 


1 OUUDC 


l,ER 




0 "• '1 


Al CA'-' 


0 1 60-'2(l 55 






CAPACITOR-FXD 


, OlUF 


+80-207 


10 OUDC 


CFR 


'^1*1480 


^ ^.^ 2 Q *^i5 


Al(:43 


niiSO-2055 


9 




CAPACITOR- FXD 


, 0 1 OF 


+80-207 


1 OOUDC 


CER 


2848 0 


0160-2055 


A1C44 


0160-20 55 


9 




CAPACITOR-FXD 


. 0 1 OF 


+80-2 0 7 


10 OUDC 


CFR 


28480 


0160-2055 


A1C4^ 


0160-*^0.j.j 


9 




CAP AC ITOR FXD 


. 0 1 UF 


180-207 


1 OOUDC 


CFR 


2848 0 


11 1 A fl fl '■i'^ 
IJ i 0 \i U. \} t-l \J 


A 1 C46 




^ 




CAPACITOR-FXD 


.OlUF 


+80-207 


10 OUDC 


CI R 


"'8480 


0 1 ^1 0 ~2 0 55 


A 1 C47 


0 1 60-2055 


9 




CAPACITOR FXD 


. OlUF 


+80-207 


1 OOUDC 


CER 


28480 


016 0-2 0 55 


AlC4a 


0160-2055 


9 




CAPACITOR-FXD 


. 0 1 UF 


+80-207 


1 OOUDC 


CF R 


2848 0 


0160-2055 


A1C49 


0160-2055 


9 




CAPACITOR FXD 


. 01 OF 


+ 80 -2 07 


1 OOUDC 


CER 


28480 


0160-2055 


A1C50 


0 1 60-2055 


9 




CAPACITOP-FXD 


. 0 1 OF 


+80-207 


10 OUDC 


CFR 


2114110 


0160-2055 


A 1 fi 1 


II 1 ''t 0-2055 


9 




CAPACITOR FXD 


. II 1 UF 


+8 0 2 07 


1 OOUDC 


Ct-R 




0 i 6 0-2 055 


A 1 C52 








CAPACITOR-FXD 


.OlUF 


+ 110-2(17 


10 OUDC 


CIR 


"'13480 




AU;fj3 


i3 160- ;■,'!) l^^.'-j 


9 




CAPACITIIR - F XD 


. 01 OF 


• H 0 :< II 7 


1 0 OUDC 


CER 


28480 


0160-2055 


A1C54 


0 i 60-2055 


9 




CAPACITOR-FXD 


, 0 1 UF 


+80-2 0 7 


10 OUDC 


CFR 


28480 


0160-2055 


A 1 C , J .J 


0 16 0 0 .J .1 






CAPACI I OR FXI) 


. 01 OF 


+80 -2 07 


1 OOUDC 


CC R 


.-1348 0 


1/ 1 D U L 11 .1.J 


A 1 C^6 


0 ibU — cUua 


9 




CAPACITOR-FXD 


■ OlUF 


+80-207. 


lOOVDC 


CF « 


284E10 


0 1 0 -2055* 


A1C57 


0160-2055 


9 




CAPACITOR-FXD 


. 0 1 UF 


+ 80-2 OX 


1 OOUDC 


CER 


2848 0 


0160-2055 


A1C58 


0180-1746 




6 


CAPACITOR-FXD 


ISUF-f- 


107 20UDC TA 




56289 


lSOD156X90aOP2 


A1C59 


lllBO-1746 






CAPACITOR FXD 


1511F-F- 


107 20WDC TA 




S6289 


150DlH6X902nEi2 


A1C60 


oiao-r/46 






CAPACITOR-FXD 


150F+- 


107 20VDC TA 




56289 


150D156X9020H12 


AlCfcl 


0140-0149 


6 




CAPACITDR-FXD 


470PF 


+-5X 300UDC MICA 


72136 


DM15F471J030 0UU1CR 


A1C62 


0160-,1SOB 


9 




CAPACITOR-FXD 


lOF IBO 20X SOWBC CFR 




2848 0 


0160-3508 


A1C63 


0160-2055 


9 




CAPACITOR-FXD 


.OlUF 


+80-207 


10 OUDC 


CFR 


28480 


0160-2055 


A1C&4 


0180-1746 






CAPACITOR FXD 


150F + 


107 20VDC TA 




5 628 9 


150D156X9020B2 


A 1 C65 


0180-1746 






CAPACITOR-FXD 


15UF->- 


107 20VDC TA 




5.'j2B9 


1S0D156X9O20B2 


A1C66 


01130-1746 






CAPACI rOR FXD 


150FH- 


107 20VDC TA 




5 62B7 


150D15.6X902UB2 


A 1 C67 


0160-2055 


9 




CAPACITOR-FXD 


, OlUF 


+80-207 


lOOVDC 


ce;r 


28480 


0160-2055 


A1C68 


0160-2055 


9 




CAPACITOR-FXD 


.OlUF 


+H0-20Z 


lOOUDC 


CER 


2E14flO 


0K.0-205S 



See introduction to this section for ordering information 

SAC 6-5 



Model 6U62IA - Replaceable Parts 



Table 6-2. Replaceable Parts List (Cont'd) 



Reference 
Designation 


HP Part 
Number 


c 

D 


Qtv 


Description 


Mfr 
Code 


Mfr Part Number 


A 1 r; R 1 


1 V 0 1 ■ D 0 f 1 0 


3 




nrnDF ^iwrtr.HTNr; onv nnoMA 2NS T>r)-35 




„ 


"» 0 n 1 iw^ =" n 
1 y u 1 IJ u ■ i\) 


A 1 CR2 


1 V 0 1 - tl (1 u U 


3 




DiaDi'-suiTHHiNf; aou 200MA 2NS DO-35 




"'!14n0 


1 0 11 i n 4^ 11 

I y 11 1 11 II -.1 11 




1901-00 50 


3 




i)in;or GunnniNQ 8[)u 20iirtA 2Ni;i i>n-35 




2i;UBl) 


1 90 1-1) 050 


A 1 J3 


1,.',j1-7()0,j 


3 




L* U IN FN 1 - Ij 1 U 1% \J\i r i. IN n r 0 1 1 I 1 r 




2841:1 11 


1 2.1I ■ 70 0 .1 




jE a / 0 ■! _- rj n fi 1 
fi t htz 1 ■- W,j 11 11 J 






E.XIRACTDR P.C. HOARD 




->p inn 


d t, ' > 1 Q"^. fl H 1 
( 1 1 T) ' 1 t3^J U IJ J 




*t 0 c 1 *~ 1:1 J U U 1,,. 






EXlBflKTOR-P .C; . HOARD 




^n-i'io 




A1MP3 


14B0 "0116 




1 


PIN-KRV ,06H-IN DIA .25 r.N L.G STL 




2B480 


1480-0116 


A 1 Ql 


I B54~- 0 ?M 5 


1 


t 


TRANC.lcii flB NPN Q i PIi=3SnMM PT— 10HMU7 




0 4713 


2 N , W 0 4 


A ■] R 1 


ij / 1.) / u ,5 y 




1,-,. 


RflSIGTDR 51,1 17. r 1 r,^ 0 i 100 






( • I/O I fl 1 n 1 ,..,r: 


A 1 R2 


li 6 V(U -66 1 2 


1 


20 


RESISTOR 2K .1X,125U F HXH-lOO 




2 B 4 8 0 


0698- 6612 


A1R3 


0698-6612 


1 




RESISTOR PK .\% .ir':-.U F TC"»< -100 




28480 


iJ6y8-6612 


A 1R4 


21 00-3123 


0 


8 


RESISIOP-TRMB 51111 11)7. C SH>F-A»J 17 


IRN 


0 ;.' 1 1 1 


43l'501 


A 1 K 


i'' 1 0 0 — 31 23 


0 








O4.M 1 1 


43PV> 01 


A 1 R6 


2 1 00 1 23 


0 




RFSlsrilk' TRMR 500 107 C SIPl'.-ADJ 17 


I1.'N 






A l K 7 


210 0 - 3 1 f-^ 3 






Rr r.lSUiR- IRhR 500 1 07. C STDt- ADJ 1 7 ■ 


I ilN 


r'l 1 1 


43P'^' Ol 


A t. R8 


2 1 00--3I23 


0 




Rrsistnp-TRhR 500 107 C SIDF-AD.T 17 


TRN 


0 2111 


43 P 501 


A1R9 


0698-6612 


1 




REl'.lSTilR ;?K ,1Z,1?5U E TO-=0t 100 




284P0 


U6y8 -fa6l2 


A 1 R 1 0 








D i:: r.; T c TDiJ \ "Z i ''"^li C Tc — (i .t..-. i (1 n 
r( 1 1:1 1 UK iiiv I(..uw r i \.. ■- u + i ii u 






0698-661 2 


A li R 1 1 


0757— 11394 


(J 




RESISTOR 51.1 IX .125M F TOIH-100 




2 4 , ")46 


Til ■- 

C 4 ■ 1 / 8 - 1 0 - rj 1 H 1 r 


A 1 R 1 2 


0757-0394 


0 




RESISTOR 51.1 17 ,125U F Tr.= 0 + -100 




2 45 46 


V.A 1 /8 - T 0 -5 ) !>' 1 -f 




0 69B-3447 


4 


1 


RESISTOR 422 17 .125W F TC==01 100 




24546 


n4 l/8-T0- 422V-i f 


A 1 R 1 'I 


0757-0346 


2 


4 


RESISTOR 10 17 .125U F TC=ni-100 




24 546 


t";4- l/a-TU-KiRO' F 


A 1 R 1 "ij 


0757~D346 






RESTSTIIR in 17 1 ''^.U P TP— H-* -1 (10 




24546 


L4 1 / b" 1 11 1 U K il r 


A l R 1 6 


0 7 S 7 - 0 3 4 6 






RESISTOR 10 17 .125U F T(: = 0+-10 0 




-J I- 


f A 1/0 T i\ 1 IH'> fl I— 

1.4 1/01 11 — 1 II 1' 11 -r 


A 1 R 1 7 


0698 -344S 






RESISTOR 340 17 . 1 ?5U F rC"Ot-100 






r /I '1 / 0 I (1 - T i:> 'J cr 
L. -H I 0 1 11 ^1 1 » r 


A l R 1 8 


0757-0346 


2 




RESISTOR 10 17. ,1?SU F TC-Ot-lOO 




245 46 


04 1 /B-TO-1 Or.'O F 


AlW IV 


0698-3455 


4 


2 


RESISTOR ?6II< 17 ,1.-'5U F rr:=Oi 100 




2 4546 


C4 1 /8- T0-26r,l F 


A 1 R 2 0 


U /:i7t3 — J 1 vJ^ 


0 




PPQTCTOP A "^'-M^ 17 1 '^SIJ P' TP— Pt-inn 




' ^^'^^^ 


I,. 't 1/(1 1 1.1 H- ( 1 r 


A 1 R 2 1 


0 698 - 31 ,1 L 






RESISTOR 3.4HK 17 , 1 25U E TC=1H lOD 




■ > A ^. , 


r .1 1 / u 1 (1 — ? il n 1 f 


A 1 R22 


0 / 1 9 8 ~ 3 1 5 4 


0 




RESISTOR 4.22K 17 .ll'SU F Tr; = Oi-llHl 




''4'-'46 


P 1 / 0 _ T f 1 A '■> 'T i P 


air:-' 3 


IIO-3i;-.'3 


0 




RESISTOR-lRhR 5110 107 C SIDE AO.l 17 


IRN 


0 - Mil 


4 3P501 


AIR21 


2100-3123 


0 




RESISTOR-TRMR 500 lOZ C SIDE-ADJ 17 


TRN 


0 2 1 1 1 


43P5ni 


Al R2.J 


1 1) 0 — 3 1 3 






PF' 1^ T i:;TriD — TP MQ 11 11 1 117 P Sinp-ATIT 17 


IRN 


0 1 11 


43P -.J 0 i 


A "1 R26 


0757-0394 


0 




RESISTOR 51,1 17 .12SU F TC=0+-100 




24546 


C4- 1 /8 -TU —51 R 1 -F 


A t R27 


0757-0437 






RESISTOR 4.75K 17 .125U F TC=0+ 100 




2 4546 


C4 1 /8 ■ r 0 - 475 1 ■■ F 


AI,R2a 


0757-0437 


2 




RESISTOR 4.75K 17 . 1 25U F TC=0+-100 




24546 


C4 1/8-TU -4751-F 


A1R2V 


0757-0283 


6 




RESISTOR 2K 17 .IgSU F Tt:=--Oi 100 




24546 


C4- 1/8-T 0-2001 - F 


A "1 R 3 0 


fl 757- 0 283 


6 




Kr.tj J. a 1 i.PK (Ztv i /. , 1 jw r 1 v — u ' — i u u 




24546 


C4 ■ 1 /a-TO -2 0 0 1 -F 


A 1 R .5 1 


06 9^-6612 


^ 




RESISTOR I>l< .tZ.lPSU E TP-OI-lOO 




28480 


i) 6 y 8 6 6 1 2 


A i R32 


0 757- 0 394 


0 




RESISTOR 51.1 17 .12SU E T( : = 0 + - 1 0 (1 




2 4 V 1 4 6 


CA ■ 1 / 8 ■ "1 I! - '"t 1 t - F 


A1H33 


0757-0438 


3 


3 


RESISTOR 5. UK 17 .125U E rC==0i -100 




24546 


C4 1 /8- TO -51 1 1 F 


A1R3A 


0757-0438 


3 




RESISTOR 5.11K 17 ,125U F TC=0+-100 




24546 


f.:4 1/8-10-51 1 1 -F 


Al R35 








D (ft:; T QTi'iD 1 1 iv 1 7>'=.i.i r" tp— o j.... 1 n fi 
K 1 .:) 1 UK ij i . I I /• . I i'xjw t 1 I., — it ^ I 11 11 




24,.)46 


Pa. 1/Q^Tfl ='1Di IT 
L4 1 / M 1 It ..J 1 K i r 


A 1 R36 


069t! -6612 






RESISTOR 2K .i2.1?-5U F TC==0+-100 




2B4B 0 


IJ698-6612 


A 1 R 3 7 


U 6 98-66 i 2 






RESISTOR 2K .17. .125U E TC=Oi 100 




28480 


U 69 8-6612 


A1R38 


U69B-6612 






RESISTOR 2K .1Z.125U F TC=0l-100 




28480 


U698-6612 


A1R3V 


11698-6612 






RESISTOR 2K .17 . 1 25U F TC=iO+ 100 




28480 


0698-6612 


A 1 R40 


u ij90 -66 12 






DccrcTciD oi/ i '/. 1 tr Tr'~ (1 — 1 (1 n 
KtaJ.alUK iiiv . J. A , t i..>.i<M r ii. -ut— iiiij 




284B0 


M J-. (:t — A 1 '3 
U070 001i_ 


Al R41 


iW 0 Q *^ il, ^ r> 
UoVtf DOltr 






RESISTOR 2K .17.125W F Tr:=0< 100 




28480 


0 698-6612 


A l R42 


0757-0726 




1 


Kr.biblOIx Dll 1/- . iZ.iW r It.. — in — 1 11 u 




245 46 


r^c i/A_Tri 

L. 1 J ■■ ■ 1 / 4 ~ 1 l.l — -J I I \< - 1- 


AIR43 


1)698-6612 






RESISTOR 2K .1X.12SU F TC'Ot 100 




28480 


0698-6612 


AIR44 


0698-6612 






RESISTOR 2K .1Z.125W F TO0+-100 




28480 


0698-6612 


Al R4S 








RESISTOR 2K .12.125U F lC = i]i 100 




28480 


I] 6 9 B - 6 6 1 2 


A 1R46 


u,0?a-6612 






RESISTOR 2K .17. .125U F T(; = 0<-100 




2l-!480 


1)698-6612 


A 1 R 4 7 








D I"' c T c- T no '.'1/ -1 V 1 on 1 1 r" t n — n .• i n n 

K 1 ;:> 1 ^) 1 UK 1. Is , 1 /. , i t '.j W r M,, - IJ t i ij u 




28480 


U6Va-66l2 


A 1 R4a 


0757— 0 ,5'?4 






RESISTOR 51,1 17 .125U F TC=0+-100 






C4 1 /8— T 0 -51 R 1 - F 


A J R 4 9 


0757-0394 






RESISTOR 51,1 17 ,125U E TC=0+-100 






L4 1/W lU ,j1K1 r 


A 1 R 5 0 


0757- 0 438 






RESISTOR 5.11K 17 , 1 25U F TO0+-100 




245 46 


C4 1/8-T 0-51 1 1-F 


A1R51 


u653-f>612 






RESISTOR 2K .17 .125W F TCs^D-i 100 




28480 


06V8-6612 


A 1 RS2 


0f:»98— 3455 






RESISTOR 261K 17. . 1 25U E TO0+-100 




24546 


C4— 1 /8-TO —261 3 -E 


Al R53 


06V8— 6612 






RESISTOR 2K .17 ,125U F TO-Ol 100 




28480 


0678-6612 


A l R54 


0757-0394 


0 




RESISTOR 51.1 17 .125U F TC=0+-100 




24546 


C4— 1 /8-TO — 5 1 R 1 — F 


Al 


0757-0394 


0 




RESISTOR 51.1 1% .125U F Tr;=0+-100 




24546 


f.yi 1/0 I'd "^lOX ET 

L 4 - 1 / tt — 1 0 — .J 1 R 1 ' E 


A'iR56 


0 757-0 394 


0 




RESISTOR Sl.l 17 .125U F TC=0+-100 




24546 


C4 1 /8-TO -5 1 R 1 -E 


A1R57 


0757-0394 






RESISTOR 51.1 1% ,125U F TC=0+-100 




24546 


C4 1/8-T0-51R1 F 


A1TP2 


0360-0535 


0 


13 


TERMINAL TEST POINT PCB 




0 0 0 tl 0 


ORDER BY DESCRIPTION 


A1TP3 


0360-0535 


0 




TERMINAL lEST POINT PCB 




0 0 0 0 0 


ORDER BY DESCRIPTION 


A1TP5 


0360-0535 


0 




TERMINAL TEST POINT PCB 




0 0 0 (J 0 


ORDER BY DESCRIPTION 


AnP9 


0360-0535 


0 




TERMINAL TEST POINT PCB 




0 0 0 0 0 


ORDER BY DESCRIPTION 


A i TPl 0 


0360-053S 


0 




TERMINAL TEST POINT PCB 




0 (i 0 (1 0 


ORDER BY DESCRIPTION 


AlTPll 


0360-0535 


0 




TERMINAL TEST POINT PCB 




00 000 


ORDER BY DESCRIPTION 


A1TP12 


0360-0535 


0 




TERMINAL TEST POINT PCB 




00000 


ORDER BY DESCRIPTION 


A1TP14 


0360-0535 


0 




TERMINAL TEST POINT PCB 




00000 


ORDER BY DESCRIPTION 


GND 


0360-0535 


0 




TFRMINAL TEST POINT PCB 




0 0 0 (1 0 


ORDER BY DESCRIPTION 


GND 


0360-0535 


0 




TERMINAL TEST POINT PCB 




0 0 0 0 0 


ORDER BY DESCRIPTION 


Giro 


0360-0535 


0 




TERMINAL TEST POINT PCB 




0 (1 (1 (1 0 


ORDER BY DESCRIPTION 




O360-O53S 


0 




TERMINAL TEST POINT PCB 




00000 


ORDER BY DESCRIPTION 


Al TPi9 


0360-0535 


0 




TERMINAL TEST POINT PCB 




00000 


ORDER BY DESCRIPTION 



See introduction to this section for ordering information 

SAC 6-6 



Model 6U62IA - Replaceable Parts 



Table 6-2. Replaceable Parts List (Cont'd) 



Reference 
Designation 


HP Part 
Number 


c 

D 


Qtv 


Description 


Mfr 
Code 


Mfr Part Number 




1 r< v.( IJ i U 






li,, '.jlf^ilL AN^1LYZLI^' iJUN'l k LJL 1 ( i' 


;'fi)4B (1 


1 Nf.t 4~5 0 10 


A 1 U2 


1 8 10-0 273 


9 


S' 


NI-. TUGK' K TG 1(1 "CirMyO.O i'.lilM X 9 


0 I 121 


21 0 A471 


A 1 1.) 3 


1 (iJ 1 0 — 0 29B 


8 


1 2 


NH.TWnRK ■ Wli! 8 10 Bt.P240.0 (iHM X V 


0 1121 


2 1 0 A ;i* 4 1 




1 1'l 0 3 ''"'i 9 


7 




MISn Et'L 14- INP 


0 7 li? '3 


1" 1 1,1 0 1 4 P C. 




1 t:i n — 1 Ann 




■■ 


T c p&i IT i;pi AtiiTi niiAi^ 'i r Kit) 
1. 1., I 'M 1 r.l.j-L. HN U IJL'HU .1. |vr 


0 471 3 


M C 1010 4 F 


A J. U6 








i 1' r'Aii:: tn Mnia niiAii "3.. Tt.)i> 
1.1.1 (.iH ir c.IjL.. INUlT W'KtI' i:. i ri.y 


0 4/13 


M{.' 1 0 1 0 21' 


A 1 U7 


1 Ri'l) — 23^'>9 






1 r M 1 r r" 1' 1 1 - t m p 

11.^ II 1. - /\.r I. L/L. A "^T i. Iv| 




i:' '1 n fi 1 A p p 


AJ.U8 


ie;)20"0;,-'69 


4 


2 


T.c, c;ati;: ttl nand «uad 2 inp 


(1 1 29!:, 


SN74 0 3N 


AlU'? 


IBl [)~D29B 


B 




NEIWDRK Rr.B 10 !';rP240.0 Cihrt X 9 


01 121 


2 1 0A241 


A lUl 0 


i c.i 1 n fi c.i n 
1 l;i 1 u 11 1,'. (:l IJ 




3 


Nh.TUURK—RI'-f;) 1 0 "S:)'! P 1 0 . 0 K Oilh X 9 


0 1 1 2 1 


2 1 0 A 1 0 3 


A 1 1.) 1 1 


1 lit 1 0- OPH 0 


8 




jvr.. 1 w i.JK i\ J> J . \ H ) 1 r 1 l> 1 J l\ i_J > 1 n A / 


011.1 


1 0 A 1 0 .! 


A 1 U 1 1 








K\V-" T I.I i'\ I'J w . D r" o n '7 ii f\ \ i^a v 
Nr. t WLJlT II. — K r b o ;:> 1. 1 4 / . (1 UHn X 4 


n 1 121 


;.Mllil!470 


AlUl.i 


lBl(3-()29t:) 


8 




nf;.i wriRK -Rf:!;; id •■,rp240.o trnM x 9 


!i 1 1 ; ' 1 


P I GAP 41 


AllJi4 


1820-1201 


b 


1 


IC GATE TTL AND QUAD 2-INP 


01295 


SN7'lL5i)BN 


A J. UU-i 


1 S:) 1 0 - 0;;',73 


9 




Nl." TUf'lRK — Rl. S 10~f'IP470,0 Ullh X 9 






A 1 1 ) 1 6 


1 r(;;* 1) - 1 831 




,) 


ir P-A I F FC\ l iR (JI!AD P- INP 


'l 971 \ 


nl. ! U 1 .) ■! 








6 


IC CN 1 1^ El'l. P 1 N SYNCHRO P nfl- t;i Di;i I 1 Ij 


1)7'.' /• 3 


PI 11 1; 1 ^)Dr, 


A 1 u 1 n 


1 V-i '1 n 1 "?( .'1 > 






11" i ' N 1 R 1 1 1. Ti 1 N n Y Nl IR B 1' 1 ■ f - 1)1-. Pi - 1 R ). !ii 


!) '/26 3 


1 1 l i 01 6 ■')("; 


n ) U19 


IHLiO-OIUIP 


1 




JC CfMi NMH [JMAD 2 IMP 


0 4713 


MPl 11 1 02P 


aiu;:m) 


iBr>()-()Hij:,' 


1 




1 n TA 1 |: 1",L M iR I.J11AD P- .i.NF' 


n 47 1 3 


MCI 01 n;'P 


A J. U2 1 








I Lti'.H E r. 1.. I) 1 Y p r p o !ii - 1. o ti". i ■ ■ t r Ji c dual 


0 47 1 3 


hP. 1 013(11 


Al IIP? 


1 ffP (1 — 1 'SAd 






1. 1., l.t.ri r.UL U IT 1 I:. P l.ii:) I: DItV;. ■ IK 1. Is IJIJAI . 


0 47 1 3 


KB 1 0 1 3 (1 1. 


A 1. U23 


1 n n — (1 n 1 7 






T f"* IT" C r' r* 1 T\ M / TM 1 A 1 

S. \., r Y- t \.,\.. If -n/ b iK.lHl. 


0471 3 


MC;i (1 1 31P 


A 11,124 


{)-i4()n 


7 




JiC ivAHii ECL AND QUAD 2- itNP 


0 4713 


MCI 11 04P 


A1U25 


iNi:i4-S018 


1 


1 


iL, LLOLK uLNEkAlUR 


2B4H0 


1NE4-5018 


A 1 U 2 6 


1 BP 0 — ? 075 






p. n J. ..jL. ml I. ':> 


0129 5 


SN741-S245N 


A L U27 


1 (;1 1 0- 0 2B0 


g 




Wl- T i.ini? 1/ — 0 1 (1 .>c:; 1 D 1 11 (11/ ni 1 M ¥ o 

ni.. 1 wi.piT c — K 1.. J 1 u ,.i .1 1 1 11 . (1 IV i.ii in A y 


0 1 1 r* 1 


21 (1 P. 1 0 3 


Al 1J2B 


1 ]"(26- 1)27 1 




.., 


IP nC AMll P P (( I't T D .P Pl/P 
p I., 1 1 1 hi ri r I'M 1.) 1/ 1. r 1 r l\ I.T 


li' 1 L 9 '..) 


P.N7274 ] P 


A I. U2V 


U;i26-0271 


0 




U: BP fiHP CP a BIP-P PKG 


O12'."o 


ilN7:'741P 


All)30 


1 1126- 1)544 


0 


1 


U OFF B-CIP-C 


0 47 1 3 


MPUO'd 


A 1 U 3 1 


1 iill 0 — 0298 






M T 1,1 rii.) 1/ D 1 i'' 1 <i [") ''J ii o n rf"i 1 1 i*A V rj 


0 1 1 2 1 


21 (1A241 


A 1 U32 


1 l-J 1 0 " 029B 


B 




hi F 1 LM 1 ''} u IJ r 1.: in "i p ''i a n '\ Pi > i «* v o 
IN r_, MAi 1 ' ' c }\\ , ) 1 u > 1 1 ' ij , i) i.' 1 1 n A / 


0 1 l 2 1 


2 1 0 A2 4 1 


A 1 1)33 


1 C.J 1 U U 1... 7 Q 






N 1- 1 W [ 1 K - R 1 1 ii j 1. P 2 4 [) , 1) Bl lh X 9 


(1 1 1 7:' 1 


21 (1A241 


A1U34 


181(1-1)278 


8 




Nf.lUnKK ki 'il \l\ :.,IPP10,1) lU-IH X 9 


0 1 1 ;'M 


21 OA 2 41 


A1U35 


1 BIO - 0298 


8 




NFTWURK-RIvS 10 ;i;ilP240.0 OHM X 9 


0) 1 21 


21 llfi241 


A :l U 3 6 


1 H 1 6— 1 4^>2 






1 L, r.l ,1. / 1 iJ K 1 IJ • ' ( 1 (w 1 H 1 Ir Hn . ■ 1 0 " N b U" Iv 


!-i 0 16 7 


hDrt 1 04;''2H 


A "i \i27 


1 1 0 0 2 9 8 






INI.. 1 WLlivlv K 1; .b 1 11 ;:i .1 r t. *HI . H l.ll in X V 


0 1 1 ? 1 


2 1 (1A:*41 


t\ 1 LJ3B 




"1 




l.C f-.Cl../ll)K 1 024 (IK) l-JTAT RAH 1 0- NS D 'i 


GO 167 


hP.Ml 0422H 


A ). U39 


is;iio-0 29a 


8 




NETUORK-RFS 1 0 -;il\P;?4() . 0 OHM X 9 


0 1 1 2 1 


21 (1A241 


Al U4 0 


1F116-1462 


2 




ire Er,l./10l< 1 024 (IK) BTAT RAM 10-NS 0-E 


BO 167 


MliMl 0 422H 


A 1 U4 1 


1 CrI 1 U U t.. T CJ 






NI: r UfIRK — RES 1 (i - S il P 24 0 , 0 OHM X 9 


0 1 121 


21 (1A241 


A H M 2 


1 B 16-1 4 Z))-* 






IL II,I../1.)I< 10. 4 (IK) liTAI RAH lO-N!^? D- P. 


'■iO 1 67 


Mp.M 1 n4;''<'H 


Al U43 


1 R 20 — 0 R 06 






,[ C.A 1 1 ECl. OR - N( IR DUAL 4 S - INP 


0 471 3 


MPJ 0 1 09P 


A1U44 


1B20- OB 02 


1 




lie GATE Fli.L. Ni.iK QUAD 2- liNP 


04713 


KBi 01 o;>p 


A1U45 


1B20-1400 


7 




IC CAiE ECl. AND (^UAD 2. - INP 


0 4713 


KCl I1104P 


Al U46 


l 0 "OPl 9 




4 


NT. I Wl.iKK ni .b \:i ■ ) 1 r t.:t. U . 11 (.M ln X 4 


0 1121 


2 0 86221 


A "] U47 


1 i I P 0 - 0 B 1) 9 






!(.. R(,UR El.L L. TNIi RCWR QUAD 2-INP 


0 471 3 


MCI 01 15P 


A J. U 4 1:1 


\ [-] \ 0 "" 0 2 1 9 






Nt;,1 Wl.jR K ■ R F:. *Si B !.> 1 P 22 0 . 0 OIlH X 4 


0 1 1 2 1 


20 8F(221 


A 1 U49 


1B10-021V 


3 




NFTWORK-RFS 8-G.lP220,0 OHM X 4 


01121 


2(1811221 


AlU^iO 


1B20- 0809 


B 




liC RC^R PCL LINE HCX'M QUAD 2-INP 


0 471 3 


MBl 01 I'SP 


A 1 US 1 


1 Si) 1 0 ■■■ 0 1.? 1 9 






Mlir T L.I n P 1/ D r" p a c: H" n 't^ n f\ i i w * 


01121 


2(1811221 


Al IJ52 


1 82 0 ~ 1 1 73 






TP VI -| rj fPI 111 ...Tn .CP 1 ni 1AT\ n T MO 

Al.. 1 K r:.l.L. I 1 1 . 1 i.J-r.l.L QL-mO 2— J.Nr 


0 <1 7 1 3 


MC 1 0 1 24L 


A 1 L)53 


1 !:l20-2 024 






TP IIU TTI 1 P 1 T lilf T\r>MP llfTI 

J I.. VK 11 1... I..b l. .1. Nr. UK VK UL. I L 


0 129;:i 


8N74I S244N 


A1U54 


1826-0856 


'7 


2 


iC row 8-B-D/A PD-DIP-P PKC 


34335 


AMftOeOAPC 


A 1 U55 


1B26-0856 


7 




IL CBNU 8 -B -D/A 20-DTP -P PKG 


34335 


AM,'. OBOAPi; 


A1U5^> 


IBl 0-0273 


9 




Nl^ I LifiT k ■ 0 r Q 1 n ■ Q 1 P J7 fl n ni iM V O 
[■(r. 1 iwi.i.* i\ K c i3 I 11 . > 1. r -H / U . IJ 1 It In a V 


Oil 2 1 


21 (1A471 


A 1 U57 


1 Ci 10- 0302 






INI.. 1 wi.irc r, K l a c( b .1 1 n / . U UMrl a 4 


01121 


2(1BP470 


Al I.J58 


1 13 J _ J 3 7 






TP r' P" 1 / 1 PI 1/ i. A Tr'T 'T 1'^ T a T 1^ iV X4 y J.U'^ 

1. U 1 1,1 . / 1 11 K o -4 1.1 J. 1 1:) 1 H 1 H An 6' Nb 


07263 


1 0 1 45APC 


A 1 U59 


1816-1338 


1 




IC ECL/IOK 64-EaT STAT RAM 6-NS 


0 7263 


ioi4SftPi:: 


A 1 U6 0 


1R16- 133B 


1 




iliC ECL/IDK 64-Bf.T SiAT RAM 6-N!5 


0 7263 


10145AP(.: 


Al U61 








IC F(i:L/10K 64-FiiliT STAT RAM 6-NS 


0 7263 


1 014SAPC 


Al IJf>2 


1 B2 0- 1 1 73 






T 1"^ VI T D r' P' 1 TTI T n C" PI P'VI 1 AT\ *^ T 1^1 Q 

I.I. AL 1 K t.l.^L 1 1 !.. ■ 1 IJ— b.L,l. tijUHl; i^~INP 


0 4713 


HCl 0 1 24L 


A 1 Ufe3 


1 fi?n~i 1 71 

il.lt-U l k / 0 






IC XLTR ECL TTL-TO-ECI.. QUAD 2-INP 


04713 


Mf-.l 01241. 


AlUf>4 


1820-1173 


1 




IC XLTR ECL TTL-TO-ECL QUAD 2-TNP 


0 4713 


MC10124L 


A 1 U65 


lOaO-1 1)52 


5 


10 


IC XLTR ECL ECl ~TO-TTL QUAD 2~INP 


0 4713 


MCI 01251- 


AlU6fe 


1R20-1 052 






TC XLTR ECL ECLTO-TTL QUAD 2INP 


0 47 1 3 


«C1012«,I_ 


A J1U67 


1020-1997 


7 


6 


IC FF TTL LS D-TYPF PUB -t OUL-TR IC PRI -IN 


01 P95 


BN741 S374N 


A1U68 


1820-1997 


7 




IC rr TTL LS D- TYPE P OS- EDCE-T R li G PRL-liN 


n 1 295 


SN74LS374N 


A1U69 


1 ft 2 0 "• 1 9 9 7 






IC FF TTL LS D -TYPE POS-EDCL-TR IC PRI -IN 


0 1 P95 


SN74I S374N 


A1U7(] 


1816-130B 






JiC TTL L 1 024 (IK) STAT RAM 75 NS 3 5 


07263 


9:'.P422PC 


A1U71 


1BU~1308 






IC TTI.. L 1024 (IK) STAT RAM 7^^i-Nfi; 3 G 


07263 


931 422PC 


A1U72 


lBlfe-1308 






IC TTL L 1 024 (IK) STAT RAM 75 NB 3- S 


0 7263 


93L422PC 


A1U73 


lHU-1308 






IB TTL L 1024 (IK) STAT RAM 7^v-NS 3 -S 


0 7263 


93L422PC 


A1U74 


182 0-1 052 






rc X1..1R ECL ECL-TO-TTL UUAD 2-JNP 


04713 


MCI 0125L. 


AIU75 


iaiO-0273 


9 




NETUORK-^RES 10-SIP470.0 OHM X V 


01131 


210A471 


A1U76 


181 0-0273 


9 




NETWORK RES 10~SIP470.D OHM X 9 


011?>1 


21 Ofl471 



See introduction to this section tor ordering information 

SAC 6-7 



Model 6k621A - Replaceable Parts 



Table 6-2. Replaceable Parts List (Cont'd) 



Reference 
Designation 


HP Part 
Number 


c 

D 


Qtv 


Description 


Mfr 
Code 


Mfr Part Number 


[177 


1 H i'' 0 -- 1 0 fv r* 






IT y( 1 B FPi t~i'i . in-.-i Ti riiiAii - i mp 

1. ij Al-. I k r I.* K.. K., I . i IJ 1 1 P_, lij LIH U '.. i, IVr 




lir 1 n 1 '""1 


A l L178 


1 1.1 i-U 1 / Qt) 


4 




11.. L.(N 1 K t-l.'l- tl X IN oTrU..llKl.l r U -IJ tl.lM:>ll t K .1 Ij 


07 3 


\- 1 li 0 1 fa in.. 


AU)7V 


1820-1788 


4 




IC CN1R E:CL bin synchro POS-flBCE-IRIG 


0 7263 


EI O016OC 


A1U80 


ia2»-1831 


B 




IC GATE ECL OB BOAD 2-INP 


04713 


MClO t 031. 


A11J81 


1 r)'^> 11 1 "Jiifu 
A n u 1 / ifn 






IP PM1 13 V Xj r w c-v MPi.ii) n d ri(;;....ir. T^(■■■r.^...T rj in 
1.1.. 1 . IN 1 K t:.i,,i_ P J. IN ::> T IN t -t IK u r 1.* in t:. Pi.jI::. 1 K l.i.i 


0 7? 6 3 


IT. 1 fl n 1 £ ("• 

1 1 l| U 1 CI wL, 


ri l U8'^ 


1 5120 - 1 '7RB 






T f p w x'u FC'i i( "1 M <^ Y wr 1.41? R p i i*'; ^pnp r -tis v p 

.1 lh IN 1 1*. P_ ^ . 1 f M [y _) 1 IN ^ / n 1*; r < 1 ■. ) l._ l/V:r I 1 K .1 1 f 




I.' 1 (1 (1 1 (,r\p 
r 1 11 u 1 o 


A 1 1 1 B ^^ 


1 n? 0 -- 1 (ly 1? 






in XI iR f r 1. 1 - "[ n I II i>ji)Af) 2- iNP 


0 471 t 




A i U84 


1H20-1052 






IC XLTIv' ECl.. FDL -TG-TTI. Q'..(AI> 2 - lNF 


0 4713 


MCI 012SL 


AUJB5 


ii;!:? 0-11 73 


1 




rc XI IR e;:cl til -tg e?.cl quad 2-:i;np 


04713 


MCI 012 4L 


A 1 UB6 


ia.30-1997 


' 




.L L, r r I 11.- l. o 1/1 T r r.. r Up r;. LH.il,: 1 K .L l,i r K 1 . IIN 


01 29^1 


C;il|' 7 A 1 CT'"/ AM 

biV / *H...bo / H IN 




1 (■.>':> fi — 1 A 'i>Q 
1 Ml' 11 1 *ii:^n 






.1.1., ni.) AK / l/H 1 H i:f i 1 L. L.. in < 1 1.) I L.ltVI::. IiJUm.U 




C (vl "7 H 1 i O M 

biN /■'tL.o I i..'ON 


A 1 U88 


1 R PO — 1 'IPS 






T n M M V D / ri AT A ..^ 1 T ri 1 n t j'l..- 1 „i t m r" en i a T^ 


0 1 '■'9'^ 


bN / 4L.b 1 i-iHN 


AUiB9 


1820-1997 


7 




TC TIL LS5 rrPE pbb-edqe- irtg r'i-ii..-:i:N 


0129S 


SN74LS374N 


A 1090 


1816-1308 






IC Tn L 1024 (IK) STAT RAM 7S~N*n 3 S 


0 72^/3 


93L422PC 


Al U91 


(IJ "1 i 1 "I (1 IS 






IP 1 "T 1 1 1 nj'A / 11/ "1 QIAT &AM '7'':;...WC> J — C 

.1. i.y 1 11.. 1... IIJ^..-^ *. .1 l\ ^ !n 1 H t Kf-in / ri',/ .n 


0 7263 


93L422P L 




1 f.i 1 O 1 11 (3 






T f T "T" I 1 1 fl "".J ^ 1 1/ ^ T A T DAM -7 1-" M('* ~Z O 

it.. ML L 1 U ti*l (IK) b 1 H I K Hn / .„p N> i >n ;:i 





■ ODP 


A1U93 


1 n 1 i lino 






IP 111 1 1 11 '1 a / V \ r'TAT DAM '7'^'".-. uir; 7 <■' 






A J, UV4 


1320-1 052 


5 




IC XI..TR ECL F.CL-TO-TTL qUAI) 2-INP 


0 4713 


MCI 01251. 


AU)V5 


1810-0273 


9 




NETWORK-RES 10 niP470.(i OHM X 9 


0 i 1 2 1 


2J 0A471 


A IU96 


1 R '"^ 0 1 197 


9 




I (.i CA 1 L T 1 1., t J:i NANI) QIIAO 2 INI* 


0 1 29vi 


BN74I_ SOON 










.1. L, rl 1 1 l_. 1 . ,! Is of-iK r i.J;:) 1;. t/'vl:. 1 11 1. 1,> 


0 1 .■.'95 


SN"'' 4 L SI 0 9 AN 


AIU98 




3 




it., r 1 1 1 L L b J l<. pHK r Vlb ■■ L I.K;>r ** 1 K J. In 


0 1 -'9^:1 


SN74I S 1 09 AN 


A 11) 9 9 


ip:-.: 0-1 197 


9 




i;C CAIF ITl. LS NANI) QUAD 2- IKP 


1)1295 


SN74LS0 ON 


A J Ul 0 0 


1 82 () - 1 2 1 6 


3 


3 


IC DCDR TTL LS 3 Tfl-B ■■ L I NE 3- INP 


0 1 295 


SN74LS138N 


A 1 LI 1 0 1 


ll:!.-,'0~ 1216 


3 




IP ■^\pY^^J i ti i i Tn .q. i vur ^ . vkid 
J 1.. l/',l.'K 1 II.. .1 1 U i:t 1 llvi". ,s iivr 


0129':,> 


b IN / -1 Lb 1 .nr? N 


A i U 1 0 

■ ''S 


1 8? 0 ~ 1 2 1 6 


, 




TP IM'IMi TT'I 1 c; "r TH -O-.l TMT' 1..TMP 

J. L. u\.,i?,-< 1 11. L ; 1 Ji III Q l-.l.tNl:. o llNr 




;;ir' / 41. b I J)!;tiN 


A 1 IJ 1 U i5 




3 




J- r 1 111— I - ..) iJ i\ rtK r Lj ..J I,, .v/i.v i:l i k t i.t 


01' 9'^' 


i.ny / -'tI 1 l.l 7 H IN 


A1U104 


1820-1^311 


3 


2 


IC CNTP TTL LS BIN SYNCHRO PClS -EDGE- TR XC 


0129S 


SN74I S161AN 


AlUl 05 


1B20-1430 


3 




IC CNIR TTL I..B BIN SYNCHI^C) POB-EDCE ■ I IG 


:)1295 


SN7 4LS161AN 


A i U 1 06 


Kir. 0 1 t_81 






J. I/Lri/1\ 1 1 1... L„l» 1 l.l *T L„ J rti, iM.'rIl... J P*l 


0 ) ,:9 j 


c: M '7 d 1 C 1 T < J w 


A 1 Li 1 U / 


1 Ii2 0 — 1 ?B? 






P. Ij T r 111... 1-. w) J l\ -I.' 1"! A r LJ i.> 1.-1/ Iv r.. 1 .1. Ij 


n .| -XDC- 


QU'7 ai Q 1 n iJ AM 


A -1 111 n n 


1 Q2 (1 — 1 0S2 


^. 




TP TIJ FPl rPI -Tn.-TTI ntlAH '^.-TMP 
1 A 1 . 1 l\ C-t.. 1... 1., l.j l._ 1 I 1 1 1 L- WU iZ J. INI 


0 4713 


Ml' 1 0 1 251 




1820--1 os;5 


5 




IC XLIR ECL ECL-TO-TIL QUAD 2-XNP 


0 47 1 3 


fiCl 0125L 




18;."' 0-1 052 






IC XLTR ECL E:CL-TO-TTL QUAD 2-XNP 


0 4713 


MCI 01251 


A 1 U 1 1 I 




9 




IV l_. 1 WlIK 1\ 1\ 1.. ..> .MI 1. r / U . il 1 I M n A / 


vl 1 1 .... 1 


' ^ ''A4 ^ t 


A 1 U 1 1 ? 


1 M A,' *t ij U / 






if 1 I ii iN i 1- li' ' n ft ( I (.1^ li V f 1 1 h( 




I til ■ i .J li u / 




.1 l.t 1 If 11 C- / o 


9 




ivt:. 1 wi'K i\ K t..;:) i i) ,:■ 1. 1 -4 / II i li i ji in A / 


VI 1 1 




AlUtlS 


1320-1199 


1 


1 


IC INV TTL LS HrX 1 -INP 


0 1295 


SN74LS04N 


A 1111 16 


1820-1210 


7 


1 


IC GATE TIL LS ANDOR INW DUAL 2-INP 


0 1 295 


f'.N74LS51 N 


A 1 Ul 1 7 


18.. 0 1423 






TP Mil TIT 1 c; wriMiiCT til D(."rnTr" niiAi 
1 nv 1 II... Lb niiivi.)':) 1 r.ii... ki: i k j i.... ulihi.. 


0 1 29.< 


S N 7 4 1 , S 1 2 N 


A 1 1.1 1 1 8 


1 82 0 -21 02 


8 




IC 1 CH ITL I S D-IYPE OCTL 


01 295 


SN74I.S373N 


A1U119 


ia;.'0-2i 02 


B 




IC LGH TTI LS D-TYPE OCTL 


01295 


SN74I S373N 




"I \>i ''^ A 1 O ('J 7 
,\ ot.' U 1 y / / 






11^ r. c T ■■( 1 1 Q i\ ..Tvpc o n c; r; TM' i-....ti3TP odi _rhi 
1 1., F 1 11 L. I..;:) 1? 1 T 1 r. r Ub 1::. Ui.jI." 1 K .). Lj 1 K L . L IN 




C Kl *7 1 C "I '7 A Kl 




1 82 tl -2 0 7''j 


A 




T i'^ M T ct T TT 1 
n J. bL 1 1 L Lb 




bN / ■'1 L.b2*ti.jN 


Aim^'' 


18i-0"*l024 


" 




TP TiDliD TTI 1 c; 1 T hlLT HDUP PPTT 
1. Lf l.'dvK 1 1 L. lb l.-lNt:. J/KVK l,j|„. 1 1,. 


01 ,-.9.j 


b IV / -H L b t. *t IN 


A1U123 


1820 ■-1195 


7 


1 


IC EE TTL LS B-TYPE P OS- EBGE-TR IG COM 


0129S 


SN74I..S175N 


A1U124 


1B20~02(S9 


4 




IC GATE TTL NANB IJUAB 2-INP 


01295 


SN7403N 


Al M1^/ 


1 d (... U 1 1 M *( 


^ 




TP r"ATC.' TTI 1 G kinrj nllAT^ o... rMr> 
1 Li laM It- 11 L. L.b nuK yi.im' ii j. ini 




o *i'7 1 c n "J M 
OiN / *H..b 1! i. In 




1 w (1 — n 7 fi n 
J. wi.. ij u / n u 






TP TiD U13 TM 1 T Wr IMS UP HUfin 




i/bl:J o I IN 


A1 1 1 r)7 


1 tt c U — 1 1.; u W 






TP nATi::' tti i c r\o niiAi\ T tmci 


0 1 295 


C Kr'V 1 C "7 111 

bN /4L b.Si. N 


A nil ."'8 


IBl 0 ■0298 


S 




NETWORK RES 10 BIP240,0 OLiH X 9 


1) 1 1 2 1 


21 l)A2 11 


A1U129 


1820-1173 


1 




IC XLTR ECL TTL-TCl-ECL QUAD 2-INP 


0 4713 


MCi (11241 




1 Q 1 ci — 11 n'y 'X 
I n A u 11 c / o 






Mf- ii,i("ii:)i/ .. ij r.' c; i n '^'■lOiivn n timm v o 
) V r: 1 W 1 1 1 ^ r\ K 1 - t I U . > 1 V / 11 . 11 1 J i i n A / 


.1 ) 1 2 1 


21 0A4 ^ i 




1 ' T Q 0 C 4 






i.M ll.f l\ r 1 i L. *t It L. V 1 rJ 1 1^ 1 t 1/ 1 1 ■ ) 1 1' iS 




1 . II U 0 O..1 4 


Al xu''"^-' 


[ p (1 Q — j) iy'^tJ^ 


7 




Fi 1 " 1/ JV T ... r R A fl f" f"l M T" T*i I P T'l 1 P 1 t T'l D 

■ l\ i t 1. 1.. -'t U L 1 .UN 1 U ' r JJ M il. .UK 


'■■n4B() 




A-|XU2b 


1200-0639 


8 




SQCKt I-IC 20-CnNr DIP DIP-SLDR 


2R4R0 


120 0-0639 


A1XU28 


1200-0796 


8 


2 


r>nci<r i-ic b-cont dip dip slbr 


2B4B0 


120 0-0796 


A i XU<i9 


1 tl u u U / Yo 






CM"\ f 1/ r'" 1' T I'' n f I'k M T' n T D r. T n i f\p 


2 B 4 8 0 


1 2 0 0 -0796 




■I D (1 ii — n ^ *7 




4 


1 I""! r - 1/ r" T '1 f"' i / l"'llilT 1\ It) T\ T t> 1 Tl ID 

I. Ill Kl 1 1 L 1 o LUN 1 D.l.r U i.r bL.DK 


fV'i:148 0 


120 0-0607 


A IXU'^O 


■1 '3 n [1 .... nun '"/ 






cnpi/CT..-TP ^t PiTMT' Ti T n nrn, ("i nra 

bULitV r:. \ 1 Li 1 O Lit.) IN 1 U i. 1 1/ .1. 1 ;:tl.. IfK 




1 2 11 0 0 6 U / 


Aixusrs 


120 0-0639 


8 




BOCKET-IC 20-CDNT BIP DIP SLBR 


;:o48o 


120 0-0639 


A 1X07 0 


1200-0612 


7 


a 


SOCKET-IC 22-CONT BIP DIP-SLDR. 


2H40fi 


1200-0512 


A1XU71 


1200-0612 


7 




BOCKET-IC 22-CONT DIP DIP -ELBR 


2848 0 


1200-0612 


A1XU72 


1200-0612 


7 




SOCKET-IC 22-CONT DIP DIP-SLDR 


284t;iO 


120 0 -061 2 


A1XU73 


1200-0612 


7 




nOCKFT -IC 22-rONT BIP DIP-SLDR 


2B4B0 


1200-0612 


A) XU90 


1200-0612 


7 




SOCKfl -IC 22-CilNT DIP DIP-SI DR 


2848 H 


120 0 0612 


A1XU91 


1200-0612 


7 




sricKLT-[G 22 i:nNr dip dip sldr 


2B480 


120 0-0612 


A 1 XU92 


120 0-0612 


7 




SOCKEI-IC 22-CONI' DIP DIP-SLDR 


28480 


120 0-0612 


A1XU93 


1200-0612 


7 




SOCKET-IC 22-CONT DIP DIP SLBR 


28480 


1200-0612 


A1XU112 


1200-0654 


7 




SOCKET-IC 40-CONI DIP DIP-SIBR 


2848 0 


120 0-0654 


AlXUl 17 


1200-0607 


0 




EOCKET-IC 16-rnNT DIP BIPSLOR 


28480 


120 0-0607 


A1XU12& 


1200-0607 


0 




SOCKET-IC 16-CONr DIP BIP-SLDR 


28480 


120 0-0607 


A1XU127 


1200-063B 


7 


1 


EDCKET-IC 14-CONT BIP BIP ELBR 




1 200-063B 



See introduction to tiiis section for ordering information 



SAC 6-8 



Model 6U62IA - Replaceable Parts 



Table 6-2. Replaceable Parts List (Cont'd) 



Reference 
Designation 



HP Part 
Number 



Qty 



Description 



Mfr 
Code 



Mfr Part Number 



MPS 
MPS 
MfM 
MPS 

Ul 



2200-0147 


4 




2;!00-0151 


0 


2 


64620-67601 


7 


1 


6'>620-6760a 


8 


1 


7121-2158 


S 


1 


64620-61602 


6 


1 



U3 
U4 



64620-61605 
64620-61620 



SCRFU-MACH 4-40 ,5-IN LG PAN-HD-P07T 
SCREW MflCH 4 -40 .75-IN-l.G PflN-HD-PClZI 
HOOD-CONNECTOR ASiSEMBLY (TOP) 
HOOD -CONNECTOR ASSETMBLY (BOTTOM) 
LABLE-CLOCK PROBE 

CABLE-CLOCK ASSEMBLY 
NOTE 

IF THE CABLE IS DAMARED, THE ENTIRE Ul 
CABLE-CLOCK ASSY MUST BE REPLACED. 
CABLE-DATA ASSEMBLY 

«« DEPENDS ON THE NUMBER OF ACQUISITION 
BOARDS BEIN(3 USED IN THE SYSTEM. SEE 
THE ACQUISITION MANUALS. 

CABLE-SYNCHRONOUS EXPANSION BUS (SEB) 
CABLE - INIERMOBULE BUS (1MB) 



00000 
00000 
284B0 
28480 
28480 

2848 0 



ORDER BY DESCRIPTION 
ORDER BY DESCRIPTION 
64620 67601 
64620-67602 
7121-2158 

6462 0-61602 



2O480 
28480 



646P0-61605 
64fc;>0-61620 



See introduction to this section for ordering information 



SAC 6-9 



Model 6U62IA - Replaceable Parts 



Table 6-3. List of Manufacturers' Codes 



Mtr 
No. 




Address 


Zip 
Code 


so 167 


fUJITSU LTD 


TOKYO 


J P 




i:i4013 


HITACHI 


TOKYO 


JP 




00 000 


ANY SATISFACTORY SUPPLIER 








0 1 1 2 1 


flLLLN-BRADLFY CD 


MILWAUKEE 


UI 


53204 


01;.' 9 5 


TEXAS INSTR INC SFMICOND CMPNT DIU 


DALLAS 


TX 


75222 


021 1 1 


SPECTROL ELECTRONICS CORP 


CITY OF IND 


CA 


91745 


04713 


HOTDROLA SEHICONBUCTDR PRODUCTS 


PHOENIX 


AZ 


85 0 nu 


0 7263 


FAIRCHILD SEMICONBOOTOR BIV 


MOUNTAIN VIEW 


CA 


94042 


1 1236 


CTS OF BERNE INC 


BERNE 


IN 


4671 1 


1V701 


MEPCD/ELECTRA CORP 


MINERAL WELLS 


TX 


76067 


20932 


EMCON DIV ITU 


SAN DIEGO 


CA 


921 29 


2 '5546 


CORNING GLASS UORKS (BRADFORD) 


ERADFORB 


PA 


167 0 1 


25403 


AMPEREX ELEK CORP SEMICON 4 MC DIW 


SLATERSUILLE 


RI 


02B76 


27014 


NATIONAL SEMICONDUCTOR CORP 


SANTA CLARA 


CA 


95051 


27 1 67 


CORNING GLASS WORKS (WILMINGTON) 


Mil MINGTON 


NC 


284 01 


28480 


HEWLETT-PACKARD CO CORPORATE HQ 


PALO ALIO 


CA 


94304 


31..585 


RCA CORP SOLID STATE DIU 


SimERUILLL 


NT 




34335 


ADVANCED MTCRO DEVICES INC 


SUNNYVALE 


CA 


94 0RA 


52763 


SIETTNER -TRUSH INC 


CAZENOVIA 


NY 


13 0:'.;-;, 


56289 


SPRAGUE ELECTRIC CO 


NORTH ADAMS 


MA 


01247 


72136 


ELECTRO MOTIVE CORP 


FLORENCE 


SC 


06226 


75042 


TRU INC PHILADELPHIA BIU 


PHILADELPHIA 


PA 


1910(1 



Sec introduction to this section for ordering information 



SAC 6-10 



Model 6k621A - Manual Backdating 



SECTION VII 



MANUAL BACKDATING 



7-1. INTRODUCTION. 



7-2. This section contains information required to backdate or update this manual 
for a specific repair number prefix. 



7-U. This manual applies directly to the instrviment having the repair number prefix 
shown on the manual title page. If the repair prefix is not the saime as the one on 
the title page, find your repair number prefix in Table 7-1 and make the changes to 
the manual that are listed for that repair nximber prefix. When making chauiges list- 
ed in table 7-1 » make the change with the highest number first. Example: if 
backdating changes 1,2 and 3 are required for your repair number, do change 3 first, 
then change 2, and finally chauige 1. 

7-5- If "the repair number of your instrument is not listed either on the title page 
or in table 7-1, refer to an enclosed MANUAL CHANGES sheet for updating information. 
Also, if a MANUAL CHANGES sheet is supplied, make all indicated ERRATA corrections. 



CHANGE 1 
Section VI, 

Page SAC 6-k, Table 6-2. Replaceable Parts List, 

Change Al part number from 6I462I-66502 to 6U62I-66501. Check digit from 6 to 



Page SAC 6-5, Table 6-2. Replaceable Parts List, 

Change A1R2, R3, R9, HIO, R29-31, R36-I4I, Rl+3-^7, R51, R53 part numbers from 
0698-6612 to 0757-0283 (20 places). Check digit from 1 to 6 (20 places). 
Tolerance from 0.1% to 1% (20 places). Mfr Code from 28U80 to 2k^U6. Mfr 
Part Number from O698-6612 to CU-1/8-TO-2001-F. 

Delete last line -AITPI8, O365-O535, 0, Terminal Test Point PCB, 00000, Order 
by Description. 

Change A1TP2 QTY from 12 to 11. 



7-3. MANUAL CHANGES. 



Table 7-1. Manual Changes 



PREFIX 
2lUitA 
22U6A 



MAKE CHANGES 
1 and 2 
2 



SAC 7-1 



Model 6k621A - Manual Backdating 

CHANGE 2 

Section VI, 

Page SAC 6-U, Table 6-2. Replaceable Parts List, 

Change Al to read: Al, 6U621-66502, 6, 1, lOMHZ STATE ANALYSIS CONTROL BOARD, 
28U80, 6U62I-66502. 

Delete A1C68, Ol60-2055, 9, -, CAPACITOR-FXD .OIUF +80-20% lOOVDC CER, 281*80, 
0160-2055. 

Change AlCl QTY from 50 to U9. 

Page SAC 6-5, Table 6-2. Replaceable Parts List, 

Delete AITPI9, O36O-O535, 0, TERMINAL TEST POINT PCB, 00000, ORDER BY 
DESCRIPTION. 

Change A1TP2 QTY from 13 to 12. 
Page SAC 6-6, Table 6-2. Replaceable Parts List, 

Delete AlUlU, 1820-1201, 6, 1, IC GATE TTL AND QUAD 2-INP, 01295, 1820-1201. 
Section VIII, 

Delete TPI9 from the eight component locators facing the schematics. 
Service Sheet 5, 
Remove VlkC. 

Disconnect Ul pin 17 from UlkC pins 9 and 10. 

Disconnect UlUC pin 8 from J2 pin U3. Show pin U3 as NC. 

Disconnect J2 pins k2 and kk fi-om ground. Show them as NC. 
Service Sheet 7» 

Show U98A pins 2, 3» and U as no connection (NC). 

Disconnect U73 pin 9 from U73 pin 17 (+5V). 

Connect U73 pin 9 to U73 pin 11 (LSFLGB). 
Service Sheet 8, 

Delete C68 from the list of +5 Volt bypass caps (.OIUF). 

Delete TPI9, SA START/STOP, test point from PI pin 69. 



SAC 7-2 



Model 6U62IA - Service 



SECTION VIII 
SERVICE 

8-1. INTRODUCTION. 

8-2. This section contains information for troubleshooting and repairing the Model 
6U62IA State Analysis Control Board. 

8-3- The block diagram, schematic, component location figure, and other service in- 
formation are provided on fold-out service sheets to help you in servicing the Model 
6U62IA. 

8-U. Because the State Analysis Control is software dependent, it becomes very dif- 
ficult to discuss the Theory of Operation at the bit level. Therefore, the follow- 
ing discussion is at the concept level of various functions. 

8-5. The following five areas of the State Analyzer are discussed in detail: 1. 
Clock Term Generator, 2. Strobe Generator, 3. Sequencer, U. Analysis Controller, and 
5. State/Time Counter. 

8-6. The Clock Terra Generator, Analysis Controller, and the State /Time Counter are 
custom integrated circuits manufactured by Hewlett - Packard. How the ICs work is 
presented to help you understand how the State Analyzer works , rather than a "black 
box" approach. 

8-7. The Strobe Generator is discussed because it must be repaired using convention- 
al methods instead of Signature Analysis. 

8-8. The Sequencer is discussed because it is not apparent from the schematics how 
it works , due to feedback loops . 

8-9. STATE ANALYZER SUBSYSTEM BLOCK DIAGRAM. 

8-10. The State Analysis Subsystem Block Diagrajn, Figure 8-1, is designed to give an 
overview of the State Analysis System. The block diagram is divided into two sec- 
tions, the Control Board and the Data Acquisition Board. The Data Acquisition Board 
is also divided into two sections, the Overview block, which is only on the 20 chan- 
nel board, and the rest of the blocks which are on both the 20 chajinel and UO chaoi- 
nel boards. 

8-11. The shaded blocks on the Control Board are all parts of the Analysis 
Controller (Ul) a hybrid chip. Other hybrids are the Clock Terra Generator (U25) , 
the Trace State/Time Counter (U112) on the Control Board, and the Counter (U23) in 
the Overview State/Time Counter on the 20 channel board. 

8-12. The Block Diagram is also divided into six sections shown by the red lines. 
These six secitons represent time. There are six time periods; 1. Clock 
Qualification, 2. Input Data Sampled, 3- Decode Trigger Terms and Bucket Generation, 
k. Pipeline Registers, 5- Data Storage/Count Enable Determination, and 6. Store Data 
and Output. 



SAC 8-1 



Model 6U62IA - Service 



8-13. DESCRIPTION. 
8-14. Time Period 1. 

8-15. Clock Qualification consists of all the circuitry for setting up the threshold 
levels for the clock. The Data Threshold block sets up the threshold levels for the 
20 cheuinels of data. In addition to the clock threshold circuitry, the Control 
Board portion of this section contains the interfaces to the general purpose 
preprocessor, the interface to the Inter Module Bus (1MB), and the Clock Term 
Generator. The Clock Term Generator is loaded by the CPU when the clock is 
specified in the format specification. When that specification is satisfied the 
Clock Term Generator sends out a 15ns pulse to the Strobe Generator which initiates 
a timing sequence in the rest of the state analyzer. 

8-16. Time Period 2. 

8-17. The key to the State Analysis System is the Strobe Generator. It provides all 
the timing signals for the system to insure the proper sequence of events. 

8-18. The Strobe Generator, in Time Period 2, is where the input data is latched 
into the acquisition cards. The signals from the Strobe Generator, P/NBSRS 
(Positive/Negative Bus State Recognition Strobe), are sent across the SEB 
(Synchronous Expansion Bus) to strobe in the data on the acquisition cards. The 
PBSRS signal is also used in the Overview State /Time Counter (only on the 20 channel 
acquisition board) to increment the overview counter every time a valid clock term 
is encountered. 

8-19. Time Period 3. 

8-20. The Resource Pattern, Sequence Pattern and Event Generation is where the State 
Analyzer's resources are allocated and the Sequencer patterns determined. The 
Acquisition Board detects specified combinations of trigger, storage, and count in- 
formation, and sends that information on LBRPO-7 (Low Bus Resource Pattern) over the 
SEB to the Resource Allocation portion of the Analysis Controller. This section of 
the Analysis Controller determines, from the data on the LBRO-7 lines, how to allo- 
cate the set number of resources available to the state analyzer aunong the trigger, 
storage, and count specifications. 

8-21. The Resource Pattern, Sequence Pattern and Event Generation block also deter- 
mines when the Data Acquisition boards have found the sequence state(s) requested by 
the user. If no sequence events were specified, then the Low Bus Sequence Pattern 
0-3 (LBSP 0-3) lines would always be high. 

8-22. Time Period 4. 

8-23. Time Period k. Pipeline Registers, is where the State Analyzer latches all the 
data so that the front end can bring in new data, and the rest of the analyzer can 
process the current data. The latching is done by the Positive Pipeline Strobe 
(PPLS) which occurs 95ns after the Strobe Generator is started. This allows the 
state boards to work on 2 different sets of input data at the same time. The timing 
for PPLS is critical. 



SAC 8-2 



Model 6U62IA - Service 



8-24. Time Period 5. 

8-25. The Data Storage/Count Enable Determination continues the resource allocation 
and gating that was started in time period k. All this is done on the control board 
in the Analysis Controller. These control signals are output by the Analysis 
Controller gating functions: 

HOVCQ - (High Overview Count Qualify) 

HOVCQ, when high, enables the overview counter in the 20 channel Data 
Acquisition Board. It is derived from the internal Overview Count Signal or 
LSOCE (Low Sequence Overview Count Enable) from the Sequencer. 

HCQ - (High Covint Qualify) 

When high, HCQ enables the Trace State/Timing Counter allowing it to increment. 
It is derived by the internal Trace Count signal or the LSCE (Low Sequence 
Counter Enable) signal from the Sequencer. 

LSFLG - (Low Store Flag) 

This active low signal indicates to the Trace Count/Status Memory that storage 
is enabled. LSFLG is enabled by the internal storage signal, or LSE (Low 
Storage Enable) from the 1MB (Inter Module Bus), if active, or either of the 
signals from the Sequencer, LSSE/Q (Low Sequence Store Enable/Qualify). 

NTRIG - (Negative Trigger) 

This signal goes from a high to a low each time a user specified trigger event 
occurs. It is used to latch signals into the trace point latch internal to the 
Analysis Controller, and into the BNC Port latch. It is derived from the in- 
ternal Trigger Signal, or LSTE/HSRS (Low Sequence Trigger Enable /High State 
Recognition Strobe) signals from the Sequencer, or either LTE/HTR (Low Trigger 
Enable /High Trigger) from the 1MB. 

LTE - (Low Trigger Enable) 

This active low bidirectional signal is the 1MB signal that is sent to the 
other modules when a trigger is recognized by the control board. It is derived 
from the same signals NTRIG output is derived from. 

8-26. The Trace State/Time Counter in Time Period 5 is used whenever that function 
is turned on in the trace specification. It is suiother of the hybrid chips designed 
for this instrument. Its function is to covint the number of states between two 
states or periods of time between two states. When LSTATE (Low State) is low the 
counter counts the number of states between two stored states. The counter is in- 
cremented by PINC (Positive Increment) which is developed from HWQ (High Write 
Qualify) and HWRT (High Write). HWQ is generated by the Analysis Controller, and is 
used to disable the coxinter when the output of the Counter is being stored in the 
Trace Coxint/Status Memory. HWRT is developed in the Strobe Generator each time a 
qualified clock is detected. 

8-27. When LSTATE is high the Counter counts the time between two states. The L25 
MHz (Low 25 Megahertz) signal is used to clock the Counter in this mode. 



SAC 8-3 



Model 6U62IA - Service 



8-28. Time Period 6. 

8-29. Time Period 6 is the Store Data and Output block. This is the last stage 
before the captured data and count information is sent to CPU for display. There 
are three separate operations that occur in this block. 

8-30. The first is on the 6U623A (the 20 channel acquisition board) where the 
Overview events are stored in the Overview memory. The CPU unloads Overview Memory 
using LRDL (Low Read Data Latch), for the Overview Event Data Latch, and LRDOV (Low 
Read Overview), for the Overview Memory Address Counter Latch. 

8-31. The second operation that occurs in this block is on both the 6U622A {kO chan- 
nel acquisition board) and the 6k623A (20 channel acquisition board). The 20 chaai- 
nels of data on each half of the board are latched into the Trace Pod Data Memory by 
HBQWRT (High Bus Qualified Write). HBQWRT synchronizes the data storage with the 
Trace Counter /Status Memory on the control board. The data is read from the Trace 
Pod Data Latch onto the CPU Data Bus by LRDL (Low Read Data Latch) which is 
developed on the acquisition board from CPU control signals. 

8-32. The third operation takes place on the control board. The Trace Coimt/Status 
Memory section of the Control Board stores the 8 outputs of the Sequence State 
Latch/Counter (TSSO-7), the 20 outputs of the Trace State/Time Counter (CNTO-I9) and 
three control signals HOTFB (High Overview Trigger Flag Buffered), HCQB (High Count 
Qualify Buffered), and LSFLGB (Low Store Flag Buffered). The CPU needs these con- 
trol signals to interpret the data from the state system. 

8-33 • The final section is the five registers that hold the information to be read 
onto the CPU Data Bus. These five registers are enabled by control signals 
developed in the CPU Read Decoder on the Control Board from the CPU Address Bus sig- 
nals. The five signals are: 

LRSQRG - (Low Read Sequence Register) 

This active low signal allows the output of the Sequence State Latch/Counters 
(TSS 0-7) to be read onto the CPU Data Bus. 

LRTDR - (Low Read Trace Data Register) 

When low, LRTDR enables the Trace Point Register allowing the value of the 
Trace Count/Status Memory to be read by the CPU. 

LRTPRG - (Low Read Trace Point Register) 

This active low signal allows the Trace Point address to be read over the CPU 
Data Bus. The Trace Point address was latched by LTRCP when the trace point 
was found. 

LRSTS - (Low Read Status) 

When low, LRSTS enables the Analysis Status Buffer to allow eight different 
signals to be read by the CPU. 



SAC 8-U 



Model 6I462IA - Service 




Figure 8-1. 

State Analyzer Subsystem Block Diagram 

SAC 8-5 



Model 6U62IA - Service 



8-34. CONTROL BOARD BLOCK DIAGRAM. 

8-35. The Model 6U621A State Analysis Control Board consists of the following 
nine basic functional groups: 

* Clock Probe Interface 

* Preprocessor Interface Bus 

* Strobe Generator 

* Sequencer 

* Analysis Controller 

* BNC Control 

* Trace State /Time Counter 

* Trace Count/Status Memory 

* Mainframe Interface 

8-36. CONTROL BOARD BLOCK DIAGRAM THEORY. 

8-37. CLOCK PROBE INTERFACE. 

* The Clock Probe Interface consists of the Clock Term Generator chip, U25, and 
the D/A Converters, U5U and U55. 

* The Clock Term Generator allows eight different clocks to be input to the 
State Analyzer. 

* The eight clocks may be used in various qualification patterns. 

* The Clock Term Generator outputs a master clock to the Strobe Generator. 

* The D/A Converters provide threshold levels for the Clock Probe. The threshold 
levels are set by the operator through the keyboard. 

8-38. PREPROCESSOR INTERFACE BUS. 

* The Preprocessor Interface Bus provides the communications path from the 
Mainfreune to the General Purpose Probes and the General Purpose Preprocessor. 

* The clock for the State Analyzer is provided by the Preprocessor when it is 
being used instead of the Clock Probe. 

8-39. STROBE GENERATOR. 

* The Strobe Generator converts the output of the Clock Term Generator, U25, 
into the various strobes needed throughout the State Analyzer (including 
the Acquisition Boards). 

* The amounts of delay for each strobe and the pulse widths are adjustable. 

* The Strobe Generator can also be activated by the Mainfraune Interface for 
Performance Verification using signals PPVSTB or PBSRQ. 

8-40. SEQUENCER. 

* The Sequencer is a group of counters, memories, and gates that allow the 
State Analyzer to find events in various sequences and occurrences. 



SAC 8-6 



Model 6U62IA - Service 



* The Sequencer is programmed by the Mainframe for each Trace to be performed. 
Variables are entered from the keyboard. 

8-41. ANALYSIS CONTROLLER. 

* The Analysis Controller, Ul, is the heart of the State Analyzer. 

* The Analysis Controller recognizes event.*? occurring on the Acquisition 
Boards and in general provides the handshaking between the Acquisition 
Boards auid the Control Board. 

* The Analysis controller is programmed by the Mainfreune CPU. 

* The Analysis Controller controls the Intermodule Bus (1MB). 
8-42. BNC CONTROL. 

* The BNC Control circuit drives signals of correct polarity to the Mainframe's 
Rearpanel. 

* The polarity is selected by software. 
8-43. TRACE STATE/TIME COUNTER. 

* The Trace State/Time Counter, U112, is a 20 bit floating point gray code 
coxinter. 

* The State/Time Counter accumulates the time between two stored states, or the 
number of states between two stored states . 

* The State/Time Counter is referenced to a 25 MHz crystal when measuring 
time, and to the qualified count states as input in the trace specification 
when counting states. 

* The 25 MHz crystal is located in the Mainfraune. 
8-44. TRACE COUNT/STATUS MEMORY. 

* The Trace Count/Status Memory stores the values output from the Trace 
State/Time Coimter for each measurement. 

* The Trace Count/Status Memory can store values for each of the 256 locations 
in the Trace Pod Data Memory on the Acquisition Boards. 

* The values are read from the memories over the Mainframe's Data Bus and for- 
matted by the CPU for display on the CRT. 

* The Trace Count/Status Memory stores sequence states and flags associated 
with each counter value. 

8-45. MAINFRAME INTERFACE. 

* The Mainframe Interface consists of various latches and buffers (wire ORed) 
for interfacing the State Analyzer's circuits to the Mainframe. 



SAC 8-7 



Model 6k621A - Service 



* Through the use of read and write decoders , the Mainframe can select various 
groups of circuitry on the Control Board and write to (program) or read 
from (verify, interrogate) them over the Mainframe's Data Bus. 



SAC 8-8 



Model 6k621A - Service 



/ 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



Q 
Q 
< 



o 
cc 
I- 
z 
o 
o 



o 
o 



CM 

X 

z 



PREPROCESSOR 
INTERFACE 
BUS 

TEST 11 



1 



Q 
-1 
O 
Z 
(A 
lU 

cr 
z 



w 

HI 

m 
O 
cc 
h- 



SEB 

TO/FROM ACQUISITION BOARDS 



CLOCK 
PROBE 
INTERFACE 



TEST 3, 10 

/\ /\ A 



HMCLK 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



7\ 



PSTIM/PHALT 



UJ 

O 

z 

UJUJ 
31- 

o< 

UJl- 
(0(0 



UJ<0 
(00. U 



zco 

UJCC 

>> 
OO 
mm 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



(OK- 2 

iu< 



SEQUENCER 
TEST 4 



CONTROL 



ADDRESS 



STROBES 



CONTROL 
LINES ^ 



\ 



OO 
tro 



Cm 



ooo 
mm 
zzz 



/ 



ANALYSIS 
CONTROLLER 

TES T 2 



A 

V 



HWRT, HTIMS 



I 



TEST 8 



PDC 

LME 

LTE 

LSE 

HTR 



BNC 
CONTROL 

.TEST 12 

/\ /\ /\ 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7\ 



20 



2" 



> 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 



DATA 



Q 
_i 



UJ 








< 


(0 


cc 


1- 


u. 


cc 


z 


o 


< 


Q. 


s 





N 

z 

m 

CM 



MAINFRAME INTERFACE TEST 1 



Figure 8-2. 

State Analysis Control Board Block Diagram 

SAC 8-9 



Model 6U62IA - Service 



8-46. DETAILED CIRCUIT THEORY. 

8-47. CLOCK TERM GENERATOR. 

8-1+8. The Clock Term Generator, U25, is a custom designed clock decoder. It con- 
verts eight clock channel inputs into a single master clock. 

8-U9. Each clock input can be programmed by loading two internal shift registers. 
The shift register outputs set up the channel to be edge sensitive or level sensi- 
tive, but not both at once. The level sensitive inputs are called clock qualifiers 
and are wire ANDed internally. Any combination of inputs can be made edge sensi- 
tive, and any input can trigger on a positive edge, a negative edge, or both edges. 

8-50. The eight clock channel inputs are differential at approximately ECL levels, 
and the master clock output (HMCLK) is ECL. The two shift registers smd their clock 
are TTL levels. 

8-51. Clock Term Generator Timing. 

8-52. Inputs used as clock qualifiers have a set-up time of 20 nS and hold time of 0 
nS. Inputs used as clocks must have a pulse width of 20 nS minimum. Due to system 
restrictions, the master clock rate is 10 MHz maximum. Propagation delay is ap- 
proximately 8 nS from clock input to master clock output. 

8-53. Clock Term Generator Block Diagram. 

8-5U. Prior to execution of a trace, the Edge Detect Register and Level Select 
Register are loaded from lines DBO and DBl using Positive Write Clock (PWCLK) , Two 
bits per clock channel control the channel's Level Select Gate. The channel can be 
made "don't care" by programming both bits high. The outputs of all eight Level 
Select Gates are ANDed, so that all qualifiers must be true before the data input to 
the Edge Detect filp-flops go true. 

8-55- Two more programmable bits per clock channel are needed to control which clock 
edge, if any, will produce a High Master Clock (HMCLK). A high output by the Edge 
Detect Register to any flip-flop will prevent that detector from toggling. All 
filp-flop outputs are ORed to produce HMCLK. Therefore, all possible combinations 
of chamnels and edges are allowed. The only restriction is that HMCLK pulses must 
be at least 100 nS apart. 

8-56. HMCLK drives Pulse Width Output (PWO) which is connected externally to Pulse 
Width Input (PWI). After a delay, PWI resets the edge detector responsible for the 
master clock. This results in a pulse width of 1^ nS maximum for HMCLK. 

8-57' The Edge Detect Shift Register and Level Detect Shift Register can be made to 
overflow during performance verification. These registers output High Clock Data 0 
and 1 (HCDO-1). 



SAC 8-10 



Model 6U62IA - Service 



FROM 
CLOCK PROBE 
OR 

PREPROCESSOR 



CLOCK TERM GENERATOR 

1 OF 8 CLOCK INPUTS 
HCLKO 




25' 
11 
12 . 
31 

32 < 
9< 

10< 

33 4 

34 . 



FROM 
LEVEL SELECT < 
REGISTER 



LEVEL SELECTOR 




+5V 



3.25V 



FROM 
7 OTHER 
LEVEL 
SELECTORS 




FROM EDGE SELECT 
REGISTER 



RESET 
D Q 



> POSITIVE 
EDGE 
DETECTOR 




FROM EDGE SELECT 
REGISTER 



RESET 
D 0 



> NEGATIVE 
EDGE 
DETECTOR 



DELAY 



PWI(ECL) 



35 



PWO(ECL) 



I 

/ 



WIRED TOGETHER 
EXTERNALLY 



12NS TYPICAL 



HMCLK(ECL) 



^ 29 



TO D INPUTS, 14 OTHER 
EDGE DETECTORS 



FROM 
14 OTHER 
EDGE 
DETECTORS 



TO RESET INPUTS,14 OTHER 
EDGE DETECTORS 



FROM I DBO(TTL) 

CPU DATA 13-^ 

BUFFER 



FROM > PWCLK(TTL) 

WRITE DECODER N 



16 BIT EDGE SELECT REGISTER 



HCDO(TTL) 



TO 
STROBE 
GENERATOR 



FROM 
CPU DATA 15^ 
BUFFER 



DBI(TTL) 



16 BIT LEVEL SELECT REGISTER 



HCDI(TTL) 



TO 

)> ANALYSIS STATUS 
BUFFER 



> 26, 



Figure 8-3. 

Clock Term Generator Block Diagram 

SAC 8-11 



Model 6U62IA - Service 



8-58. STROBE GENERATOR. 



8-59 • The Strobe Generator develops seven major strobes from HMCLK or PPVSTB and 
PBSTBRQ (see Figure 8-U) ; 

1. HSRS 2.HTIMS 3- HOVS U. HPLS 5- HWRT 6. LMV 7- LDV 

HMCLK is used to drive the Strobe Generator in the Analyzer's rxm mode. PPVSTB and 
PBSTBRQ are used in the Performance Verification mode. 



8-60. Strobe Uses. 



8-61. HSRS is used to clock the 1MB State Recognition Register in the Analysis 
Control Chip. P/NBSRS clocks data into the State Recognition Latch/Counters on the 
Data Acquisition Boards. 

8-62. HTIMS is used to trainsfer information to the outputs of the Trace State/Time 
Counter . 

8-63. HOVS is used to develop LBOVEN and PBOVRST. LBOVEN and PBOVRST are used on 
the 20 Channel Data Acquisition Board only. LBOVEN allows the Overview section to 
look for its trigger events. PBOVRST is used to reset the Overview State/Time 
Counter . 

8-6U. HPLS is used to latch infomation into the Pipeline Registers on the Control 
Board and the Data Acquisition Boards. 

8-65. HWRT is used to time write commands to Trace and Overview Memories. These 
write commands store data in the Memories. 

8-66. LMV develops P/NMACRS. P/NMACRS is used to latch information from the Trace 
Count/Status Memory Address Coxinter into the Trace Memory Address Counter Read 
Register. 

8-67. LDV is used to indicate the point in time that the Trace Memory outputs are 
stable . 



P/NBSRS 



PPVSTB 



HMCLK 



PBSTBRQ 



HSRS 



HTIMS 



HPLS 



HWRT 



LMV 




LDV 



Figure 8-4. Strobe Generator Block Diagram 



SAC 8-12 



Model 6U62IA - Service 



8-68. How A Strobe Is Generated. 

8-69. Figure &-k is a simple block diagram of the Strobe Generator, and Figure 8-5 
shows the timing relationship of the seven major strobe signals. The time periods 
indicated are approximate values and should not be used for calibration purposes. 

8-70. Six of the seven stages work very much the sajne. Therefore, only the first 
stage will be discussed. The seventh stage is built using OR gates. 

8-71. At time zero, U23 pin 11 goes from a low to a high (the sajne in the run mode 
or Performance Verification mode). Because U23 pin 10 is connected to a high level, 
U23 pin 15 goes high when the positive edge on pin 11 occurs. At the same time, U23 
pin 1^4 begins to go low. Pin ih cannot go low instantly due to the charge in CIO 
and the currents in RI8, R8 and the 2k0 ohms in U9. The amount of time it takes pin 
Ik to reach a low state is determined by these components. 

8-72. The hysteresis of U50 pin 13 is set to -1.55 V by U50 pin 9, two 220 ohm 
resistors in U5I, euid one 2U0 ohm resistor in U35» As U50 pin 13 {U23 pin Ik) goes 
negative (the hysteresis level being crossed), U50 pin 15 goes positive, changing 
the hysteresis level. This action is fed back to U50 pin 12 and enhances U50 pin 13 
going negative, causing U50 pin 15 to change to a high state very quickly. 

8-73. The output of stage one, U50 pin 15, is fed to the next stage, providing U23 
pin 6 with a positive going clock. The same action as in stage one now begins in 
stage two. This effect ripples through the remaining stages. 

8-7U. The output of 1150 pin 15 is also sent back to the reset input, of U23B pin 13. 
VJhen U50 pin I5 goes high, U23B is reset, causing U23 pin 15 to go low. This action 
defines the pulse width of HSRS. 

8-75 • At the same time, U23 pin lU is going high at the rate defined by the RC net- 
work. When U50 pin 13 reaches the positive hysteresis U50 pin 15 goes low. The 
reset mode (U23 pin 13) is now removed and stage one is ready to begin the cycle 
again. 



SAC 8-13 



Model 6U62IA - Service 



TIME IN NANOSECONDS 
0 25 50 



HSRS 
U23, 15 



75 100 125 150 175 200 225 250 275 300 



-45- 



•85- 



•89 



■89 



130 



■172- 



•20 



-23 



■47- 



245- 



48- 



-80- 



■55 



25 50 75 100 125 150 175 200 225 250 275 300 



Figure 8-5. Strobe Timing Relationship 



SAC 8-lU 



Model 6U62IA - Service 



8-76. SEQUENCER. 
8-77. Description. 



8-78. The Sequencer consists of memories, counters and latches. Its purpose is to 
enable various fvmctions of the State Analyzer Subsystem when a series of states or 
events have occurred in the system under test. The Sequencer hardware contains 
feedback circuitry which combines the sequence state with incoming data to form the 
next sequence state. The Sequencer is a good example of a synchronous state 
machine . 



8-79. Functions. 



8-80. The Sequencer can enable and disable all functions of the State Analysis 
Subsystem. See Figure 8-6. It caji also cause the State Analyzer to trigger, store, 
and drive the 1MB master enable. It must be loaded before execution of a trace or 
overview. To operate the Sequencer, the operator must specify a series of terms 
and/or windows. The terms usually represent states (e.g. an address or a data 
value) and the windows are an enable/disable pair of terms. Then the operator 
specifies the order in which these terms must occur, how many times each must occur 
(occurrence), and whether the next term must occur immediately or eventually. The 
operator must specify which sequence term will enable a function, ajid which term 
will disable a function. The operator may also specify which terms will restart the 
sequencer. Further details are available in the operator's maaiual. 



LOAD 



DATA INPUT. 



SEQUENCER 



ENABLE/DISABLE 



STORE 



TRIGGER 



STROBE 



> 

> 



COUNT 
OVERVIEW 
FUNCTION 



COUNT 
FUNCTION 



STORE 
FUNCTION 



TRIGGER 
FUNCTION 



OVERVIEW 
FUNCTION 



MASTER 
ENABLE 
FUNCTION 



Figure 8-6. Sequencer Functions 



SAC 8-15 



Model 6U62IA - Service 



8-81. Sequencer Specifications. 

Depth 3 choices: 15 terms with restarts, no windows 

7 terms with restarts , one window 
3 terms without restarts, two windows 

Occurrence 1 to 65535 times 

Enable/Disable separately 

Immed iate ly /Eventually quali f icat ion 

8-82. The depth is due to the feedback signals, Bus Sequence State (BSSO-3). Four 
signals allow only sixteen permutations, and one cannot be used. A window uses a 
signal, and it caimot be used by the terms. The Sequence Occurrence Counter is a 
sixteen bit counter. 

8-83. Sequencer Block Diagram. 

8-8U. The major components of the Sequencer are the Sequence Pattern Trigger Memory, 
the Sequence State Latch/Counter, the Sequence Transistion Memories, the Sequence 
Occurrence Counter Memories, and the Sequence Occurrence Counter. All of these com- 
ponents are located on the Control Board except the Trigger Memories which are lo- 
cated on the Data Acquisition Boards. All the Memories must be loaded with informa- 
tion from the Mainframe before a trace begins. 

8-85. During a trace, synchronous data (e.g. SYNDO-I9 on a 20 Channel Acquisition 
Board) from the State Recognition Latch/Coiinter provides part of an address to the 
Sequence Pattern Trigger Memory. The remainder of the address is provided by Bus 
Sequence State (BSSO-3), the last sequence state. The Trigger Memories output a se- 
quence pattern (LBSPO-3). All Trigger Memories are wire ORed, ajid will drive a se- 
quence pattern signal true (low) if all the Memories were loaded with a true state 
at the address supplied by the incoming data and the sequence state. 

8-b6. The sequence pattern is applied to the Sequence State Latch (this register is 
used as a counter only to load memories before a trace) after modification by the 
DME Gate. The DME, disjoint minterm event, is formed by inverting LBSP3 and ORing 
the result with LBSP2. This allows the operator to specify one term which has the 
form "ADDRESS <> OFE5H" . In other words, the operator can specify one "not equal 
to" term. Only LBSPO-2 are left as inputs to the Sequence State Latch. 

8-87. BSSO-3 supplies four more inputs to the Sequence State Latch. BSSO-3 is out- 
put by the Sequence Transition Memories and forms the major feedback path for the 
Sequencer. The fourth input to the Latch is low Occurrence Carry (LOCCRY) . LOCCRY 
is output by the Occurrence Counter when it has found a term the required number of 
times . 

8-88. At Positive Pipeline Strobe (PPLS), these inputs are latched and applied to 
the Transition Memories, forming a new sequence state, named Trace Sequence State 
(TSSO-7). TSSO-7 is stored in Trace Memory auid can be used by the operator to debug 
code. During performamce verification, the CPU can read TSSO-7 from trace memory to 
verify proper fiinctioning of the Sequencer. 



SAC 8-16 



Model 6U62IA - Service 



8-89. The Sequence Trainsition Memories use TSSO-7 as address lines, and outputs I6 
control signals. These signals include BSSO-3 used to change from one sequence 
state to the next, as well as function enables for count, trigger, store and master 
enable functions, a trigger signal (HSTR) , and a store signal (LSSQ). The Memories 
also output Low Overview Enable (LOVEN) and Low Overview Reset (LOVRST) vdiich con- 
trol Overview on the 20 Chaomel Board. The Memories output two control signals to 
the Sequence Occurrence Counter; Low Sequence Occurrence Counter Load (LSOCLD) and 
Low Sequence Occurrence Counter Enable (LSOCEN) . 

8-90. Function Enables. The Sequencer will enable an Analyzer function only when all 
specified sequence terms have been fovind. The enabling signals serve as inputs to 
the Analysis Controller, except for LOVEN, and are as follows: 



The Sequencer can disable the above functions by driving any of them high. 

8-91. Sequence Occurrence Counter/Memories. This part of the Sequencer controls the 
Occurrence, or, the number of times a sequence state must be found before the 
Sequencer moves on to the next specified state. 

8-92. An Example. Suppose a state must occur 10 times before the Sequencer looks for 
the next state. Before the trace started, the Transition memories were loaded so 
that when the term prior to the 10 times term was found, the Transition Memories 
output Low Sequence Occurrence Counter Load (LSOCLD). At that time, BSSO-3 will 
cause the Occurrence Memories to output terminal count, 65535 > minus 10, or 65525- 
LSOCLD will load the Occurrence Counter with 65526. The next time the sequence pat- 
tern goes true, the Transition Memories will output Low Sequence Occurrence Counter 
Enable, enabling the Occurrence Counter. The Occurrence Counter will be incremented 
by Positive Sequence Occurrence Counter Increment (PSOCINC) due to HWRT strobe. 
This will continue until the Counter reaches terminal count. Then the Counter out- 
puts Low Occurrence Carry (LOCCRY) , which will be latched into the Sequence State 
Latch aind will change the sequence state. 

8-93. Sequencer Troubleshooting. 

8-9U. Performance verification on the Control Board tests the Sequencer using Test 
U. The loop includes the feedback paths of LOCCRY and BSSO-3. If signature 
analysis shows that multiple signatures are bad, it is due to the propogation of a 
bad signature around the loop. Test 1 has been provided to break the feedback. It 
is a stimulus test for the Sequencer which writes to all locations of the Transition 
Memories and the Occurrence Memories, and tests the Occurrence Counter, but does not 
latch the next sequence state into the Sequence State Latch. 



LSOCE 

LSCE 

LSSE 

LSTE 

LOVEN 

LSME 



Low Sequence Overview Count Enable 



Low Sequence Count Enable 
Low Sequence Store Enable 



Low Sequence Trigger Enable 

Low Overview Enable 

Low Sequence Master Enable 



SAC 8-17 



Model 6 1*6 21 A - Service 



TERMINAL COUNT 



PSOCINC 



BUS SEQUENCE STATE 



DATA FROM PROBE 



-7^ 



.20 



P/N BSRS 



J 



STATE 




BSS0-3_ 


RECOGNITION 




LATCH/ 


SYNDO-19^ 


COUNTER 




CLK 





SEQUENCE 
PATTERN 

TRIGGER 
MEMORY 



SEQUENCE PATTERNS FROM OTHER ACQ BOARDS 



SEQUENCE 
OCCURRENCE 
COUNTER 



TC 



CLK 



LSOCLD/ 
LSOCEN 



LOAD/ENABLE 



A 



SEQUENCE 
OCCURRENCE 
COUNTER 
MEMORIES 



^ BSSO-3 



BUS SEQUENCE STATE 



BSSO-3^ 



LOCCRY^ 



LBSPO-3 



SEQUENCE 
PATTERN 




DME 



SEQUENCE 
STATE 
LATCH/ 

COUNTER 

CLK 



HPLS 



TSSO-7 



TRACE 
SEQUENCE 
STATE 



SEQUENCE 
TRANSITION 
MEMORIES 



BSSO-3 



LSOCLD/LSOCEN 



LOVEN/LOVRST ^ TO OVERVIEW 



LSOCE/LSCE/LSME/ LSSE/LSTE 



ENABLE ANALYSIS 
^ CONTROLLER FUNCTIONS 

LSSQ/HSTR CONTROL ANALYSIS 

CONTROLLER FUNCTIONS 

TSSO-7 ^ TO TRACE 
MEMORY 



Figure 8-7. 

Sequencer Block Diagram 
SAC 8-18 



Model 6U62IA - Service 



8-95. ANALYSIS CONTROLLER. 

8-96. Description. 

8-97. The Analysis Controller, Ul, is a custom designed IC which controls the master 
enable, coxrnt, store, and trigger functions of the State Analysis Subsystem. Figure 
8-8 is a summary of the Analysis Controller. 

8-98. The Analysis Controller decodes inputs from the Resource Patterns, the 
Sequencer and the Inter Module Bus (1MB), and outputs control signals to all cards 
in the State Analysis Subsystem and to other Analysis Subsystems over the IHB. The 
Analysis Controller must be programmed (loaded) before each execution. 
Electrically, the inputs and outputs are at ECL levels, with the exception of the 
following TTL signals: NTR, NMC, LLOAD, SERDATA, PLCLK, and LRUN. Internally, the 
part is emitter functional logic (EFL), similar in design to ECL. 

LOAD 



I 



RESOURCE PATTERNS ^ 


ANALYZER 
ENABLE 


RESOURCE 
GATING 


COUNT (STATES/TIME/EVENTS) ^ 


STORE (STATES/ELAPSED TIME) 


SEQUENCER 


TRIGGER (TRACEPOINT)^ 


INTERMODULE BUS (1MB) 


IMB^ 







STROBE GENERATOR 



Figure 8-8. Analysis Controller Summary 



8-99. Modes. 



8-100. The Analysis Controller has two primary modes, run mode and load mode, con- 
trolled by LRUN and LLD. The load mode is used to program a 58 ^i't shift register 
inside the Analysis Controller. The parallel outputs of the register initialize and 
determine which of the various inputs will control the Analysis Controller during a 
trace execution. The 58 bits are grouped as follows: 

Storage Function 3 bits 

Trigger Function 6 bits 

Master Enable Function U bits 

Resource Pattern Allocation 30 bits 

Initialize Poststore 10 bits 

Initialize Sequencer Enables 5 bits 

The rim mode is used while executing a trace. 

8-101. Two secondary modes are used during performance verification: nin_load mode 
with both LRUN and LLD low, and not run_not load mode with both LRUN and LLD high. 
R\m_load mode allows the Analysis Controller to r\m but excludes external clocks. 
Not run not load mode is used while testing the Sequencer. 



8-102. Block Diagram. 



SAC 8-19 



Model 6U62IA - Service 



8-103. The Block Diagram shows a time progression from the arrival of resource 
patterns to output of control signals including write control. First there is 
Resource Allocation, then Resource Gating, then Write Qualification. Additional 
major sub-blocks include Analyzer Enable, and 1MB Receive and Drive. 

8-loU. The 58 bit shift register selects which of these sub-blocks or inputs will 
actively be used to produce an output. Finally, the Sequencer plays a major role in 
controlling the State Analysis Subsystem and is referenced in the Block Diagram even 
though it is not physically part of the Analysis Controller. 

8-105. Resource Allocation. On the Acquisition Boards, trace data addresses the 
Resource Pattern Trigger Memories, and the Memories output an 8 bit pattern (wire 
ORed accross all boards) which forms the Resource Pattern input (LBRPO-7) for the 
Analysis Controller. Inside the Analysis Controller, these eight signals are allo- 
cated to various functions, with the following limitations: the sum of the resources 
cannot exceed eight; trigger and store can use up to eight resources; count can use 
up to four resources (LBRP2,3,6,7) ; overview count can use up to four resources 
(LBRP0,1,U,5) ; four resources can be ranges provided a 20 channel board is present; 
a "not" condition requires two resources. The 58 bit shift register uses 30 bits to 
specify which terms will be used by which function. The following table shows an 
example for resource allocation: 

STATE RECOGNITION RESOURCES 



trigger 


on 


ADDRESS 




UOOOH and STATUS = Mem read 


#1 




or 


ADDRESS 




itOOOH and DATA <> 0 


#2, #3 




or 


ADDRESS 




range OH thru OFFH 


#1+ 


store 


on 


ADDRESS 




rai.ge UOOOH thru 14135H 


#5 




or 


ADDRESS 




OFOOOH 


#6 


coxint 


on 


ADDRESS 




6OOOH 


#7 




or 


STATUS 




10 in 


#8 



8-106. The table shows k resources used by trigger, 2 by store and 2 by count. 
Because of the "DATA <> 0", the second specification line for trigger required 2 
resources. Internally, this is done by DME (disjoint minterm event) gating, which 
requires one resource to find DATA ~ 0, and a second resource to invert it. 
Pipeline Strobe (HPLS) latches the count, store and trigger resources, and they are 
applied to Resource Gating, 

8-107. Resource Gating. The count, storage and trigger resources are gated with the 
Sequencer, 1MB, and Analyzer Enable, and output as Overview Count Qualify (HOCQ) , 
Store Flag (LSFLG) and Trigger (NTR). The 58 bit shift register uses I8 bits 
(Storage Function, Trigger Function, Analyzer Enable Function, Initialize Sequencer 
enables) to specify which inputs to Resource Gating will be looked at. The default 
state for these bits cause the Analysis Controller to count everything, store al- 
ways, and trigger on anything. 

8-108. Write Qualification. Write Qualify Gating determines which trace data will be 
written into the Trace Pod Data Memories. Low Strobe Enable (LSE) is directly 
produced by Storage Qualify Gating, and can be modified by the Trace Point Latch and 
the Measurement Complete Latch. The Trace Point Latch is set by the first trigger 
(NTR) , then it enables the Post-Trace Point Counter to count each time data is 



SAC 8-20 



Model 6U62IA - Service 



stored in the Trace Memories. The Post-Trace Point Counter counts the number of 
states to be stored after trace point, then sets the Measurement Complete (NMC) 
Latch, which disables the Write Qualify Gating (forces HWQ to go low). The 58 bit 
shift register uses 10 bits (Initialize Poststore) to initialize the two latches and 
the PostTrace Point Counter. 

NOTE 

Writing to the Overview Event Memory is not controlled by the 
Write Qualification function. Overview writing is controlled 
directly by the Sequencer and Analyzer Enable. 

8-109. NTR produces a pulse each time the trigger event occurs, and caai be used to 
trigger external test equipment. NMC can be routed to external test equipment, and 
also serve as an overflow for the 58 bit shift register. The overflow function is 
used during performance verification to test the loading of the Analysis Controller. 
Data is input on bit 0 of the data bus (LDBO) and clocked by Positive Write Analysis 
Controller (PWAC). Low Load (LLD) must be low to clock in data. 

8-110. Analyzer Enable. This is the master enable for the entire State Analyzer. 
Master Enable (LME) casi be set low by Run (LRUN) which is a keyboard command to 
begin execution, or it can be received from the 1MB. When LME is strobed by State 
Recognition Strobe (HSRS) , it latches Analyzer Enable 1 (HAEl). When HAEl is 
strobed by Pipeline Strobe (HPLS), it produces Positive Pipeline Strobe (PPLS) which 
is used to strobe the Sequencer, the Data Pipeline Registers, and Analyzer Enable 2 
(HAE2). When HAE2 is strobed by Write (HWRT) , it produces High Bus Overview Write 
Strobe (HBOWRT) and Positive Sequence Occurence Counter Increment (PSOCINC). HBOWRT 
is used to write to the Overview Event Memories on the 20 Channel Acquisition Board. 

8-111. Another source of master enable is the Sequencer. When the Sequencer finds 
all of the required states in the order specified, it can drive Sequence Master 
Enable (LSME) low. LSME then enables the trigger and store functions in the 
Analysis Controller. LSME can also be programmed to drive LME on the 1MB. The 58 
bit shift register uses k bits to specify whether or not the 1MB or Sequencer will 
control Master Enable. 

8-112. IMB Receive and Drive. Master Enable, Trigger and Store functions can be 
received by the Analysis Controller from the IMB. Ulie Analysis Controller c&a 
transmit (drive) Delayed Clock (PDC), as well as Master Enable (LME), Trigger (HTR) , 
Trigger Enable (LTE), and Store Enable (LSE). When the Analysis Controller is 
receiving IMB signals, the signals are latched with the State Recognition Strobe 
(HSRS) and applied to the Resource Gating after Pipeline Strobe (HPLS). When the 
Analysis Controller is driving the IMB, they are strobed out by Write (HWRT). The 
58 bit shift register is responsible for determining which IMB signals are active. 

8-113. Sequencer. The Sequencer is an integral part of the Control Board and should 
be considered an extension of the Analysis Controller. The inputs to the Resource 
Gating from the Sequencer are similar to the inputs from the IMB Receiver. It is 
the 58 bit shift register which determines which circuitry will actively control the 
State Analyzer during a particular run. The Sequencer can perform a master enable 
function by setting Sequence Master Enable (LSME) low. The Sequencer alone controls 
Overview Enable (LOVEN) and Overview Reset (LOVRST) . 



SAC 8-21 



Model 6U62IA - Service 



8-114. Timing of Analysis Controller. 

8-115. The Strobe Generator controls timing of the Analysis Controller by use of 
State Recognition Strobe (HSRS) , Pipeline Strobe (HPLS) and Write Strobe (HWRT). 



HSRS / \ 



/ \ 



I / \ 

I I I 

95 nS 135 nS 180 nS 

Prior to Resource Allocation, the Resource Patterns, Analyzer Enable, and 1MB are 
clocked by HSRS. After Resource Allocation, HPLS clocks the Sequencer and all other 
inputs, so that Resource Gating is valid. Finally, HWRT clocks out write signals, 
and HWRT going low clocks the 1MB Drive. Internal delays are in the several 
nainosecond range due to the EFL logic design. 



HPLS I 

HWRT I 

0 nS 



SAC 8-22 



Model 6U62IA - Service 



RESOURCE 
"ALLOCATION" 



RESOURCE 
" GATING " 



WRITE 
"QUALIFICATION" 



RESOURCE PATTERNS LBRP 0-7 



RESOURCE 
ALLOCATION 


DME 


OVERVIEW COUNT 
QUAL TERM 2, 3, 6, 7 


PIPELINE 
REGISTER 


TRACE COUNT 
QUAL TERM 0, 1, 4, 5 


STORAGE 
TERM 0-7 


TRIGGER 
TERM 0-7 



HPLS 



OVERVIEW COUNT RESOURCE 



TRACE COUNT RESOURCE 



STORAGE RESOURCE 



TRIGGER RESOURCE 



SEQUENCE PATTERNS LBSP 0-2 



OCCURRENCE CARRY LOCCRY 



BUS SEQUENCE STATE BSS 0-3 



+5V 
-5.2V 
5.2V 



26 



13 



32 



14 



31 



•Vcc 
•Vee 

■ VEE 

GND 
-GND 



'SEQUENCE 
STATE 
LATCH/ 
COUNTER 



TSSO-7, 



'SEQUENCE 
TRANSITION 
MEMORIES 



LSOCE 



LSCE 



LSSE/LSSQ 
LSTE/HSTR 
LSME 



PPLS 



V 



HPLS 



ANALYZER ENABLE 



LRUN 



ME 



ANALYZE 
ENABLE 
GATING 



LME 



ANALYZER 
ENABLE 
1 



HSRS 



HAE1 



-PPLS 



LOVEN/LOVRST 
TO 20 
CHANNEL 
ACQ. BD. 



ANALYZER 
ENABLE 
2 



HPLS 



HAE2 



1MB RECEIVE 



1MB- 



LTE, HTR, LSE 



1MB 
STATE 
RECOGNITION 
REGISTER 



1MB 
PIPELINE 
REGISTER 



LSE 



HAE1 



LTE/HTR 



OVERVIEW 
COUNT 
QUAL 

EN 



TRACE 
COUNT 
QUAL 



EN 



STORAGE 
QUAL 



EN 



TRIGGER 



EN 



HOCQ 



HCQ 



LSFLG . 



NTR 



TRACE 
POINT 
LATCH 



LSE. 



HTR. 



NMC. 



WRITE 
QUAL 
GATING 
EN 



HWQ 



HWRT 



HBQWRT. 



HQWRITE 



NTR 



(TTL) 



HTR. 



HWQ 



HPLS 



POST 
TRACEPOINT 
COUNTER 



EN 



EN 



MEASUREMENT 
COMPLETE 
LATCH 



HAE2 



1MB DRIVE 



HWRT 



HTR 



LSE 



LTE 



LSME/LRUN 



HWRT 



1MB 
OUTPUT 
LATCH 



J^CLK 



PDC 



HSRS 



HPLS 



*NOT PART OF 
ANALYSIS CONTROLLER 



LME, PDC, LTE, HTR, LSE 



LDBO (TTL) 



PWAC (TTL) 



LLD (TTL) 



58 BIT 
> SHIFT REGISTER 

EN 



NMC 



(TTL) 



HBQWRT 



PSOCINC 



Figure 8-9. 
Analysis Controller Block Diagram 

SAC 8-23 



Model 6U62IA - Service 



8-116. STATE/TIME COUNTER. 
8-117. Description. 

8-118. The State/Time Counter is a custom designed 20 bit Gray Code counter with 
prescale. The prescaler allows it to covmt up to 730,000,000,000 states in the 
count states mode, and 8+ hours at a 25 MHz rate in the co\mt time mode. 
Externally, the Counter is ECL except for three TTL inputs. Internally, it is 
emitter-functional- logic (EFL). Chip delay from clock edge to counter outputs is 
approximately 25 nS without prescale. With prescale, chip delay can exceed 100 nS. 
There are 5 prescale factors: 1. divide by 1, 2. divide by 8, 3. divide by 2 
elO, k. divide by 2 el7, and 5. divide by 2 e2U. 

8-119. Where Used. 

8-120. The counter is used on both the 6U621A Control Board and the 6U623A 20 
Channel Acquisition Board. 

8-121. On the Control Board, the Counter is used during trace (256 states), and is 
used during Overview on the 20 Channel Board. Pin 35 controls the Trace /Overview 
modes. On the Control Board pin 35 is tied low, the Trace mode. On the 20 Channel 
Board pin 35 is tied high for the Overview mode. 

8-122. LSTATE, pin 8, makes the decision to count either qualified states or time 
intervals. When LSTATE is low, states between stored qualified states will be 
counted. When LSTATE is high, time between stored qualified states will be counted. 

8-123. Function. 

8-124. Modes. The counter has two modes, the load mode and the normal mode. The 
load mode is used during Performauice Verification. It forces the Counter to act 
like two ten-bit counters without prescale, which qreatly improves loading and test- 
ing efficiency. The normal mode is described in the Block Diagram description. 

8-125. Blocic diagram. The Block Diagram shows inputs on the left and outputs on the 
right. The three major sections are counter control, 20 bit counter, and the output 
latch. 

8-126. Counter Control. The counter control section controls the count, reset, and 
latch functions. The counter's versatility is shown by the triple 2 to I4 selector, 
one selector for each function. Using the count function as an example, if pin 8 is 
a logic high auid pin 35 is a logic high, then overview on time is selected, which is 
input 3 to all functions of the selector. This means that the control section will 
count using 25 MHz as input (PINC is used to count states); it will reset when PSET 
goes high, and it will latch the covint when PLATCH goes high. The count pulse must 
be enabled by a high counter enable (HCE) in order to reach the prescale circuitry. 
The prescaler will pass pulses directly to the 20 bit counter vmtil the count ex- 
ceeds 611,000. Then the 3 bit exponent will cause the prescaler to divide by 8 
before allowing a coxint pulse. As the count increases, the prescaler will divide by 
2 elO, 2 el7 and finally 2 e2U. 

8-127. PSET (Positive Set). PSET is an edge sensitive input which resets the counter 
to a known state. The counter is locked in that state until the reset function is 
clocked by 25 MHz. The half -way AND gate does not allow PSET to reset the counter 
until it has counted to at least half-way through the divide-by-1 range. 



SAC 8-2U 



Model 6U62IA - Service 



6-128. 20 Bit Counter. The counter provides a 20 bit output consisting of 3 bit ex- 
ponent and a 17 bit mantissa. It operates either as a time counter or as a state 
counter. The time count mode provides a minimum resolution of kO nS with a minimum 
3 digit accuracy from 100 nS to 30 kS (8 hours). The state co\mt mode provides 
single state resolution to 611,670 states, and prescaled counts up to 
750,000,000,000 states. Because it covints in Gray Code (only one bit changes for 
each new state), the outputs appear to chaaxge without a pattern. The counter out- 
puts are reset after each storage event (an exception is > halfway restriction in 
time count), which produces a relative covmt. 

8-129. Output Latch. The Output Latch is controlled by a gate and an output enable. 
Vhen PLATCH goes high, the counter outputs are latched. The exception is PSET. 
When PSET is low and trace state is selected, the latch is transparent; when PSET 
goes high, the counter outputs are latched. Low output enable (LOE) enables the 
output drivers. The counter outputs will be low when LOE is high, or when the 
counter is reset, latched and LOE goes low. 



SAC 8-25 



Model 6U62IA - Service 



PIN # 
32 HCE (ECL) 



+5V 
-3.25V 
3.25V 



8 HTIME/LSTATE (TTL) 



35 HOV/LTRACE (ECL) 



27 PINC (ECL) 



25 PSET (ECL) 



26 PLATCH (ECL) 



9 HLOAD (TTL) 



7 LOE (TTL) 



1 

10 
31 
11 
28 

"29 



■Vcc 
Vee 
Vee 
GND 
GND 
GND 



V 





TRACE STATE 
TRACE TIME 
OV STATE 
OV TIME 




RESET 



LATCH 



> 



20 BIT GRAY 
CODE COUNTER 



EXP 

MANTISSA 
TEN/TEN R 



J 



OUTPUT 
^ LATCH 



17 



G EN 



Figure 8-10. 

State/Time Counter Block Diagram 
SAC 8-26 



Model 6U62IA - Service 



8-130. MNEMONICS. 

8-131. The signals in this product have been assigned nmeraonics that indicate the 
true state, auid the function of the signal line. In general the first character in- 
dicates the true state, H for high, 1 for low. If the signal is used with an edge 
sensitive device, P for positive, and N for negative is used to indicate the edge 
that the signal becomes true on. No indication of the voltage levels is given, 
i.e., TTL, ECL, MOS. This information is given on the schematic using the newer 
type of Logic Symbology. 

Table 8- 1. Mnemonics 
Mnemonic Description 

BSSO-3 Bus Sequence State 0-3 --a feed back path within the Sequencer that enables 
it to change from one state to the next. A state may require that an event 
occur only once, or it may require the event to occur many times before 
chajiging to the next state. 

CDO-7 Co\inter Data 0-7 outputs of the Trace Counter/Status Memories. The in- 
formation stored in the Memories represents the time between two stored 
states, or the number of states between two stored states. A value for 
each measurement is stored and returned to the CPU (CDO-7, LDBO-7) over the 
CPU's Data Bus for formatting and display on the CRT. The sequence state 
for each measurement is also returned to the CPU by CDO-7. 

CNTO-19 Count 0-19 --outputs of the Trace State/Time Counter. CNTO-I9 represents 
the time between two stored states, or the number of states between two 
stored states. The value (CNTO-I9) for each measurement is stored in the 
Trace Count/Status Memory. 

GNDSEN Ground Sense -- the return path from the Clock Probe for the Clock 
Threshold Digital to Analog Converters. 

HBOTF High Bus Overview Trigger Flag -- from the ACQ Board. When high, indicates 
that the 20 Channel Acquisition Board has seen a qualified trigger event. 
(A trigger event is a single occurrence of an event decoded from input data 
or from the Overview State/Time Counter.) HBOTF comes from the 20 Channel 
ACQ Board only. 

HBOVCQ High Bus Overview Count Qualify -- sent only to the 20 Channel Data 
Acquisition Board. When high, HBOVCQ allows the Overview Counter to incre- 
ment. HBOVCQ may be driven by the Analysis Controller or HOVCQ. 

HBOWRT High Bus Overview Write -- sent to the 20 Channel Acquisition Board only. 

When high, HBOWRT enables write circuits on the 20 Chajinel ACQ Board for 
writing to the Overview Event Memories. HBOWRT is also used to increment 
the Overview Trace State/Time Counter, and can drive PSOCINC due to a wire 
OR connection (see PSOCINC). When enabled on the 20 Channel Data 
Acquisition Board, HBOWRT allows the Overview Event Memories to be written 
to and increments the Overview Memory Address Counters. 

HBQWRT High Bus Qualified Write -- when high, HBQWRT synchronizes the Trace Pod 
Data Memories in the Acquisition Boards with the Trace Counter /Status 



SAC 8-27 



Model 6I+62IA - Service 



Table 8-1. Mnemonics (Cont'd) 



Mnemonic 



Description 



Memories in the Control Board. When low, HBQWRT increments the Trace Pod 
Data Memory Address Counters in the Data Acquisition Boards. HBQWRT is 
enabled by HWQ, and is derived from HWRT. 

HCDO-1 High Clock Data 0-1 -- outputs from the Clock Term Generator, U25, returned 
to the Mainframe. Used in Performance Verification to indicate that the 
Term Generator can respond to the various combinations of clocks and 
qualifiers input from the Clock Probe or Preprocessor. 

HCLKO-7 High Clock 0-7 -- differential (LCLKO-7) clock signals or qualifier bits 
from the user's equipment. The eight bits are defined to be clocks or 
qualifiers by keyboard entry. HCLKO-7 may come from either the Clock Probe 
or the Preprocessor. 

HCQ High Count Qualify -- when high, HCQ enables the Trace State/Time Counter 

to increment. HCQ develops HCQB. The status of HCQ is stored in the Trace 
Count/Status Memory. When a high is stored for HCQ, the software will add 
the value one to the stored value in the Trace Count /Status Memory. 

HCQB High Count Qualify Buffered --a flag returned to the CPU. When high, HCQB 
indicates that the Trace State/Time Counter may have been counting when the 
user's information was stored. 

HCTST High Coiuit Test -- used when testing the Trace State/Time Counter. When 
high, HCTST divides the Counter into two ten bit counters. HCTST is con- 
trolled by the CPU. 

HDVLD High Data Valid -- derived from the Strobe Generator. When high, HDVLD has 
latched CDO-7 into the Trace Data Read Register. When LRTDR is low, the 
latched information is presented to the CPU over the Data Bus. HDVLD is 
also returned to the CPU through the Analysis Status Buffer indicating that 
information has been latched into the Trace Data Read Register. 

HENHLT High Enable Halt -- when high, HENHLT allows PHALT to be sent to the 
Preprocessor. HENHLT is CPU controlled. 

HENSTIM High Enable Stimulus -- when high, HENSTIM allows PSTIM to be sent to the 
Preprocessor. HENSTIM is CPU controlled. 

HINV High Invert — when high, inverts the two signals going to PORTl and P0RT2. 
The inversion may be selected by a keyboard command. 

HLD High Load -- when high, HLD switches the Sequence State Latches /Counter to 

the coiint mode. The outputs of the Counter are used to address the 
Sequence Transition Memories while loading information from the CPU 
(LDBO-7/LSEQDO-7) . HLD and LLD are asserted at the same time. 



HMCLK High Master Clock ~- when going from a low to a high, HMCLK indicates that 
the eight clock inputs have satisfied the requirements that have been 
programmed into the Clock Term Generator by the CPU and has started the 
Strobe Generator Cycle. HMCLK is wire ORed with PPVSTB and PBSTBRQ. 



SAC 8-28 



Model 6U62IA - Service 



Table 8-1. Mnemonics (Cont'd) 
Mnemonic Description 

HOTFB High Overview Trigger Flag Buffered -- from the ACQ Board. When high, in- 
dicates that the 20 Channel Acquisition Board has seen a qualified trigger 
event. (A trigger event is a single occurrence of an event decoded from in- 
put data or from the Overview State/Time Counter.) HOTFB comes from the 20 
Channel ACQ Board only. 

HOVCQ High Overview Count Qualify -- HOVCQ becomes HBOVCQ. When high, HOVCQ al- 
lows the Overview Counter on the 20 Channel Data Acquisition Board to in- 
crement. HOVCQ is derived from the Analysis Controller or HLD. 

HOVS High Overview Strobe -- generated in the Strobe Generator. Develops LBOVEN 
and PBOVRST. These two signals are used on the 20 Channel Data Acquisition 
Board only. 

HPLS High Pipeline Strobe -- developed in the Strobe Generator. HPLS is used by 
the Control Board ajid both Data Acquisition Boards for latching information 
into the Pipeline Reqisters at the correct time in the Analyzer's timing 
cycle (PBPLS). 

HQWRITE High Qualified Write --when high, HQWRITE is used to write to the Trace 
Counter /Status Memories, and to internally reset the Trace State/Time 
Counter. HQWRITE going low increments the Trace Count/Status Memory 
Address Counter. HQWRITE is derived from HWRT and enabled by HWQ. 

HSRS High State Recognition Strobe -- developed in the Strobe Generator. HSRS 
is used to clock the State Recognition Register in the Analysis Control 
chip. The purpose of the register is to store information received on the 
Intermodule Bus (1MB). HSRS also clocks LRUN. 



HSTR High Sequence Trigger 
been found. 



when high, indicates that a Sequence Trigger has 



HTCLK High Transfer Clock -- a differential clock (LTCLK) used in the 
Preprocessor. When HTCLK goes from a low state to a high state, data is 
transferred to/from the State Analyzer and the Preprocessor. 

HTIMS High Time Strobe -- developed in the Strobe Generator. Used in the Trace 
State/Time Counter (PLATCH). When HTIMS goes from a low to a high, the in- 
formation inside the Trace State/Time Counter is latched into its output 
latches . 

HTR High Trigger -- HTR is one of the bidirectional signals that make up the 

Intermodule Bus (1MB). HTR is used to indicate to other modules connected 
to the 1MB that a trigger event has been found. Being bidirectional, the 
State Analyzer can tell other modules that it has found a trigger, or ob- 
serve that smother module has fovind a trigger event. HTR is wire ORed with 
other modules. 



HWQ High Write Qualify -- generated by the Analysis Controller. HWQ is used to 

enable HBQWRT, and stops the Trace State/Time Counter when the output of 
the Counter is being stored in the Trace Counter/Status Memories. 

SAC 8-29 



Model 6I+62IA - Service 



Table 8-1. Mnemonics (Cont'd) 



Mnemonic 



Description 



HWRT High Write -- developed in the Strobe Generator. HVJRT is used to transfer 
storage commands from the inputs to the outputs of the Analysis Controller 
at the correct time in the data acquisition cycle, auid to provide timing 
for other write signals. 

L25MHZ Low 25 Megahertz --a high accuracy crystal controlled clock originating in 
the Mainframe. L25MHZ is used to clock the Trace State/Time Counter when 
in the time mode for measuring time between states. 

LAO-13 Low Address 0-13 -- a I6 bit address bus generated by the CPU and used to 
address various devices in the system. Only bits 0-13 are used in this 
model. 

LABO-13 Low Address Buffered 0-13 -- same as LAO-13 with additional buffering. 
LABO-13 may also be latched from the Address Bus. 

LBCLR Low Bus Clear -- same as LCLR except buffered. LBCLR is sent to the 20 and 
UO Chamnel Data Acquisition Boards to clear various counters and registers. 

LBMACS Low Bus Memory Address Coxinter Select -- developed in the Strobe Generator. 

Used in the 20 and UO Channel Data Acquisition Boards. When low LBMACS al- 
lows the Memory Address Counters (on the ACQ Boards) to address the Trace 
Pod Data Memories. When high, the CPU csoi address the Memories over the 
CPU Address Bus. 

LBOVEN Low Bus Overview Enable developed from HOVS. LBOVEN is used only on the 
20 Channel Data Acquisition Board. When low, LBOVEN allows the Overview 
section to look for its trigger events and enables overview storage. 

LBRPO-7 Low Bus Resource Pattern 0-7 -- eight signals coming from the Data 
Acquisition Boards. When low, indicates to the Analysis Controller that 
combinations of Trigger, Storage, and Count information have been detected. 

LBSPO-3 Low Bus Sequence Pattern 0-3 four signals coming from the Data 

Acquisition Boards. When low, they indicate to the Sequencer that the Data 
Acquisition Boards have found the Sequence State(s) requested by the user. 

LCLKO-7 Low Clock 0-7 -- differential (HCLKO-7) clock signals or qualifier bits 
from the user's equipment. The eight bits are defined to be clocks or 
qualifiers by keyboard entry. LCLKO-7 may come from either the Clock Probe 
or the Preprocessor. 



LCLR Low Clear -- used to clear various counters and registers on the Control 
Board. Derived from the CPU Address Bus and other Mainframe control lines. 
LCLR is also used on the 20 and UO Channel Data Acquisition Boards (LBCLR) 
to clear various covmters and registers . 

LDO-12 Low Data 0-12 -- a I6 bit bidirectional bus used to transfer data to and 
from the CPU. When LSTB is low, the data on the bus is valid. Only bits 
0-12 are used in this model. 



SAC 8-30 



Model 6U62IA - Service 



Table 8- 1. Mnemonics (Cont'd) 
Mnemonic Description 

LDBO-7 Low Data Buffered 0-7 -- same as LDO-7 with additional buffering. LDBO-7 
is distributed throughout the State Analyzer Control Board. 

LDV Low Data Valid -- developed by the Strobe Generator. When low, LDV indi- 

cates that the Trace Memory outputs are stable and the CPU may read them. 

LDVTTL Low Data Valid TTL -- LDVTTL is used to clock the Trace Point Register. 
LDVTTL is derived from LDV in the Strobe Generator. 

LIAO-3 Low Interface Address 0-3 -- signals used for reading and writing informa- 
tion in the Preprocessor. LIAO-3 are derived from the CPU's Address Bus. 

LID Low Identification -- a signal originating in the Mainframe. When low, the 

CPU is requesting that the Board Identification be sent from the State 
Analyzer Control Board to the CPU over the Data Bus on data bits 8 and 12. 

LIDB Low Identification Buffered -- a signal originating in the Mainframe and 
buffered on the State Analyzer Control Board. See LID. 

LIDO-7 Low Interface Data 0-7 -- a bidirectional data bus between the Preprocessor 
ajid the Control Board. LIDO-7 are derived from the CPU's bidirectional 
Data Bus. 

LIWRT Low Interface Write -- one of the control lines from the Control Board to 
the Preprocessor. When low, the Control Board is writing to the addressed 
device, i.e., the Preprocessor. LIWRT is the same as LWRT except buffered 
two times (LWRTB) . 

LLD Low Load -- when low, LLD allows the internal registers of the Analysis 

Controller to be loaded with serial data (LBDO) from the CPU. LLD and HLD 
are asserted at the same time. 

LMACS Low Memory Address Counter Select -- developed in the Strobe Generator. 

When low, LMACS allows the Trace Cotmt/Status Memory Address Counters (on 
the Control Board) to address the Trace Counter/Status Memories. When 
high, the CPU can address the Memories over the CPU Address Bus. 

LMAP2 Low Map 2 -- a signal developed by the CPU. LMAP2 is used as the Start/Stop 
Pulse in Signature Analysis sind appears only on the extender card. 

LMC Low Measurement Complete -- when low, LMC indicates that the State Analyzer 

has stored all the information requested by the user in the Trace Memories. 

LME Low Measurement Enable -- LME is one of the bidirectional signals that make 

up the Intermodule Bus (1MB). When LME is low, the State Analyzer is al- 
lowed to operate in a normal mode without waiting for other modules. If 
the State Analyzer is operating in the Measurement Enable Mode and LME is 
high, it may not drive or receive any 1MB functions. LME is wire ORed with 
other modules . 



SAC 8-31 



Model 6I162IA - Service 



Table 8-1. Mnemonics (Cont'd) 
Mnemonic Description 

LMS Low Memory Select -- developed from LSEL and LSTM. "When low, LMS latches 

the CPU Address Bus (LAO-13), LWRT, and LID into the Address Latches. At 
the same time, LMS enables the CPU Data Buffer (bidirectional). If LRSTB 
is low, the CPU caoi send information to the Control Board over the CPU Data 
Bus (LDO-12). If LRSTB is high, the CPU can read information from the 
Control Board. 

LMSYN Low Memory Synchronize -- a signal sent to the CPU. When low, the CPU is 
forced to wait vintil the Control Board can complete a read or write 
operat ion . 

LMV Low Memory Valid -- developed by the Strobe Generator. When low, LMV 

generates PMACRS and NMACRS if PBRSTB has occurred. 

LOCCRY Low Occurrence Carry -- when low, LOCCRY indicates that the Sequence 
Occurrence Counters have reached terminal count. 

LOVEN Low Overview Enable -- LOVEN is sent only to the 20 Channel Data 
Acquisition Board. When low, LOVEN allows the Overview section to look for 
its Trigger Events. LOVEN is strobed to the 20 Channel Board with HOVS. 
LOVEN is developed in the Sequencer. 

LOVRST Low Overview Reset -- developed in the Sequencer and used only in the 20 
Channel Data Acquisition Board. LOVRST is used to reset the Overview 
Coxmter. 

LPOP Low Power On Preset -- when low (during Mainframe power-up or during A.C. 

power line disturbances), LPOP resets various latches, counters, and 
registers to a known state. When LPOP returns to a high state, the 
Mainframe begins executing software. 

LPPBEN Low Preprocessor Buffer Enable -- when low, LPPBEN enables the Preprocessor 
Data and Address Buffers to allow information to be transferred to/from the 
Preprocessor. 

LPPSTB Low Preprocessor Strobe -- developed in the Mainframe Interface Circuits. 

LPPSTB develops HTCLK/LTCLK. LPPSTB transfers data to/from the State 
Analyzer and the Preprocessor. 

LRC Low Register Clock -- a clock developed from the CPU's Address Bus and 

LWRT. LRC is used to latch information from the CPU's Data Bus into 
Control Registers U120 and U123, generating various control signals for the 
State Analyzer Control Board. 

LRDEN Low Read Enable -- developed in the Mainframe Interface Address Decoder. 

When low, LRDEN enables the CPU Read Decoder. The CPU Read Decoder in turn 
selects one of five registers or buffers to place information from the 
Control Board onto the CPU Data Bus. 



SAC 8-32 



Model 6U62IA - Service 



Table 8-1. Mnemonics (Cont'd) 
Mnemonic Description 

LRMACR Low Read Memory Address Coiinter Register -- when low, LRMAC enables the 
Trace Memory Address Counter Read Register allowing the value of the Trace 
Count/Status Memory Address Counters to be read over the CPU's Data Bus. 

LRSQRG Low Read Sequence Register -- when low, LRSQRG enables the Sequence Read 
Register allowing the value of the Sequence State Latch/Counters (TSSO-7) 
to be read over the CPU's Data Bus. 

LRSTB Low Read Strobe -- developed in the Mainframe Interface from LWRTB and 
LIDB, LSTB and LSEL. When low, LRSTB allows information to be placed on 
the CPU Data Bus. 

LRSTS Low Read Status -- when low, LRSTS enables the Analysis Status Buffer al- 
lowing the states of eight different signals to be read over the CPU's Data 
Bus . 

LRSTSS Low Reset Sequence State Coxinter -- when low, LRSTSS resets the Sequence 
State Counter to zero. The Counters cannot begin counting until LRSTSS 
returns to a high state. LRSTSS is developed from the CPU's Address Bus 
and other control lines from the CPU. 

LRTDR Low Read Trace Data Register -- when low, LRTDR enables the Trace Data Read 
Register allowing the contents of the Trace Counter/Status Memories (CDO-7) 
to be read over the CPU's Data Bus. 

LRTPRG Low Read Trace Point Register -- when low, LRTPRG enables the Trace Point 
Register allowing the value of the Trace Count/Status Memory Address 
Counters to be read over the CPU's Data Bus. 

LRUN Low Run -- master enable for the Control Board generated by the CPU. When 
low, LRUN enables the Analysis Controller aind is returned to the CPU 
through the Analysis Status Buffer. 

LSCE Low Sequence Counter Enable -- a Sequencer output used by the Analysis 
Controller to determine when the Trace State/Time Counter should be 
enabled . 

LSCLK Low Slow Clock -- when low, LSCLK indicates that it has been at least 100 
mS since the last HMCLK. The status of LSCLK is returned to the CPU 
through the Analysis Status Buffer over the CPU Data Bus. 

LSE Low Storage Enable -- LSE is one of the bidirectional signals that make up 

the Intermodule Bus (1MB). When LSE is low, the Storage Qualify function 
is enabled in the State Analyzer and will store information when another 
module tells it to. LSE is wire ORed with other modules. 

LSEL Low Select -- a signal originating in the Mainframe. When low, LSEL allows 
the State Analyzer Identification Code to be returned over the CPU's Data 
Bus. This allows the CPU to identify if there is a State Analyzer Control 
Board installed in the Mainframe, and if so which slot of the Card Cage it 



SAC 8-33 



Model 6U62IA - Service 



Table 8-1. Mnemonics (Cont'd) 

Mnemonic Description 

is installed in. LSEL is also used to enable the State Analyzer Control 
Board . 

LSEQDO-7 Low Sequence Data 0-7 the data path the CPU uses to load information 
into the Sequence Transition and Sequence Occurrence Memories prior to a 
measurement (LDO-7, LDBO-7, and LSEQDO-7). 

LSFLG Low Store Flag -- an Analysis Controller output. LSFLG is used as a flag 
in the Trace Counter/Status Memories. When low, LSFLG indicates when 
storage is enabled. 

LSFLGB Low Store Flag Buffered -- LSFLGB is the same as LSFLG except translated 
from an ECL level to a TTL level. When low, LSFLG indicates when storage 
is enabled. 

LSME Low Sequence Master Enable -- an Analysis Controller input. When low, LSME 
enables the LRUN portion of the Analysis Controller. LSME is an output of 
the Sequence Transition Memory. 

LSOCE Low Sequence Overview Count Enable -- aji Analysis Controller input. When 
low, LSOCE enables LBRPO-7 to generate HOVCQ. LSOCE is an output of the 
Sequence Transition Memory. 

LSOCEN Low Sequence Occurrence Counter Enable -- when low, LSOCEN allows the 
Sequence Occurrence Counters to count up. The commsuid to enable is stored 
in the Sequencer by the CPU (LDBO-7, LSEQDO-7) . LSOCEN is an output of the 
Sequence Transition Memory. 

LSOCLD Low Sequence Occurrence Coimter Load -- when low, LSOCLD allows the value 
stored in the Sequence Occurrence Memories to be loaded into the Sequence 
Occurrence Counters. The command to load the Coianters is stored in the 
Sequencer by the CPU (LDBO-7, LSEQDO-7). LSOCLD is an output of the 
Sequence Transition Memory. 

LSSE Low Sequence Store Enable -- an Analysis Controller input. When low, LSSE 
enables LBRO-7 to generate LSFLG. LSSE also enables HWQ. LSSE is and out- 
put of the Sequence Transition Memory. 

LSSQ Low Sequence Store Qualify -- an Analysis Controller input. When low, LSSQ 
qualifies LBRPO-7. When qualified, LBRPO-7 generates LSFLG. LSSQ also 
qualifies HWQ. LSSQ is an output of the Sequence Transition Memory. 

LSTATE Low State -- LSTATE controls the two modes of the Trace State /Time 
Counter. When LSTATE is low, the Counter counts the number of states be- 
tween two stored states. PINC is used to increment the counter in the 
state mode. When LSTATE is high, the Counter counts time using L25MHZ as a 
reference. 

LSTB Low Strobe -- a signal orginating in the Mainframe. When low and the CPU 
is in the write mode (LWRT low) , LSTB indicates the Data Bus has valid 



SAC 8-3U 



Model 6I+62IA - Service 



Table 8-1. Mnemonics (Cont'd) 

Mnemonic Description 

information on it. When low and in the read mode, LSTB indicates that the 
CPU is not driving the Data Bus, and the device addressed may now drive it. 

LSTE Low Sequence Trigger Enable -- a Sequencer output used by the Analysis 
Controller. When LSTE is low, the Analysis Controller enables NTRIG. 

LSTM Low Start Memory --a signal originating in the Mainframe. When low, LSTM 
indicates that the information on the CPU's Address Bus is valid. 

LTCLK Low Transfer Clock -- a differential clock (HTCLK) used in the 
Preprocessor. When LTCLK goes from a high state to a low state, data is 
transferred between the State Analyzer and the Preprocessor. 

LTCSMSO-3 Low Trace Count/Status Memory Select 0-3 -- LTCSMS is used to enable (chip 
select) the Trace Coiinter/Status Memories. 

LTE Low Trigger Enable -- LTE is one of the bidirectional signals that make up 

the Intermodule Bus (1MB). When LTE is low, the Trigger Recognition func- 
tion is enabled in the State Analyzer. LTE is wire ORed with other 
modules . 

LTP Low Trace Point -- LTP is normally high. The traoisition from high to low 

indicates that the State Analyzer has found the Trigger Event requested by 
the user. 

LTRCP Low Trace Point -- LTRCP is normally high. The transition from high to low 
indicates that the State Analyzer has found the Trigger Event requested by 
the user. LTRCP is returned to the CPU through the Analysis Status Buffer. 

LWOCML Low Write Occurrence Memory Lower -- when low, the CPU can load information 
into the Lower Sequence Occurrence Memories (LSEQDO-7). 

LWOCMU Low Write Occurrence Memory Upper -- when low, the CPU can load information 
into the Upper Sequence Occurrence Memories (LSEQPO-7) • 

LWRAP Low Wrap --a status signal returned to the CPU at the CPU's request. When 
low, LWRAP indicates that the Trace Counter/Status Memories are full of 
information. 

LWRT Low Write -- one of the control lines from the Mainframe. When low, the 
CPU is writing to the addressed device, i.e., the State Analyzer Control 
Board . 

LWRTB Low Write Buffered -- one of the control lines from the Mainfrajne with ad- 
ditional buffering. When low, the CPU is writing to the addressed device, 
i.e., the State Analyzer Control Board. 

LWRTSTB Low Write Strobe -- CPU controlled. When low, LWRTSTB enables the 
Mainframe Interface Write Decoders when the CPU wants to do a write cycle 
on the Control Board. 



SAC 8-35 



Model 6U62IA - Service 



Table 8-1. Mnemonics (Cont'd) 
Mnemonic Description 

LWSEQML Low Write Sequence Memory Lower -- when low, the CPU can load information 
into the Lower Sequence Transition Memories (LSEQPO-7). LWSEQML is 
developed in the Write Decoders. 

LWSEQMU Low Write Sequence Memory Upper -- when low, the CPU can load information 
into the Upper Sequence Transition Memories (LSEQDO-7) . LWSEQMU is 
developed in the Write Decoders. 

LWTHSl Low Write Threshold 1 -- when LWTHSl goes from a high to a low, information 
from the CPU is latched into the Digital to Analog Converter. The output 
current is proportional to the binary value latched. ((Full Scale Current 
X Binary Value Latched) /256 = Output Current.) 

LWTHS2 Low Write Threshold 2 -- when LWTHS2 goes from a high to a low, information 
from the CPU is latched into the Digital to Analog Converter. The output 
current is proportional to the binary value latched. ((Full Scale Current 
X Binary Value Latched) /256 = Output Current.) 

NBDSTB Negative Bus Data Strobe -- a differential signal (PBDSTB), developed in 
the Strobe Generator. Used to latch the outputs of the Trace Pod Data 
Memories into the Trace Pod Data Latch on the Data Acquisition Boards. 

NBSRS Negative Bus State Recognition Strobe -- a differential strobe (PBSRS) 
developed in the Strobe Generator, and sent to the Data Acquisition Boards. 
At the beginning of a data acquisition cycle, NBSRS goes from a high state 
to a low state. NBSRS is used to latch user information into the State 
Recognition Latches/Counters. 

NDSTB Negative Data Strobe -- a differential signal (PDSTB) developed in the 
Strobe Generator. NDSTB and PDSTB are used to develop HDVLD (see HDVLD) . 

NIHALT Negative Interface Halt -- a differential signal (PIHALT) sent to the 
Preprocessor that can be used to halt the user's system. 

NINCSS Negative Increment Sequence State -- when NINCSS goes from a high to a low 
state, the Sequence State Latch/Counter will be incremented one state when 
in the count mode. NINCSS is developed by the CPU and is wire ORed with 
PPLS. 

NISTIM Negative Interface Stimulus -- a differential signal (PISTIM) sent to the 
Preprocessor. NISTIM is developed from PSTIM when enabled by HENSTIM. 
NISTIM goes from a high to a low state when a Trigger Event or Sequence 
Event occurs if enabled by the user. 

NMACRS Negative Memory Address Counter Register Strobe -- a differential signal 
(PMACRS) developed in the Strobe Generator. NMACRS is used to latch infor- 
mation from the Trace Count/Status Memory Address Counters into the Trace 
Memory Address Counter Read Register. The information in the Register is 
placed on the CPU Data Bus when LRMACR goes low. 



SAC 8-36 



Model 6U62IA - Service 



Table 8-1. Mnemonics (Cont'd) 



Mnemonic 



Description 



NMC Negative Measurement Complete -- an output from the Analysis Controller. 

When low, NMC indicates to the CPU that the information requested by the 
user has been stored in the Trace Memories. NMC also latches LMC into the 
Port Latch. 

NOCSTB Negative Occurrence Counter Strobe -- NOCSTB is developed from the CPU's 
Address Bus and other control lines from the CPU. NOCSTB is used to 
develop PSOCINC. NOCSTB is used only during performance verification. 

NSEQEV Negative Sequence Event -- when going from a high state to a low state, 
NSEQEV indicates that either a Sequence Event has been found, or the 
Sequence Occurrence Counters have been incremented. NSEQEV can develop 
PSTIM, a State Analyzer output. 

NSQRGS Negative Sequence Register Strobe -- a differential signal (PSQRGS) 
developed in the Strobe Generator. NSQRGS is used to latch information 
from the Sequence State Latch/Counters into the Sequence Read Register. 
The information in the Register is placed on the CPU Data Bus when LRSQRG 
goes low. 

NTRIG Negative Trigger --am Analysis Controller output. NTRIG goes from a high 
state to a low state each time the Trigger Event specified by the user oc- 
curs. NTRIG latches LTP into the Port Latch and LTRCP into the Trace Point 
Latch. 

PBDSTB Positive Bus Data Strobe -- a differential signal (NBDSTB) , developed in 
the Strobe Generator. Used to latch the outputs of the Trace Pod Data 
Memories into the Trace Pod Data Latch on the Data Acquisition Boards. 

PBOVRST Positive Bus Overview Reset -- developed from HOVS. PBOVRST is used only 
on the 20 Channel Data Acquisition Board. When PBOVRST goes from a low 
state to a high state, the 20 Bit Overview Counter is reset. 

PBPLS Positive Bus Pipeline Strobe -- saune as HPLS except buffered. Used in the 
20 and Channel Data Acquisition Boards for latching information into 
Pipeline Registers at the correct time in the Analyzer's timing cycle. 

PBRSTB Positive Bus Read Strobe --a CPU generated signal. When PBRSTB goes from 
a low state to a high state, P(N)DSTB, P(N)MACRS and P(N)SQRGS are enabled 
in the Strobe Generator. These strobes are used to latch internal informa- 
tion into various data registers/memories as it moves from the input of the 
State Analyzer to the its outputs and then to the CPU. 



PBSRS Positive Bus State Recognition Strobe -- a differential strobe (NBSRS) 
developed in the Strobe Generator, and sent to the Data Acquisition Boards. 
At the beginning of a data acquisition cycle, PBSRS goes from a low state 
to a high state. PBSRS is used to latch user information into the State 
Recognition Latches/Counters. 



SAC 8-37 



Model 6U62IA - Service 



Table 8-1. Mnemonics (Cont'd) 
Mnemonic Description 

PBSTBRQ Positive Bus Strobe Request -- a signal coming from the Data Acquisition 
Boards during Performance Verification only. PBSTBRQ when going from a low 
to a high state, begins a strobe generator cycle. PBSTBRQ is wire ORed 
with PPVSTB and HMCLK. 

PDC Positive Delayed Clock --an 1MB signal driven by the State Analyzer. PDC 

is a delayed version of HMCLK. Vftien enabled, PDC may be used by other 
Modules using the 1MB. 

PDSTB Positive Data Strobe -- a differential signal (NDSTB) developed in the 
Strobe Generator. PDSTB and NDSTB are used to develop HDVLD (see HDVLD) . 

PHALT Positive Halt -- PHALT goes from a low to a high state when Trace Point or 
Measurement Complete occurs, if enabled by the user. PHALT is used in the 
Preprocessor (if enabled) and becomes P0RT2. 

PIHALT Positive Interface Halt -- a differential signal (NIHALT) sent to the 
Preprocessor that can be used to halt the user's system. PIHALT is derived 
from PHALT when enabled by HENHLT. 

PISTIM Positive Interface Stimulus -- a differential signal (NISTIM) sent to the 
Preprocessor. PISTIM is developed from PSTIM when enabled by HENSTIM. 
PISTIM goes from a low to a high state when a Trigger Event or Sequence 
Event occurs if enabled by the user. 

PMACRS Positive Memory Address Counter Register Strobe -- a differential signal 
(NMACRS) developed in the Strobe Generator. PMACRS is used to latch infor- 
mation from the Trace Count /Status Memory Address Counter into the Trace 
Memory Address Counter Read Register. The information in the Register is 
transferred to the CPU Data Bus when LRMACR goes low. 

PORTl Port 1 -- a signal from the Card Cage to the Rear Panel Connector PORT 1. 

In the case of the State Analyzer Control Board, PORTl is used for Positive 
Stimulus (see PSTIM). 

P0RT2 Port 2 -- a signal from the Card Cage to the Rear Panel Connector PORT 2. 

In the case of the State Analyzer Control Board, P0RT2 is used for Positive 
Halt (see PHALT). 

PPLS Positive Pipeline Strobe -- same as NINCSS but inverted. When PPLS goes 
from a low to a high state, the Sequence Pipeline Latch/Counter is incre- 
mented one state when in the count mode. 

PPVSTB Positive Performance Verification Strobe -- PPVSTB is developed in the 
Write Decoders from the CPU. PPVSTB when going from a low state to a high 
state begins a strobe generator cycle. PPVSTB is used only during 
Performance Verification. PPVSTB is wire ORed with HMCLK and PBSTBRQ. 

PSOCINC Positive Sequence Occurrence Counter Increment -- developed from NOCSTB. 

When PSCINC goes from a low to a high, the Sequence Occurrence Coxinters 



SAC 8-38 



Model 6I462IA - Service 



Table 8-1. Mnemonics (Cont'd) 

Mnemonic Description 

will be incremented one state when in the count mode. PSOCINC may also be 
driven by HBOWRT, they are wire ORed. PSOCINC never drives HBOWRT. 

PSQRGS Positive Sequence Register Strobe -- a differential signal (NSQRGS) 
developed in the Strobe Generator. PSQRGS is used to latch information 
from the Sequence Pipeline Latch/Counters into the Sequence Read Register. 
The information in the Register is placed on the CPU Data Bus when LRSQRG 
goes low. 

PSTIM Positive Stimulus -- PSTIM goes from a low to a high state when a Trigger 
Event or a Sequence Event occurs if enabled by the user. PSTIM is used in 
the Preprocessor (if enabled), and also becomes PORTl. 

PWAC Positive Write Analysis Controller -- a CPU controlled signal developed in 
the Write Decoders. When the Analysis Controller is in the load mode (LLD 
low) , PWAC writes LDBO into the Controller. 

PWCLK Positive Write Clock -- a CPU controlled signal developed in the Write 
Decoders. PWCLK writes LDBO and LDBl into the Clock Term Generator. 

PWLOAD Positive Write Load -- a CPU controlled signal developed in the Write 
Decoders. When going from a low state to a high state, PWLOAD latches LABO 
into the Load Latch asserting or negating HLD and LLD. 

PWRUN Positive Write Run -- a CPU controlled signal developed in the Write 
Decoders. When going from a low state to a high state PWRUN latches LABO 
into the Run Latch producing LRUN and latches LABI into the Port Latches 
negating LTP and LMC. 

TSSO-7 Trace Sequence State 0-7 -- outputs of the Sequence State Latch/Counters 
used in either the load mode or the rvin mode. TSSO-7 represent the present 
sequence state. 

VTHSHl-2 Voltage, Threshold 1-2 a voltage that is programmable by the user emd 
sent to the Clock Probe as a reference voltage for the Comparators. 



SAC 8-39 



Model 6U62IA - Service 



Table 8-2. Schematic Diagram Notes 



I 1 



9 

I 

o 

^TPI 

V 

(D 3 



ETCHED CIRCUIT BOARD 



FRONT PANEL MARKING 



REAR-PANEL MARKING 



MANUAL CONTROL 



SCREWDRIVER ADJUSTMENT 



ELECTRICAL TEST POINT 
TP (WITH NUMBER) 



NUMBERED WAVEFORM 
NUMBER CORRESPONDS TO 
ELECTRICAL TEST POINT NO. 

LETTERED TEST POINT 
NO MEASUREMENT AID 
PROVIDED 



(925) 



IJP = 

P/O = 

NC = 

CW = 



WIRE COLORS ARE GIVEN 
BY NUMBERS IN PARENTHESES 
USING THE RESISTOR COLOR 
CODE 

I (925) IS WHT-RED-GRN 



0- BLACK 
1 - BROWN 
2- RED 

3 ORANGE 

4 - YELLOW 



GREEN 
BLUE 
VIOLET 

GRAY 
WHITE 



OPTIMUM VALUE SELECTED 
AT FACTORY, TYPICAL 
VALUE SHOWN; PART MAY 
HAVE BEEN OMITTED. 



UNLESS OTHERWISE INDICATED. 
RESISTANCE IN OHMS 
CAPACITANCE IN PICOFARADS 
INDUCTANCE IN MICROHENRIES 



MICROPROCESSOR 

PART OF 

NO CONNECTION 

CLOCKWISE END OF VARIABLE 

RESISTOR 



COMMON CONNECTIONS. ALL LIKE-DESIGNATED POINTS ARE CONNECTED. 



NUMBER ON WHITE BACKGROUND = OFF-PAGE CONNECTION. 

LARGE NUMBER ADJACENT = SERVICE SHEET NUMBER FOR OFF-PAGE CONNECTION. 



© 



CIRCLED LETTER = OFF-PAGE CONNECTION BETWEEN PAGES OF SAME SERVICE 
SHEET. 



INDICATES SINGLE SIGNAL LINE 



NUMBER OF LINES ON A BUS 



111) 



STD-20-09-81 



SAC 8-UO 



Table 8-3. Logic Symbology 



GENERAL 

All signals flow from left to right, relative to the symbol's orientation with inputs on the left side of the symbol, and 
outputs on the right side of the symbol (the symbol may be reversed if the dependency notation is a single term.) 

All dependency notation is read from left to right (relative to the symbol's orientation). 

An external state is the state of an input or output outside the logic symbol. 

An internal state is the state of an input or output inside the logic symbol. All internal states are True = High. 
SYMBOL CONSTRUCTION 

Some symbolsconsist of an outline or combination of outlines together with one or more qualifying symbols, and the 
representation of input and output lines. 



INPUTS >- 



"1: 





& 

U98 


















OUTPUTS 



Some have a common Control Block with an array of elements: 
CHIP 

FUNCTION 



COMMON 
CONTROL-»-< 

INPUTS 



ARRAY 
ELEMENTS 




INPUTS 



3 ^ 


7D [0] 


^ 14 


4 


13 


7D [1] 


5 


12 


7D [2] 


6 


11 


7D [3] 







CONTROL 
BLOCK 



COMMON 
OUTPUT 



DEPENDENCY 
NOTATION 

LEAST 

SIGNIFICANT 
ELEMENT 



OUTPUTS 



MOST 

SIGNIFICANT 
ELEMENT 



CONTROL BLOCK - All inputs and dependency notation affect the array elements directly. Common outputs are 
located in the control block. (Control blocks may be above or below the array elements.) 



ARRAY ELEMENTS -All array elements are controlled by the control block as a function of the dependency notation. 
Any array element is independent of all other array elements. Unless indicated, the least significant element is always 
closest to the control block. The array elements are arranged by binary weight. The weights are indicated by powers 
of 2 (shown in [ 1). 

' LS-04-0S-83 - 1 



Model 6U621A - Service 



Table 8-3. Logic Symbology (Cont'd) 



INPUTS - Inputs are located on the left side of the symbol and are affected by their dependency notation. 

Common control inputs are located in the control block and control the inputs/outputs to the array elements 
according to the dependency notation. 

Inputs to the array elements are located with the corresponding array element with the least significant element 
closest to the control block. 

OUTPUTS - Outputs are located on the right side of the symbol and are effected by their dependency notation. 
Common control outputs are located in the control block. 

Outputs of array elements are located in the corresponding array element with the least significant bit closest to 
the control block. 

CHIP FUNCTION - The labels for chip functions are defined, i.e., CTR - counter, MUX - multiplexer. 
DEPENDENCY NOTATION 

Dependency notation is always read from left to right relative to the symbol's orientation. 

Dependency notation indicates the relationship between inputs, outputs, or inputs and outputs. Signals having a 
common relationship will have a common number, i.e., C7 and 7D....C7 controls D. Dependency notation 
2,3,5,6+/1,C7 is read as when 2 and 3 and 5 and 6 are true, the input will cause the counter to increment by one 
count. ...or (/) the input (C7) will control the loading of the input value (7D) into the D flip-flops. 

The following types of dependencies are defined: 

a. AND (G), OR (V), and Negate (N) denote Boolean relationship between inputs and outputs in any 
combination. 

b. Interconnection (Z) indicates connections inside the symbol. 

c. Control (C) identifies a timing input or a clock input of a sequential element and indicates which inputs are 
controlled by it. 

d. Set (S) and Reset (R) specify the internal logic states (outputs) of an RS bistable element when the R or S 
input stands at its internal 1 state. 

e. Enable (EN) identifies an enable input and indicates which inputs and outputs are controlled by it (which 
outputs can be in their high impedance state). 

f. Mode(M) identifies an input that selects the mode of operation of an element and indicates the inputs and 
outputs depending on that mode. 



h. 



Address (A) identifies the address inputs. 

Transmission (X) identifies bi-directional inputs and outputs that are connected together when the 
transmission input is true. 



DEPENDENCY NOTATION SYMBOLS 



A Address (selects inputs/outputs) (indicates binary range) 

C Control (permits action) 

EN Enable (permits action) 

G AND (permits action) 

M Mode (selects action) 



N Negate (complements state) 

R Reset Input 

S Set Input 

V OR (permits action) 

Z Interconnection 

X Transmission LS-04-08-83 - 2 



Table 8-3. Logic Symbology (Cont'd) 



OTHER SYMBOLS 



n 


Analog Signal 




Inversion 


& 


AND 


0 


Negation 


}{ 


Bit Grouping 




Nonlogic Input/Output 


i — 


Buffer 




Open Circuit (external resistor) 


1 


Compare 




Open Circuit (external resistor) 


> 


Dynamic 


>1 


OR 


=1 


Exclusive OR 




Passive Pull Down (internal resistor) 


T. 


Hysteresis 




Passive Pull Up (internal resistor) 


? 


Interrogation 


n 


Postponed 




Internal Connection 




Shift Left (or up) 



— Shift Right (or down) 

/ Solidus (allows an input or output to have 
more than one function) 

V Three State 

, Causes notation and symbols to effect 
inputs/outputs in an AND relationship, and to 
occur in the order read from left to right. 

/ \ Used for factoring terms using algebraic 
^ ' techniques. 

[ ] Information not defined. 

<J> Logic symbol not defined due to complexity. 



BG Borrow Generate 

Bl Borrow Input 

BO Borrow Output 

BP Borrow Propagate 

CG Carry Generate 

CI Carry Input 



LABELS 

CO Carry Output 

CP Carry Propagate 

CT Content 

D Data Input 

E Extension (input or output) 

F Function 



J 
K 

P 
T 

+ 



J Input 
K Input 
Operand 
Transition 
Count Up 
Count Down 



MATH FUNCTIONS 



ALU 

COMP 

DIV 



Adder 

Arithmetic Logic Unit 
Comparator 
Divide By 
Equal To 



> Greater Than 

< Less Than 

CPG Look Ahead Carry Generator 

TT Multiplier 

P-Q Subtractor 



CHIP FUNCTIONS 



BCD Binary Coded Decimal 

BIN Binary 

BUF Buffer 

CTR Counter 

DEC Decimal 



DIR 

DMUX 

FF 

MUX 

OCT 



Directional 

Demultiplexer 

Flip-Flop 

Multiplexer 

Octal 



RAM Random Access Memory 

RCVR Line Receiver 

ROM Read Only Memory 

SEG Segment 

SRG Shift Register 



DELAY and MULTIVIBRATORS 



JUl Astable 
jioo iisj Delay 

in Nonretriggerable Monostable 



NV Nonvolatile 

I State of initial power up 
J L. Retriggerable Monostable 



LS-04-08-83 - 3 



SAC 8-m 



Model 6U62IA - Service 



/ 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



O 
Q 
< 



\7 \7 



o 
cc 
I- 
z 
o 
o 



PREPROCESSOR 
INTERFACE 
BUS 



(A 

o 
o 

_l 

o 



CM 

z 

(0 

z 

I- 
> 



w 

HI 

m 
o 
cc 
h- 

V} 



CLOCK 
PROBE 
INTERFACE 

TEST 3, 10 



HMCLK 



i 



/\ /\ /\ 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



7\ 



PSTIM/PHALT 



CONTROL 



ADDRESS 



DATA 



SEB 

TO/FROM ACQUISITION BOARDS 



Ui 

O 

z 

UJUJ 
31- 

o< 



(A 



2£ 



uiuj 



lUCC 

>> 
GO 
ffiffi 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



Oh- 5 

(OH ^ 
uj<0 
ceo. O 



SEQUENCER 



TEST 4 



STROBES 



CONTROL 
LINES ^ 



\7 



\ 



000 
OQ CDOQ 
ZZZ 



/ 



ANALYSIS 
CONTROLLER 

EST 2 



A 
V 



HWRT, HTIMS 



I 



TEST 8 



PDC 

LME 

LTE 

LSE 

HTR 



BNC 
CONTROL 

TEST 12 

/\ /\ /\ 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7^ 



20 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 



7\ 



Q 
—I 



UJ 

< 

cc 



CO 

I- 
cc 
o 

Q. 



N 
I 

Ui 
CM 



MAINFRAME INTERFACE TEST 1 




64621A STATE CONTROL 



Block Diagram 



Component Locator 



SAC 8-l»2 



TO/FROM CLOCK PROBE/PREPROCESSOR 




Model 6U62IA - Service 



ICS ON THIS SCHEMATIC 



REF. DES. 


HP PART NO. 


MFG. PART NO. 


U25 


INB4-5011 


INB4-5011 


U26 


1820-2075 


74LS245 


U28-29 


1826-0271 


S1\172741P 


U53 


1820-2024 


74LS244 


U54-55 


1826-0856 


AM6080APC 


U99 


1820-1197 


74LS0O 


U129 


1820-1173 


10124 



PARTS ON THIS SCHEMATIC 



012.36,37 

CR1,2 

J3 

R1 9-34,48.49,54-57 
TP11,12 

U10,1 1,25-30,35,53-55,99,128,129 
Wl 



POWER SUPPLY 
CONFIGURATION 



-t-5 — 


20| 




1^ U26,53 


J- 



-1-5- 



14l 



U99 



-1-5- 
-5- 



16 



U129 



-1-5 
-3.25 



25 

11.12.31,32 
9,10,33,34 



Vco 
Vee 
GND 



U25 



Figure 8-11. 
Probe/ Preprocessor Interface 

SAC 8-U3 



Model 6U62IA - Service 



/ 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



O 
Q 
< 



\7 \7 



o 
cc 
I- 
z 
o 
o 



PREPROCESSOR 
INTERFACE 
BUS 

TEST 11 



(A 

o 
o 

_l 

o 



CM 

z 

(0 

z 

I- 
> 



w 

HI 

m 
o 
cc 
h- 

V} 



CLOCK 
PROBE 
INTERFACE 



TEST 3, 10 

/\ /\ /\ 



HMCLK 



STROBE 
GENERATOR 
1, 9 



STROBES 



7\ 



PSTIM/PHALT 



CONTROL 



ADDRESS 



DATA 



SEB 

TO/FROM ACQUISITION BOARDS 



O 

z 

UJUJ 
31- 

o< 



(A 



2£ 



uiuj 



UJCC 

>> 
GO 
ffiffi 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



pi" 

Oh- 5 

(OH % 
uj<0 

CCQ. O 



SEQUENCER 



TEST 4 



STROBES 



CONTROL 
LINES ^ 



\ 



000 
OQ CDOQ 
ZZZ 



/ 



ANALYSIS 
CONTROLLER 

EST 2 



A 
V 



HWRT, HTIMS 



I 



TEST 8 



PDC 

LME 

LTE 

LSE 

HTR 



BNC 
CONTROL 

TEST 12 

/\ /\ /\ 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7^ 



20 k 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 



7\ 



Q 
—I 



UJ 

< 

cc 



CO 

I- 
cc 
o 

Q. 



N 
I 

m 

CM 



MAINFRAME INTERFACE TEST 1 



49 



— C3- 

R2 — 9 

R3 — □ 

□ 



T5 T4 T3 T2 T1 



US 



10 



64621-66501 

STATE CONTROL BOARD 
REV A 

CLOCK POD 



MP3 
+ FS1-fS +FS2 



-R9 — u 



U16 



U19 



-C14- 01 
— C15— Vy" 



U31 



aU44 U45 
y u 



TP13 U35 

-C20- □ ! • - 
U48 U49 U51 



-C11- Cli 

R20 — 

— R21 — 

Fl — R22 



I — R27— 
<e — R28 — 

£ — R29 — 
- R30 — 



TPII-^rRJl 
P 



U27 n I 
TP12LJ ' - 



-C30- -C31- -C32- -C33- -C34- Q GND _C35- 

-C29- 1 



-C36- -C37- 
— R34— -C38- 



J L 



-C41- -C42- -C43- -C44- 



3 C 



-C45- EI 



SA CLOCK 
U95 TP14 



-C39- 
R36- 



□ □ — R37— 



nan -C47- -C48- -C49- -C50- 



~R38— • — R39- 



-C53- — C54- 



—051- -052- 



-C58- 
-059- 



-C81- = 
-R50 — -062- 



055- □ R46 — -056 R47 -057 

GND 

□ F 



TP17 

□ 



TP18 

□ 



TP16 

□ 



u u u 



SA START/STOP 
53 59 69 79 83 85 

III I 



-R54— C64- 

:S||= C65- 

-R57 — 066- 



64621A STATE CONTROL 



Block Diagram 



Component Locator 



SAC 8-ltlt 



Model 6U62IA - Service 



P/O Al STATE ANALYSIS 
(64621-66503) 
STROBE GENERATOR 



CONTROL BOARD 



RIO 2K 
+5 ^AA 




J!MACRS_07 



PSORGS 0g 



240 ll 
-Wr»---3.25 

P/O 
U33 



_NSORGS_0g 



_LDVm^7 



_LSCLK_(^g 



_rL 

lOOMS 
±20!'. 

SLOW CLOCK 
DETECTOR 



2 



ICS ON THIS SCHEMATIC 



REF. DES. HP PART NO. MFG. PART NO 



U5,24.45 

U6, 19,20,44 

US 

U16 

U21,22 

U23 

U43 

U47,50 

U52,85 

U65 

U117 



1820-1400 
1820-0802 
1820-0269 
1820-1831 
1820-1944 
1820-0817 
1820-0806 
1820-0809 
1820-1173 
1820-1052 
1820-1423 



10104 

10102 

7403 

10103 

10130 

10131 

10109 

10115 

10124 

10125 

74LS123 



PARTS ON THIS SCHEMATIC 



05-10,17,31,33,62 
R4,5,7-1 8,36,52 
TP1, 2,8,9,1 3,1 5 

U2,4-6,8,9,1 2.1 3,1 6,1 9-24,31 -35,43-52,57,65,85,1 1 7 



POWER SUPPLY 
CONFIGURATION 



-5.2 




U5,6,16,19-24, 
43-45.47,50 



-1-5. 



-1-5- 



U52,65,86 



U8 



Figure 8-12. 
Strobe Generator 
SAC 8-i45 



Model 6U62IA - Service 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



O 
cc 
I- 
z 
o 
o 



PREPROCESSOR 
INTERFACE 
BUS 

TEST 11 



J 



o 
I 
(fl 

lU 

cc 
z 



to 

LU 

m 
o 
cc 
I- 

V) 



CLOCK 
PROBE 
INTERFACE 

TEST 3, 10 



HMCLK 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



7\ 



PSTIM/PHALT 



CONTROL 



ADDRESS 



DATA 



SEB 

TO/FROM ACQUISITION BOARDS 




UJ 

O 

z 

UJUJ 
31- 

o< 

UJl- 
(0(0 



(0 
UJCC 

>> 
00 
ffiffi 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



ico 



S=cc 
oh 

(OH- 
UJ< , ^ 

cca O 



SEQUENCER 



STROBES 



CONTROL 
LINES ^ 




\ 



O 
cc 
I- 
z 

Cm 



Oct 

000 
mm 

XXI 



/ 



ANALYSIS 
CONTROLLER 

TEST 2 



A 
V 



HWRT, HTIMS 



I 



TEST 8 



PDC 

LME 
LTE 
LSE 
HTR 



BNC 
CONTROL 

TEST 12 

Z\ /\ /\ 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7\ 



20 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 



UJ 

< 
cc 
u. 
z 

< 

Si 



(0 

I- 
cc 
o 

Q. 



N 

X 

s 

m 

CM 



MAINFRAME INTERFACE TEST 1 




64621A STATE CONTROL 



Block Diagraan 



Component Locator 



SAC 8-1*6 



Model 6U62IA - Service 



P/O Al STATE ANALYSIS CONTROL BOARD 
(64621-66503) SEQUENCER 




ICS ON THIS SCHEMATIC 



3 



REF. DES. HP PART NO. MFG. PART NO 



U6,19 

U17,18 

U36,38,40,42 

U52,85 

U85,83,84 



1820-0802 
1820-1718 
1816-1462 

1820-1 173 
1820-1052 



10102 
10016 
10422 
10124 
10122 



PARTS ON THIS SCHEMATIC 



R36 

U3,6,l 7-1 9,31 ,32,36-42,52,65,83-85 



POWER SUPPLY 
CONFIGURATION 



-1-5. 



16 



U52,65,83-85 



-5.2- 



16 



U6,17-19 



-5.2- 



12 



U36,38,40,42 



Figure 8-13. 
Sequencer 
SAC 8-U7 



Model 6U62IA - Service 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



O 
cc 
I- 
z 
o 
o 



PREPROCESSOR 
INTERFACE 
BUS 

TEST 11 



J 



04 

Z 
w 
z 
I- 
> 



o 
z 

V) 
Ui 

cc 
z 



(0 
UJ 
GO 

o 
cc 
I- 



CLOCK 
PROBE 
INTERFACE 

TEST 3, 10 



HMCLK 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



7^ 



PSTIM/PHALT 



SEB 

TO/FROM ACQUISITION BOARDS 



Ui 

O 

z 

UJUJ 
31- 

o< 

(n</) 



UJ<0 
(/>Q. U 



ZV) 
UJCC 

>> 
00 
mm 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



(OK- 2 
UJ< , ^ 
ceo. U 



SEQUENCER 



ST 4 



STROBES 



CONTROL 
LINES ^ 



CONTROL 



ADDRESS 



7^ 



\ 



00 

tro 



Cm 



000 
mm 
zzz 



/ 



ANALYSIS 
CONTROLLER 

TEST 2 



A 
V 



HWRT, HTIMS 



I 



TEST 8 



PDC 

LME 

LTE 

LSE 

HTR 



BNC 
CONTROL 

TEST 12 

/\ /\ 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7\ 



20 



> 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 



DATA 




UJ 

< 
CC 
u. 
z 

< 

Si 



I- 

QC 

o 

Q. 



N 

z 

S 

in 

CM 



MAINFRAME INTERFACE TEST 1 



MP1 
MP3 



IS I - I ran' 



T5 T4 T3 T2 T1 



-R3— □ 
□ 



64621-66501 

STATE CONTROL BOARD 
REV A 

CLOCK POD 



IT 



IT 



MP3 

+ FS1-FS+FS2 



R9 — o 



I 



—RIO- I 1 I I I I I I I I Y 



n It 



IV 



-C14- Q1 

— C15— v_y 



11 c 



TPI3 U35 
□ -C20- □ I ' - 



U48 U49 U51 



C11- -C12 

R20 — 

R21 — 

i^-,-R27- 

1 i — H30 — 

TP11 jR31 — 



' — R33 — 



Zl -C29- 



-C30- -C31- -C32- -C33- -C34- Q GND -CZS- 



-C36- -037- 
-R34— -C38- 



r 



-C41- -C42- -C43- -C44- 



aU79 U80 US1 US2 

i □ □ Li 



-039- 
-R36- 



3 □ R37 — -C 



-R38— — R39- 



— R41- 

_P40 -C47- -C48- -C49- -C50- 



-CS1- -C52- 



-R«— 



-C58 

_C59 — R50 — -C62- 

C60 



-CSS- □ R46 — -CSS R47 -057- 

GND 
□ 



-R48 — U130 
-R49- 



TP17 

□ 



TP18 

□ 



-063- 



TP16 

□ 



TP19 

□ 

SA START/STOP 
53 59 69 79 83 85 

Q 

d 



— R54 — 064- 

-^11- C65- 

— R57 — C66- 



64621A STATE CONTROL 



Block Diagram 



Component Locator 



SAC 8-1*8 



Model 6U62IA - Service 



P/0 Al STATE ANALYSIS CONTROL BOARD (64621-66503) 
SEQUENCE OCCURRENCE COUNTERS/MEMORIES 



LOWER 




PSOCINC 



LWOCMU 



LWOCML 



BSSO-3 



UPPER 



LSEQDO-7 



101)3 



MEMORY 

ECL 



BSSO 10 



. BSSl 


g 


. BSS2 


7 


. BSS3 


6 



LWOCML 



NC ■ 



13. 



1^ 




^ LSEQDO 



Gl 

IC [WRITE] 
lEN [READ] 

1 U61 I 



LEAST 

SIGNIFICANT 
COUNTER 

ECL 



NC 



12. 



^ LSEQDl 



s LSEBD2 



11 



LSEQD3 



12 



AD 


A 


AD 


A ^ 


AD 


A 0 


AD 


A 0 



2 

_1 

15 
14 



-3,25 ■ 



470 

(hVV\A- 

P/0 
U56 



TTL- 
ECL 



+5 — ^A/v- 

R36 
2K 




LDBO-7 



(O ^ in 



K> \ 



■ O ID 



10 



470 

-V\/Vii 

P/0 
U56 



--3.25 



LSOCLD 



13 



CTR DIV 16 
Gl 
R 

M2 
M3 
G4 
t>l, 2. 



CT-15 



4+/1, 3C5 

UB2 r 



7 
9 
10 
11 



5D 


[0] 






5D 


[11 




5D 


[2] 




5D 


[31 


<5 



15 



14 



-NC 
-NC 
-NC 
-NC 



-3.25 • 



470 

-AAAr- 

P/0 
U95 



MEMORY 

ECL 



BSSO 



10 



BSSl 



BSS2 



BSS3 



LWOCML 



NC ■ 



13 



RAM 16X4 



0 

15 



61 

IC [WRITE] 
lEN [READ! 



^ LSEQD4 
LSEQD5 



1 



U59 



COUNTER 

ECL 



NC 



12. 



LSEQD6 



LSEQD7 



11 



12 



AD 


A X> 


AD 


A 0 


AD 


A X> 


AD 


A ^ 



2 

i 

15 
14 



12-1 



13 



LSOCEN 



U80C <>/ 



-NC 



15 



oin 



> oin 



13 



CTR DIV 16 
81 
R 

M2 
M3 
64 
>1 



CT-15 



2. 4+/1. 3C5 

U79 r 



10 



5D 


[01 






5D 


[11 




5D 


[21 




5D 


[31 


0 



15 



14 



-NC 
-NC 
-NC 
-NC 



MEMORY 

ECL 



BSSO 



10 



^ BSSl 



BSS2 



BSS3 



LWOCMU 



NC • 



13 



BAM 16X4 



0 

15 



Gl 

IC [WRITE] 
lEN [READ] 

1 U60 



COUNTER 

ECL 



NC 



12. 



. LSEQDl 


4 


, LSEQD2 


11 


. LSEQD3 


12 



AD 


A 0 


AD 


A ^ 


AD 


A X> 


AD 


A 0 



2 

_1 

15 
14 



470 
P/0 

ug5 



-3.25 



CM (n in 



> 0(jD 

> Q.3 



10 ■ 



11 



ECL 
U80 
D 



14 



\ ECL 
UBO ^ 



13 



CTR 
61 
R 

M2 
M3 
G4 
>1 



DIV 16 



CT = 15 



2, 4+/1. 3C5 

U81 r 



10 



5D 


[01 






5D 


[11 




50 


[21 




5D 


[31 


0 



15 



14 



-NC 

-NC 
-NC 
-NC 



470 

P/0 
U95 



MEMORY 

ECL 



BSSO 



10 



BSSl 



BSS2 



BSS3 



LWOCMU 



NC 



13 



RAM 16X4 



0 

15 



61 

IC [WRITE] 
lEN [READ! 



LSEaD4 



1 



MOST 

SIGNIFICANT 
COUNTER 

ECL 



NC 



12. 



USB 



LSEQD5 



v_LSEQD5_ 



11 



LSEQD7 



12 



L 



AD 


A 0 


AD 


A 0 


AD 


A 0 


AD 


A 0 



cu CO -q- jn 



> oin 

> CLID 



ECL 
UBO 



POWER SUPPLY 
CONFIGURATION 



-52- 



16 



U16,78-82 



-H5- 
-5.2- 



16 



U63,64 



U58-61 



13 



CTR DIV 16 
Gl 



R 

M2 
M3 
64 
^1. 2. 



CT = 15 



4+/1. 3C5 

U7B r 



10 



11 



5D 


[0] 




5D 


[11 




5D 


[21 




5D 


[31 





15 



14 



-NC 

-NC 
-NC 
-NC 



-3.25 • 



470 
P/0 

ugs 



240 

P/0 
U31 



-3.25 



ECL 
U16 ^ 
B 



3 LOCCRY 



40 ) 3 



ICS ON THIS SCHEMATIC 



REF. DES. 



U16.80 
U58-61 
U63-64 
U78,79.81,82 



HP PART NO. MFG. PART NO. 



1820-1831 
1816-1338 
1820-1173 
1820-1788 



10103 
10145 
10124 
10016 



PARTS ON THIS SCHEMATIC 



R36 

U 1 6,31 ,41 ,56,58-61 ,63,64,75,76,78-82,95 



4 



Figure 8-14. 

Sequence Occurrence Counter / Memory 

SAC 8-1*9 



Model 6>t621A - Service 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



O 
cc 
I- 
z 
o 
o 



PREPROCESSOR 
INTERFACE 
BUS 

TEST 11 



J 



CM 

I 
w 
I 
I- 
> 



o 
I 
u> 

cc 
I 



(0 
UJ 
GO 
O 
CC 

I- 

V) 



CLOCK 
PROBE 
INTERFACE 

TEST 3, 10 



HMCLK 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



PSTIM/PHALT 



CONTROL 



ADDRESS 



DATA 



SEB 

TO/FROM ACQUISITION BOARDS 



Ui 

O 

z 

UJUJ 
31- 

o< 

W<0 



Ui 



iu<0 
(/)□. U 



ZO) 

ujtr 
>> 
oo 
mm 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



(OH e 

uj<0 

OCQ. U 



SEQUENCER 



TEST 4 



STROBES 



CONTROL 
LINES ^ 



\ 



Oct 

GOO 
OQ ODtD 
XXI 



/ 



ANALYSIS 
CONTROLLER 

TEST 2 J 
I 



V 



TEST 8 



,5 



PDC 

LME 

LTE 

LSE 

HTR 



HWRT, HTIMS 




TEST 12 

/\ /\ 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7\ 



20 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 



7\ 




111 

< 
cr 



< 
Si 



(0 

I- 
cc 
o 

Q. 



N 

X 

S 

in 

CM 



MAINFRAME INTERFACE TEST 1 



2 



— C3— 

R2 — 9 

R3— □ 

□ 



T5 T4 T3 T2 T1 



US 



10 



64621-66501 

STATE CONTROL BOARD 
REV A 

CLOCK POD 



IT 



MP3 
+ FS1-fS +FS2 



uial 

i 



-C14- 
-C15- 



01 



TP13 
□ -C20- □ I 



C11- Cli- 
R20 — 

— R21 — 
— R22 — 

I — R27 — 

J5— R28 — 
£ — R29— 
— R30— 



U2e 



TP 11 ^R31 

~n P 
U29 g 
^ , I cc ^ 

U27 n I ^ 
TP12'-I ' — 



-C30- -C31- -C32- -033- -C34- 



□ GND _c35- 



-C36- -C37- 
-R34— -C38- 



-041- -C42- -C43- -C44- 



-039- 
-R36- 



-045- EI 



□ □ — R37- 



— R38— • — R39- 



— R41 — 

-047- -048- -049- -C50- 

U111 



-051- -052- 



_nJJ -053- —054- 



-C58- 
-059- 



-CS1- =5U = 

-R50 — -062- 



^6 



TP15 

055- □ R46 — -056 R47 -057 

GND 

□ 



R48— U130 



U123 



U125 



TP17 

□ 



U126 



TP18 

□ 



TP16 

□ 



SA START/STOP 
53 59 69 79 83 65 



— R54— C64- 

— R55 — 
— R56 — 
— R57 — 066- 



-065- 



3i 



64621A STATE CONTROL 



Block Diagram 



Component Locator 



SAC 8-50 



Model 6U62IA - Service 



INTEHMQOULE BUS (1MB) 



SYNCHRONOUS EXPANSION BUS 



(SEB) 




-5.2- 



+5- 



ICs ON THIS SCHEMATIC 



REF. DES. HP PART NO. MFG. PART NO 



U1 

U5 

U6 

U14 

U16 

U18 

U97 

U116 

U123 

U126 



INB4-5010 
1820-1400 
1820-0802 
1820-1201 
1820-1831 
1820-1788 
1820-1282 
1820-1210 
1820-1195 
1820-0780 



INB4-5010 

10104 

10102 

74LS08 

10103 

10016 

74LS109 

74LS51 

74LS175 

AM8831 



PARTS ON THIS SCHEMATIC 



C15 
CR3 
J1,2 
Q1 

R1, 35,42,43,45 
TP3-5,7,8,10 

U1-7,12,13,14,15,16,18,31,41,97,1 18,123,128 



POWER SUPPLY 
CONFIGURATION 



U5,B,16,18 




161 

"Tl U97,123,126 



-1-5- 



141 



U116 



Figure 8-15. 
Analysis Controller 
SAC 8-51 



Model 6U62IA - Service 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



O 
O 
< 



o 

QC 
I- 
Z 

o 
o 



PREPROCESSOR 
INTERFACE 
BUS 

TEST 11 



1 



o 
o 

o 



CM 

I 

X 

w 

X 



o 

X 

(0 

cc 

X 



UJ 
00 

o 
cc 
f- 

V) 



CLOCK 
PROBE 
INTERFACE 

TEST 3, 10 

/\ /\ A 



HMCLK 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



PSTIM/PHALT 



CONTROL 



ADDRESS 



DATA 



SEB 

TO/FROM ACQUISITION BOARDS 



UJ 

U 

z 

UJUJ 
31- 

o< 

lUl- 



(AO. U 



I- 
zw 

UJOC 

>> 
00 
mm 

-IQ. 



1MB 

TO/FROM OTHER 
y BOARDS ^ 



tf) 



UJ<0 

oca U 



SEQUENCER 



TEST 4 



STROBES 



CONTROL 
LINES ^ 



ceo 



000 
m mm 

XXX 



/ 



ANALYSIS 
CONTROLLER 

TEST 2 



A 
V 



HWRT, HTIMS 



TEST 8 



.5 



PDC 

LME 

LTE 

LSE 

HTR 



BNC 
CONTROL 



TEST 12 



7\ 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 




20 k 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 



7^ 




lij 

< 

cc 

z 
< 
Si 



(0 

I- 
cc 
o 

Q. 



N 

X 

in 

CM 



MAINFRAME INTERFACE TEST 1 



19 



IS E 



— C3- 

R2 — 9 

R3— □ 

□ 



T5 T4 T3 T2 T1 



U8 



10 



64621-66501 

STATE CONTROL BOARD 
REV A 

CLOCK POD 



IT 



MPS 

+ FS1-FS+FS2 



IT OC 

U19 I I 



I I I I I I ? V 1 1 

cc 

I 



ootc 

.1 I I 



-014- Q1 
— C15— W 



TP13 U35 
□ -C20- □ \ » - 



U41 



U48 U49 U51 



Oil- ■012- 
R20 — 

— R21 — 

— R22 — 



-R27 — 
-R28 — 
-R29 — 
-R30 — 



TP11 ^R31 



U27 n I 
TP12I-J ' - 



n -^29- 



-C30- -C31- -032- -033- -034- □ GND _C35- 



-036- -037- 
— R34— -C3B- 



-041- -042- -043- -044- 



□ EI 



-C4S- ^ 



SA CLOOK 
U95 TP14 



□ □ — R37— 



D40 -047- -048- -049- -O50- 



-R38 R39- 



-053- —054- 



-051- -052- 



-058- 
-059- 



-CS1- =«U = 

-R50 — -C62- 



— CSS- □ R46 — -C56- R47 — -057 

GND 
□ 



-R48 — IM30 
-R49 



TP17 

□ 



TP18 

□ 



TP16 

□ 



TP,9 

SA START/STOP 
53 59 69 79 83 85 



-R54— C64- 

C65- 

-R57 — C66- 



64621A STATE CONTROL 



Block Diagram 



Component Locator 



SAC 8-52 



Model 6U62IA - Service 



P/O Al STATE ANALYSIS CONTROL BOARD (64621-66503) 
TRACE STATE/TIME COUNTER 




240 
-^AAr- 
P/0 
U13 



TRACE STATE/TIME COUNTER 



ECL A 
U45 " 



47 

-V\Ar- 
P/0 
U57 




0 



L25MHZ 13 



I U127 \»1 »" 
12 ] D 



I H^'^ 

ECL tC] 
U129 y 15 



^^-'^N25MHZ 
34 



>Pa5MHZ 
HOV 



5 0H5SIL. 



ECL-TTL 


5 LSFLGB 


> 


t> 


12 HCQB 


> 


13 HOTFB 


> 


1 


U74 
VBB 





U112 
ECL 



LTBACE 
>PSET 

■PLATCH 

HTIME 
LSTATE 

HLOAQ 

HCE 

LQE 



LSFLGB. HCQB, HDTFB 



€)' 



16 



(D 1^ in ^ 



(D in n 



n (n c\j in 



38 



V 



V 



V 



V 



V 



V 



rv m 
1^ CD 
3 > 



V 



V 



V 



V 



V 



V 



V 



V 



.16 



V 



V 



V 



55)7 



6 



ICS ON THIS SCHEMATIC 



REF. DES. 


HP PART NO. 


MFG. PART NO. 


U20 


1820-0802 


10102 


U45 


1820-1400 


10104 


U74,77.94. 






108.109,110 


1820-1052 


10125 


U127 


1920-1208 


74LS32 


U129 


1820-1173 


10124 



PARTS ON THIS SCHEMATIC 



U1 3,20,35,45,57,74,77,94,1 08-1 1 3.1 27-1 30 



POWER SUPPLY 
CONFIGURATION 



-5.2- 



U20,45 



-1-5- 
-5. 



16 



074,77.94, 
108-110,129 



-1-5. 
-3.25- 



10.31 



11.28,29. 



Vcc 

Vee U112 
GND 



4-5- 



14 



U127 



Figure 8-16. 
Trace State/Time Counter 
SAC 8-53 



Hodel 6I462IA - Service 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



O 
cc 

z 
o 
o 



PREPROCESSOR 
INTERFACE 
BUS 

TEST 11 



1 



1 1 



I 

w 
I 
I- 
> 



o 
I 

u> 

cc 
I 



(0 
UJ 
GO 
O 
CC 

I- 

V) 



CLOCK 
PROBE 
INTERFACE 

TEST 3, 10 



HMCLK 



/\ /\ /\ 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



7^ 



PSTIM/PHALT 



CONTROL 



ADDRESS 



DATA 



SEB 

TO/FROM ACQUISITION BOARDS 



Ui 

O 

z 

UJlij 
31- 

a< 

lUl- 

(/)(/> 



Ui 



UJ<0 
(/>Q. O 



ZV) 
UJCC 

>> 
00 
mm 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



z 



OF!- 



0)1- 

iu< 

CCD. U 



SEQUENCER 



TEST 4 



STROBES 



CONTROL 
LINES ^ 



\ 



Cm 



Oat 

000 
mm 

XXX 



ANALYSIS 
CONTROLLER 

TEST 2 



V 



HWRT, HTIMS 



I 



TEST 8 



,5 



PDC 

LME 

LTE 

LSE 

HTR 



BNC 
CONTROL 

TEST 12 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7\ 



20 



2: 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 



7\ 




UJ 

< 

CC 

u. 
z 

< 

Si 



I- 

oc 
o 

Q. 



N 

X 

S 

in 

CM 



MAINFRAME INTERFACE TEST 1 



MP1 
MP3 



T5T4 T3 T2 T1 



-R2 9 

-R3— □ 

□ 



64621-66501 

STATE CONTROL BOARD 
REV A 

CLOCK POD 



MP3 
< FS1-FS 'FS2 



R9 — o 

—RIO- I I I 



n It 



IV 
I 'J. I 



-014- 01 

—015— v_y 

U37i 



mi -C20- □ 



TP13 U35 



U48 U49 U51 



Oil- -012 

R20 — 

R21 — 

"22 — 

I — R27 — 

«, — R28 — 
S — R29 — 
— R30 — 



U28 



TP11 ^R31 

P 



:2 -029- 



-O30- -031- -032- -033- -034- □ GND ^C3S~ 

IK7 IT 1 



-036- -037- 
-R34— -038- 



U60 1 U61 



u u u 



U76 

□ I. I 



-041- -042- -043- -044- 



-039- 
-R36 — 



SA OLOCK 
U95 TP14 



3 □ R37 — -046- 



-R38— — R39- 



— R41- 

_P40 -047- -048- -049- -O50- 



Q U97 Q 



-051- -052- 



-R«— -C53 054- 






U115 U116 



-058 

-C59 — R50 — -062- 

O60 



-055- □ R46 — -056 R47 -057- 

GND 

r. iD 



-R48 — U130 
-R49- 



n 



TP17 

□ 



TP18 

□ 



TP16 

□ 



TP19 

SA START/STOP 
53 59 69 79 83 85 



-R54— 064- 

Z^ll' C65- 

-R57 — 066- 



64621A STATE CONTROL 



Block Diagram 



Component Locator 



SAC 8-5U 



Model 6U62IA - Service 



P/0 Al STATE ANALYSIS CONTROL BOARD (64621-66503) 
TRACE COUNT/STATUS MEMORY 




R41 2K 
+5 — 



LSFL6B. HCQB. HOTFB 



LTCSMSO 



V 



CNTO 



CNT3 



,8 TRACE COUNT/STATUS MEMORIES 



19 



RAM 

256 X 

0' 
1 
2 
3 

4>A 
5 
6 
7 



0 
255 



Gl 

(WRITE) 
(READ) 



A, 2, 1 A, 3. IV 



A, 2, 1 A. 3, IV 



A. 2, 1 A. 3, IV 



A. 2. 1 A. 3. IV 



10 CDO 



12 CDl 



14 CD2 



16 CD3 



+5 



LTCSMSO 



17 



V 



RAM 
256 X 



0 
255 



8.--G1 



G2 (WRITE) 

G3 (READ) 
EN 

~1 U71 



CNT5 



CNT6 



13 



15 



A. 2, 1 A, 3. IV 



A, 2. 1 A, 3, IV 



A, 2, 1 A. 3. IV 



A, 2. 1 A, 3, IV 



10 CD4 



12 CD5 



14 CD6 



16 CD7 



LTCSMSl 



V 



CNT8 



21 



17 



18 



RAH 

256 X 



0 
255 



8,--Gl 



G2 (WRITE) 

G3 (READ) 
EN 

\^ U92 F 



11 



13 



15 



A. 3. IV 



A, 2. 1 

A. 2. 1 .. 

A. 2. 1 A. 3. IV 



A, 3. IV 



A. 2. 1 



A. 3, IV 



CDO 



CDl 



14 CD2 ^ 



16 CD3 



+5 



17 



20 



V 



RAM 
256 X 



0 
255 



(WRITE) 
(READ) 



CNT14 



13 



CNT15 



15 



A. 2, 1 A, 3. IV 



A, 2. 1 A, 3. IV 



A, 2. 1 A. 3, IV 



A, 2, 1 A, 3, IV 



10 CD4 



12 CDS 



14 CD6 



16 CD7 



LTCSMS2 



V 
CNT16 



21 



20 



RAH 

256 X 



0 
255 



&--G1 



G2 (WRITE) 
G3 (READ) 
EN 



U93 



11 



13 



15 



A, 2. 1 A, 3. IV 



A. 2. 1 
A. 2. 1 



A. 3, IV 



A. 3. IV 



A. 2. 1 A. 3, IV 



10 CDO 



12 CDl 



14 CD2 ^ 



16 CD3 ^ 



20 



V 



RAM 
256 X 



0 
255 



G3 



(WRITE) 
(READ) 



U73 



HCQB 



HOTFB 



15 



A. 2. 1 A. 3. IV 



A. 2. 1 A. 3, IV 



A, 2, 1 A, 3. IV 



A. 2, 1 A, 3, IV 



10 CD4 



12 CD5 



14 CD6 



16 CD7 



TSS2 



TSS3 



V 



BAM 
256 X 



0 
255 



G3 
EN 



(WRITE) 
(READ) 



13 



15 



A. 2, 1 A, 3. IV 



A. 2, 1 A, 3, IV 



A. 2, 1 A. 3. IV 



A. 2, 1 A, 3. IV 



10 CDO 



12 CDl 



14 CD2 



16 CD3 



19 



t5 



LTCSMS3 



V 



RAM 

256 X 



0 
255 



G2 
G3 
H EN 



(WRITE) 
(READ) 



U70 



TSS5 



A. 2. 1 A. 3. IV 



A, 2. 1 A, 3, IV 



A. 2. 1 A. 3, IV 



A. 2, 1 A, 3. IV 



10 CD4 



12 CDS 



16 CD7 



LDBO-7 



8 (b3 



jLCLR 



UB 



R9 2K 
+5 — WV— 



LBCLR 



59 )5 



ICS ON THIS SCHEMATIC 



REF. DES. 



U8 
U66 

U67,68,86 
U70-73 
90-93 
U87,88 
U96 

U98,103 
Ul 04,1 05 



HP PART NO. 



18200269 
1820-1052 
1820-1997 

1816-1308 
1820-1428 
1820-1197 
1820-1282 
1820-1430 



MFG. PART NO. 



7403 

10125 

74LS374 

93LS422 

74LS158 

74LS00 

74LS109 

744LS161 



PARTS ON THIS SCHEMATIC 



R39,41,46 

U8,66-68,70-73,86-88,9D-93,96,98,103-105 



POWER SUPPLY 
CONFIGURATION 



-1-5 ■ 



14 



U8,96 



+5- 



20 



10 



U67,68,86 



+5. 



221 



"gl U70-73,90-93 



+5 16j U87,88,98, 

8| 103-105 

^ ' 



+5- 
-5.2- 



16 



U86 



7 



Figure 8-17. 
Trace Count /Status Memory 
SAC 8-55 



Model 6U62IA - Service 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



o 
cc 
I- 
z 
o 
o 



PREPROCESSOR 
INTERFACE 
BUS 



TEST 11 



T 



04 
I 

X 

w 
I 
I- 
> 



o 

X 

(A 
liJ 
oc 
z 



(0 
UJ 
GO 
O 
CC 

I- 

V) 



CLOCK 
PROBE 
INTERFACE 

TEST 3, 10 



HMCLK 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



PSTIM/PHALT 



CONTROL 



ADDRESS 



DATA 



SEB 

TO/FROM ACQUISITION BOARDS 



UJ 

O 

z 

UJUJ 
31- 

o< 



UJ 



OCCE 



S28 



I- 
zco 

UJCC 

>> 
00 
com 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



00 



2*" j- 

(OH- ? 
Uj<0 
CCQ. O 



SEQUENCER 
TEST 4 



STROBES 



CONTROL 
LINES ^ 



\ 



occc 
000 

CO CDDQ 
XXI 



/ 



ANALYSIS 
CONTROLLER 

TEST 2 
I 



A 
V 



HWRT, HTIMS 



I 



7T7\ 



TEST 8 



,5 



PDC 

LME 

LTE 

LSE 

HTR 



BNC 
CONTROL 



TEST 12 

/\ /\ 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7\ 



20 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 




UJ 

< 

cc 



< 
Si 



(0 

I- 
oc 
o 

Q. 



N 

X 



MAINFRAME INTERFACE TEST 1 



19 



i I □ Di nn^P^ n« 



— C3— 

R2 — 9 

R3— □ 

□ 



T5 T4 T3 T2 T1 



64621-66501 

STATE CONTROL BOARD 
REV A 

CLOCK POD 



IT 



IT 



MP3 
+ FS1^S +FS2 



R9 — u S 00 

— RIO— I 1 



(L ' i , U11 



UUIE 
.1 I I 



-C14- Q1 _ 

-CIS- ^ ^ 



□ c 



TP13 U35 
13 -C20- □ I ' - 



U48 U49 U51 



-C11- -C12 
R20 — 

— R21 — 

— R22 — 



I — R27— 

U29I S=g||= 

. — R30 — 
TP11^^^:R31— 
-■ 

U29 » U30 



""TP12n I -R33- 



.C28- U56 5 



-C30- -C31- -C32- -C33- -C34- Q GND 

N57 U I 



-C36- -C37- 
— R34— -C38- 



-C41- -C42- -C43- -C44- 



-C39- 

-R36 — 



SA CLOCK 
U95 TP14 



□ □ — R37- 



-R38— — R39- 



— R41 — 

-C47- -C48- -C49- -C50- 

U111 



y y g I g I 



-C53- — C54— 



-C51- -C52- 



TP15 



IBBRR 

— -C61- -sv,- HI H 



-CSS- □ — R46 — -C56 R47 -C57 

GND 

-1 r- — \0 



-R48— Uyo 
-R49- 



U123 



— R51 — 
-R52- 

-C59 R50 — -C62- 



Q Q U126,p,,2 

TP17 I 1 



TP19 — C63— 



TP16 

35 □ 



_R54— C64- 

z^d- — 

-R57— 066- 



i 



64621A STATE CONTROL 



Block Diagraon 



Component Locator 



SAC 8-56 



Model 6U62IA - Service 




ICS ON THIS SCHEMATIC 



REF. DES. 


HP PART NO. 


MFG. PART NO. 


U62 


1820-1173 


10124 


U96,99 


1820-1197 


74LS00 


U98,103 


1820-1282 


74LS109 


U101,102 


1820-1216 


74LS138 


U106 


1820-1281 


74LS139 


U115 


1820-1199 


74LS04 


U117 


1820-1423 


74LS123 


U118,119 


1820-2102 


74LS373 


U120 


1820-1997 


74LS374 


U121 


1820-2075 


74LS245 


U124 


1820-0269 


7403 


U125 


1820-1 144 


74LS02 


U127 


1820-1208 


74LS32 



PARTS ON THIS SCHEMATIC 



CI -4,1 1,13,14,16,18-30,32,34,35,38-59.61.63,85-87 

PI 

R36,38,39,43,44,50,51 
TP17.18 

U37,41, 62,75,76,96,98,99,1 01 -103,1 06, 
1 15,117-121,124,125,127 



POWER SUPPLY 
CONFIGURATION 




U62 



-i-t; 


14 


U96,99,115, 


7 


124,125,127 



+5- 



161 



U98,101-103, 
106,107 




U118-121 



TO/FROM MAINFRAME 



Figure 8-18. 
Mainframe Write Interface 
SAC 8-57 



Model 6U62IA - Service 



TO/FROM 
CLOCK PROBE/ 
PREPROCESSOR 



\7 \/ 



O 
cc 
I- 
z 
o 
o 



PREPROCESSOR 
INTERFACE 
BUS 

TEST 11 



J 



/ 1 



Z 

w 

X 

I- 
> 



o 

X 

(A 
liJ 
CC 
X 



(0 
UJ 
GO 
O 

cr 
I- 

V) 



CLOCK 
PROBE 
INTERFACE 

TEST 3, 10 



HMCLK 



imTT> 



STROBE 
GENERATOR 
TEST 1, 9 



STROBES 



PSTIM/PHALT 



CONTROL 



ADDRESS 



DATA 



SEB 

TO/FROM ACQUISITION BOARDS 



UJ 

O 

z 

UJUJ 

a< 

lUl- 
W<0 



uj<0 

(/>Q. U 



ZV) 
UJCC 

>> 
GO 
mm 

Q. 



1MB 

TO/FROM OTHER 
BOARDS- 



(Oh- 2 

UJ< , ^ 
ceo. U 



SEQUENCER 



TEST 4 



STROBES 



CONTROL 
LINES ^ 



\ 



00 
ecu 



Cm 



ttoc 

000 
mm 

XXX 



/ 



ANALYSIS 
CONTROLLER 

TEST 2 



A 
V 



HWRT, HTIMS 



I 



TEST 8 



PDC 

LME 

LTE 

LSE 

HTR 



BNC 
CONTROL 

TEST 12 



HQWRITE,HWQ 



TSSO-7 



TRACE 
STATE/TIME 
COUNTER 
TEST 5, 7 



7\ 



20 



> 



1 



TRACE 
COUNT/STATUS 
MEMORY 
TEST 6 




19 



i I □ □! n^^D* n« 



— C3— 
R2 — 9 

— R3— □ 

□ 



TS T4 T3 T2 T1 



64621-66501 

STATE CONTROL BOARD 
REV A 

CLOCK POD 



IT 



MP3 

FS1-FS +FS2 



— R10- 1 1 I I I I I I I Y V 



OUIE 
.1 I I 



-C14- Q1 _ 

-CIS- ^ ^ 



TP13 U35 

3 -C20- □ 



U48 U49 U51 



-C11- -C12 
R20 — 

— R21 — 
R22 — 



— H2r— 

— R28— 
■R29- 
■R30- 



TP11 ^R31 — 

Pr 



""TP12n I -R33- 



.C28- uses 



-C30- -C31- -C32- -C33- -C34- Q GND -C35- 

N57 U I 



-C36- -C37- 
— R34— -C38- 



u 




-C41- -C42- -C43- -044- 



3 C 



-039- 
-R36- 



SA CLOCK 
U95 TP14 



□ □ — R37- 



-R38— — R39- 



U103 U104 U10S 



— R41 — 

-047- -C48- -C49- -C50- 

U111 



-053- —054— 



-051- -C52- 



-058- 
-059- 



-cei- -",11= 

R50 — -C62- 




TP16 

35 □ 



SA START/STOP 
53 59 69 79 83 85 



-R54— 064- 

-R55 — 
-R56 — 
-R57 — 066- 



-065- 



64621A STATE CONTROL 



Block Diagram 



Component Locator 



SAC 8-58 



Model 6U62IA - Service 



P/O Al STATE ANALYSIS CONTROL BOARD (64621-66503) 
MAINFRAME READ INTERFACE 



;r37 

»2K 




CPU READ 
DECODER 



LAB8 
< LAB9 



8 (61 



LABB-10 



UWP3 ^ 

' LABIO 3~ 
/ 



i -- 



OMUX 
■EN 



\PDSTB 


3 


S NDSTB 







\CD0-7 




\PSQRGS 


7 


\NSQRGS 








3 (27 

7 (sB 

7 (s^^ 
5 (46 

2 (^2 

8 (eg 
1 (1 



NMC 



LSCLK 



TRACE DATA READ 
^""""TER 



\ 
\ 


CDl 


17 


s 


CD2 


14 


\ 


CD3 


13 


\ 


CD4 


8 


\ 


CDS 


7 




CD6 


4 




CD7 


3 



19 
16 



15 



12 



LDBO . 
LDBl ^ 
LDB2 ^ 



LDB3 \ 



9 LDB4~^ 



6 LDB5~) 
~^ I nBR ^ 



LDB6 ) 
t nB7 ^ 



SEQUENCE READ 
REGISTER 



LDB7 ^ 



LRSaRG 1 t\ 
11 



' TSS4 a 



TSSO 
TSSl 



IB 
17 



D-FF 
EN 

->c 

i 



UB9 



TSS2 14 



T5S3 13 



' T5S5 7 
/ : — 



* " TSS6 



I 1 

' TSS7 3 



1^ 



19 



16 



LDBO 
LDBl 



15 LDB2 



12 LDB3 



LDB4 



LDB5 



LDB6 



LDB7 



ANALYSIS 

STATUS BUFFER 



l-i2-fc>JT EN2 



HDVLD 



1 
8 

8 (60 





> 


1 


7 






XT 


> 


1 


V 


U 


> 


1 


V 


XT 


> 


1 


V 


JT 


> 


2 


V 


n 


> 


2 


V 


JT 


> 


2 


7 


JT 


> 


2 


7 



18 


LDBO 




16 


LDBl 


/ 


14 


LDB2 


/ 


12 


LDB3 


/ 


9 


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ICS ON THIS SCHEMATIC 



REF. DES. 


HP PART NO. 


MFG. PART NO. 


U65,66 


1820-1052 


10125 


U69,89 


1820-1997 


74LS374 


U100 


1820-1216 


74LS138 


U106 


1820-1281 


74LS139 


U107 


1820-1282 


74LS109 


U122 


1820-2024 


74LS244 



PARTS ON THIS SCHEMATIC 



R3 7,40,47 

U65,86,89,89,100,106,107,122 



POWER SUPPLY 
CONFIGURATION 



+6 


20| 


10 U69,89,122 





+5- 



U100,106,107 



+5. 
-5.2- 



U65,66 



9 



Figure 8-19. 
Mainframe Read Interface 
SAC 8-59 



SALES & SUPPORT OFFICES 

Arranged alphabetically by country 



Product Line Sales/Support Key 

Key Product Line 

A Analytical 

CM Components 

C Computer Systems 

E Electronic Instruments t Measurement Systems 

M Medical Products 

P Personal Computation Products 

* Sales only tor specific product line 

" Support only for specific product line 

IMPORT ANT:These symlwls designate general product line 
capability.Tliey do not insure sales or support availability for all 
products within a line, at all locations-Contact your local sales 
office for information regarding locations where HP support is 
available for specific products. 

HEADQUARTERS OFFICES 

H there is no sales office listed for your area, contact one of these 
headquarters offices. 



NORTH/CENTRAL AFRICA 

Hewlett-Packard S.A. 

7, rue du Bois-du-Lar> 

CH-12t7 MEYRIN t, Switzerland 

Tel: (022) 83 12 12 

Telex: 27835 hmea 

Cable: HEWPACKSA Geneve 

ASIA 

Hewlett-Packard Asia Ltd. 
47/F, 26 Harbour Rd., 
Wanctial, HONG KONG 
G.PO. Box 863, Hong Kong 
Tel: 5-8330833 
Telex; 76793 HPA HX 
Cable: HPASIAL TD 

CANADA 

Hewlett-Packard (Canada) Ltd. 
6877 Goreway Drive 
MISSIS8AUGA, Ontario L4V 1M8 
Tel: (416) 678-9430 
Telex: 610-492-4246 

EASTERN EUROPE 

Hewlett-Packard Ges.m.b.ti. 
Lieblgasse 1 
P.O.Box 72 

A-1222 VENNA, Austria 
Tel: (222) 2500^1 
Telex: 1 3 4425 HEPA A 

NORTHERN EUROPE 

Hewlett-Packard S.A. 
Uilenstede 475 
P.O.Box 999 

NL-1183AGAM8TELVEEN 

The Nettierlands 
Tel: 20 437771 
Telex: 18 919 hpner nl 

SOUTH EAST EUROPE 

Hewlett-Packard S.A. 

World Trade Center 

110 Avenue Louis Casai 

1215 Cointrin, GENEVA, Switzerland 

Tel: (022) 98 96 51 

Telex: 27225 tipser 



MEDITERRANEAN AND 
MIDDLE EAST 

Hewlett-Packard S.A. 
Mediterranean and Middle East 
Operations 
Atrina Centre 
32 Kitissias Ave 

Paradissos-Amarousion, ATHENS 
Greece 

Tel: 682 88 11 

Telex: 21-6588 HPAT GR 

Cable: HEWPACKSA Attiens 

UNITED KINGDOM 

Hewlett-Packard Ltd. 
Nine Mile Ride 

Easthampstead. WOKINGHAM 
Berkshire. IRGII 3LL 
Tel: 0344 773100 
Telex: 848805 

EASTERN USA 

Hewlett-Packard Co. 
4 Choke Cherry Road 
ROCKVILLE,MD 20850 
Tel: (301) 268-2000 

MIDWESTERN USA 

Hewlett-Packard Co. 
5201 TdMew Drive 
ROLLING MEADOWS, IL 60008 
Tel: (312) 255-9800 

SOUTHERN USA 

Hewlett-Packard Co. 
2000 South Park Place 
P.O. Box 105005 
ATLANTA, QA 30348 
Tel: (404) 955-1500 

WESTERN USA 

Hewlett-Packard Co. 
3939 Lankershim Blvd. 
P.O. Box 3919 
LOS ANGELES, CA91604 
Tel: (213) 506-3700 



OTHER INTERNATIONAL 
AREAS 

Hewlett-Packard Co. 
Intercontinental Headquarters 
3495 Deer Creek Road 
PALO ALTO, CA 94304 
Tel: (415) 857-1501 
Telex: 034-8300 
Cable: HEWPACK 



ANGOLA 

Telectra Angola LDA 

Empresa Tecnica de Equlpamentos 

Rua Conselheiro Julio de Vilhema, 16 

Caixa Postal 6487 

LUANDA 

Tel: 35';i5,35516 
Telex: 3134 
E,C* 

ARGENTINA 

Hewlett-Packard Argentina S.A. 

Montaneses 2140/50 

1428 BUENOS ARES 

Tel: 783-4886/4836/4730 

Gable: HEWPACKARG 

A,C,CM,E,P 

Biotron S.A.C.I.e.l. 

Av. Paso Colon 221, PIso 9 

1399 BUENOS AMES 

CM 

Laboratorlo Rodriguez 

Corswant S.R.L. 

Misiones, 1156 - 1876 

Bernal, Oeste 

BUENOS AMES 

Tel: 252-3958, 252-4991 

A 

Argentina Esanco S.R.L. 

Avasco 2328 

1416 BUENOS AMES 

Tel: 541-58-1981, 541-59-2767 

A 



AUSTRALIA 

Adelaide, South Auairalla 
Office 

Hewlett-Packard Australia Ltd. 
153 Greenhill Road 
PARKSIDE,S.A.5063 
Tel: 272-5911 
Telex: 82536 

Cable: HEWPARD Adelaide 
A',C,CM,E.M,P 

Brisbane, Queenaland 
Office 

Hewlett-Packard Australia Ltd. 

10 Payne Road 

THE GAP, Queensland 4061 

Tel: 30-4133 
Telex: 42133 

Cable: HEWPARD Brisbane 
A,C,CM,E,M,P 



Canberra, Australia 
Capital Territory 
Office 

Hewlett-Packard Australia Ltd. 
121 Wollongong Street 
FYSHWICK,A.C.T 2609 
Tel: 80 4244 
Telex: 62650 

Cable; HEWPARD Canberra 
C,CM,E,P 

Melbourne, Victoria 
Office 

Hewlett-Packard Australia Ltd. 
31-41 Joseph Street 
BLACKBURN, Victoria 3130 
Tel: 896-2895 
Telex; 31-024 

Cable: HEWPARD Melbourne 
A,C,CM,E,M,P 

Perth, Western Australia 
Office 

Hewlett-Packard Australia Ltd. 
261 Stirling Highway 
CLAREMONT,W.A.6010 

Tel; 383-2168 
Telex; 93859 
Cable; HEWPARD Perth 
A,C,CM,E,M,P 

Sydney, New South 
Wales Office 

Hewlett-Packard Australia Ltd. 
17-23 Talavera Road 
P.O. Box 308 
NORTHRYDE,N.S.W.2113 
Tel: 888-4444 
Telex: 21561 

Cable: HEWPARD Sydney 
A,C,CM,E,M,P 

AUSTRIA 

Hewlett-Packard Ges.m.b.h. 

VerkaulsbOro Graz 

Grottenhofstrasse 94 

A-8052 GRAZ 

Tel: (0316) 291 56 60 

Telex: 32375 

C,E 

Hewlett-Packard Ges.m.b.h. 

Lieblgasse 1 

P.O. Box 72 

A-1222 VIENNA 

Tel: (0222) 2500-0 

Telex: 134425 HEPA A 

A,C,CM,E,M,P 

BAHRAIN 

Green Salon 
P.O. Box 557 
MANAMA 

Tel: 255503-265950 

Telex: 8441 

P 

Wael Pharmacy 
P.O. Box 648 
MANAMA 

Tel: 256123 

Telex: 8550 WAEL BN 

E,M 

ZayanI Computer Systems 
218 Shalk Mubarak Building 
Government Avenue 
P.O. Box 5918 
MANAMA 
Tel: 276278 
Telex: 9015 
P 



BELGIUM 

Hewlett-Packard Belgium S.A./N.V. 

Blvd de la Woluwe, 100 

Woluwedal 

B-1200 BRUSSELS 

Tel; (02) 762-32-(fc 

Telex: 23-494 paloben bru 

A,C,CM.E,M,P 

BERMUDA 

Applied Computer Technologies 
Atlantic House Building 
Par-La-Ville Road 
Hamilton 5 
Tel: 295-1616 
P 

BRAZIL 

Hewlett-Packard do Brasil 
I.e.G. ltda. 

Alameda Rio Negro, 750 
Alphaville 

06400 BARUERI SP 

Tel: (011)421.1311 

Telex: (01 1) 33872 HPBR-BR 

Cable: HEWPACK Sao Paulo 

A,C,CM,E,M,P 

Hewlett-Packard do Brasil 
I.e.C. Ltda. 

Praia de Botafago 228 

6° Andar-conj 614 

Edificio Argentina - Ala A 

22250 RK> DE JANEMO 

Tel: (021) 552-6422 

Telex: 21905 HPBR-BR 

Cable: HEWPACK Rio de Janeiro 

A, C,CM,E,P' 

Convex/Van Den 
Rua Jose Bonifacio 
458 Todos Os Santos 
CEP 20771 
RNDE JANEIRO, RJ 
Tel: 591-0197 
Telex: 33487 EGLB BR 
A 

ANAMED I.C.E.I. Ltda. 
Rua Sage, 103 
04012 SAO PAULO, SP 
Tel: (011)572-6537 
Telex: 24720 HPBR-BR 
M 

Datatronix Eiectronica Ltda. 
Av. Pacaembu 746-C11 
SAO PAULO, SP 
Tel: (118) 260111 
CM 

CAMEROON 

Beriac 

B, P, 23 
DOUALA 

Tel: 420153 
Telex: 5351 

C, P 

CANADA 
Alberta 

Hewlett-Packard (Canada) Ltd. 
3030 3rd Avenue N.E. 
CALGARY, Alberta T2A6T7 
Tel: (403) 236-3100 
A,C,CM,E',M,P' 

Hewlett-Packard (Canada) Ltd. 
11120-178th Street 
EDMONTON, Alberta TSS1P2 
Tel: (403) 486-6666 
A,C,CM,E,M,P 



SALES & SUPPORT OFFICES 

Arranged alphabetically by country 



CANADA (Cont'd) 

British Coiumbia 

Hewlett-Packard (Canada) Ltd. 
10691 Stiellbrldge Way 
RICHMOND, 

British Coiumbia V6X 2W7 
Tei: (604) 270-2277 
Teiex: 610-922-5059 
A,C,CM,E*,M,P* 

Hewlett-Packard (Canada) Ltd. 
121 - 3350 Douglas Street 
VICTORIA, British Columbia V8Z 3L1 
Tel: (604) 381-6616 
C 

Manitoba 

Hewlett-Packard (Canada) Ltd. 
1825 Inkster Blvd. 
WINNIPEG, Manitoba R2X1R3 
Tel: (204) 694-2777 
A,C,CM,E,M,P* 

New Brunswicic 

Hewlett-Packard (Canada) Ltd. 
814 Main Street 

MONCTON, New Brunswick E1C 1E6 

Tel: (506) 855-2841 

C 

Nova Scotia 

Hewlett-Packard (Canada) Ltd. 
Suite 111 

900 Windmill Road 
DARTMOUTH Nova Scotia B3B 1 P7 
Tel: (902) 469-7820 
C,CM,E*,M,P' 

Ontario 

Hewlett-Packard (Canada) Ltd. 
3325 N. Service Rd., Unit 3 
BURUNGTON, Ontario L7N 3G2 
Tel: (416) 335-8644 
CM* 

Hewlett-Packard (Canada) Ltd. 
496 Days Road 
KINGSTON, Ontario K7M5R4 
Tel: (613) 384-2088 
C 

Hewlett-Packard (Canada) Ltd. 
552 Newboid Street 
LONDON, Ontario N6E2S5 
Tel: (519) 686-9181 
A,C,CM,E*,M,P' 

Hewlett-Packard (Canada) Ltd. 
6877 Goreway Drive 
MISSISSAUGA, Ontario L4V 1M8 
Tei: (416) 678-9430 
A,C,CM,E,M,P 

Hewlett-Packard (Canada) Ltd. 
2670 Queensview Dr. 
OHAWA, Ontario K2B8K1 
Tel: (613) 820-6483 
A,C,CM,E',M,P* 

Hewlett-Packard (Canada) Ltd. 
The Oaks Plaza, Unit #9 
2140 Regent Street 
SUDBURY, Ontario. P3E5S8 
Tel: (705) 522-0202 
C 

Hewlett-Packard (Canada) Ltd. 
3790 Victoria Park Ave. 
WHIOWDALE, Ontario M2H 3H7 
Tel: (416) 499-2550 
C 



Quebec 

Hewlett-Packard (Canada) Ltd. 
17500 Trans Canada Highway 
South Service Road 
KIRKUND, Quebec H9J 2X8 
Tel: (514) 697-4232 
A,C,CM,E,M.P* 

HevKlett-Packard (Canada) Ltd. 
1 150 rue Claire Fontaine 
QUEBEC CITY, Quebec Q1R5G4 
Tel: (418) 6480726 
C 

Hewlett-Packard (Canada) Ltd. 

130 Robin Crescent 

SASKATOON, Saskatchewan S7L 6M7 

Tel: (306) 242-3702 

C 

CHILE 

ASC Ltda. 
Austria 2041 
SANTUGO 

Tel: 223-5946, 223-6148 
Telex: 340192 ASC CK 
CP 

Islcai Ltda. 

Av. itaiia 634 Santiago 

Casiiia 16475 

SANTIAGO 9 

Tel: 222-0222 

Telex; 440283 JCYCL CZ 

CM.E,M 

Metrolab S.A. 

Monjitas 454 of. 206 

SANTUGO 

Tel: 395752, 398296 

Telex: 340866 METLAB CK 

A 

Olympia (Chile) Ltda. 

Av. Rodrigo de Araya 1045 

Casllla 256-V 

SANTIAGO 21 

Tei: 225-5044 

Telex: 340892 OLYMP 

Cable: Olymplachile Santiagochile 

CP 



CHINA, Peopte't 
Republic of 

China Hewlett-Packard, Ltd. 
47/F China Resources BIdg. 
26 Harbour Road 
HONGKONG 
Tel: 5-8330833 
Telex: 76793 HPA HX 
Cable: HP ASIA LTD 
A*,M* 

China Hewlett-Packard, Ltd. 

P.O. Box 9610, Beijing 

4th FkX)r, 2nd Watch Factory Main 

BIdg. 

Shuang Yu Shu, Bel San Huan Rd. 

Hal DIan District 

BEUMG 

Tel: 28-0567 

Telex: 22601 CTSHP CN 

Cable: 1920 Beijing 

A,CCM,E,M,P 



COLOMBIA 

Instrumentaci6n 

H. A. Langebaek & Kier S.A. 

Carrera 4A No. 52A-26 

Apartado Aereo 6287 

BOGOTA 1, D E 

Tel: 212-1466 

Teiex: 44400 INST CO 

Cable: AARIS Bogota 

CM,E,M 

Nefromedtoas Ltda. 
Calle 123 No. 9B-31 
Apartado Aereo 100-958 
BOGOTA D E, 10 
Tel: 213-5267, 213-1615 
Telex- 43415 HEGAS CO 
A 

Compumundo 
Avenlda 15 # 107-80 
BOGOTA DE 
Tel: 214-4458 
Telex: 45466 MARICO 
P 

Carvajal, S.A. 

Calle 29 Norte No. 6A-40 

Apartado Aereo 46 

CAU 

Tel: 368-1111 
Telex: 55650 
CEP 

CONGO 

Seric-Congo 
B. P. 2105 
BRAZZAVILLE 

Tel: 815034 
Telex: 5262 

COSTA RICA 

Cientifica Costarricense S.A. 

Avenida 2, Calle 5 

San Pedro de Monies de Oca 

Apartado 10159 

SAN JOSE 

Tel: 24-38-20, 24^)8-19 
Telex: 2367 GALGUR CR 
CM.EM 

CYPRUS 

Telerexa Ltd. 
P.O. Box 4809 
14C Stasslnos Avenue 
NKOSIA 

Tel: 62698 

Telex: 2894 LEVIDO CY 
EM,P 

DENMARK 

Hewlett-Packard A/S 
Datavej 52 
DK-3460 BIRKEROD 
Tel: (02) 81-66-40 
Telex: 37409 hpas dk 
A,C,CM,E,M,P 

Hewlett-Packard A/S 
Rollghedsvej 32 
DK-8240 RISSKOV, Aarhus 

Tei: (06) 17-60-00 
Telex: 37409 hpas dk 
CE 

DOMINICAN REPUBLIC 

Mteroprog S.A. 

Juan Tomis Mejta y Cotes No. 60 
Arroyo Hondo 
SANTO DOMBMO 

Tel: 565-6268 

Telex: 4510 ARENTA DR (RCA) 
P 



ECUADOR 

CYEDE Cla. Ltda. 
Avenlda Boy Alfaro 1749 
y Belgica 
Casilla 6423 CCI 
QUITO 

Tel: 450-975, 243-052 
Telex: 22548 CYEDE ED 
CM,E,P 

Medtronics 

Vaiiadoiid 524 Madrid 

P.O. 9171, QUITO 

Tel: 223-8951 

Telex: 2298 ECKAME ED 

A 

Hospitaler S.A. 
Robles 625 
Casilla 3590 
QUITO 

Tel: 545-250, 545-122 
Telex: 2485 HOSPTL ED 
Cable: HOSPITALAR-Qulto 
M 

Ecuador Overseas Agencies C.A. 
Calle 9 de Octubre #818 
PO. Box 1296, Guayaquil 
QUITO 
Tel: 306022 

Telex: 3361 PBCGYE ED 
M 



EGYPT 

Sakrco Enterprises 
70, Mossadak Str. 
Dokki, Giza 
CAIRO 
Tel: 706440 
Telex: 93146 
C 

International Engineering Associates 
24 Hussein Hegazi Street 
Kasr-el-AIn 
CAIRO 

Tel: 23829, 21641 
Telex: 93830 lEA UN 
Cable: INTEGASSO 
E,M* 

S.S.C Medical 

40 Gezerat El Arab Street 

Mohandessin 

CAIRO 

Tel: 803844, 805998, 810263 
Telex: 20503 BSC UN 
M* 

EL SALVADOR 

IPESA de El Salvador S.A. 

29 Avenida Norte 1223 

SAN SALVADOR 

Tel: 26-6858, 26-6868 

Telex; 20639 IPESA SAL 

A,C,CM,E,P 

ETHIOPIA 

Seric-Ethlopia 
P.a Box 2764 
AOOIS ABABA 

Tel; 185114 
Telex: 21150 
CP 

FINLAND 

Hewlett-Packard Oy 
Piispankalliontle 17 
02200 E8P00 
Tel: 00358-0-88721 
Telex: 121563 HEWPA SF 
A,CCM,E,M,P 



FRANCE 

Hewlett-Packard France 
Z.I. Mercure B 
Rue Berthelot 
13763 Les Milles Cedex 
AIX-EN-PROVENCE 
Tei: (42) 59-41-02 
Telex; 410770F 
A,CE,M,P* 

Hewlett-Packard France 
64, rue Marchand Salllant 
61000 ALENCON 
Tel; (33) 29 04 42 

Hewlett-Packard France 
28 rue de la Republlque 
Boite Postale 503 
25026 BESANCON Cedex 
Tel: (81) 83-16-22 
Telex: 361157 
CM 

Hewlett-Packard France 
Chemin des Moullles 
Boite Postale 162 
69130 ECULLY Cedex (Lyon) 
Tel: (78) 833-81-25 
Telex: 310617F 
A,CE,M 

Hewlett-Packard France 

Pare d'activitfe du Bois Briard 

2, avenue du Lac 

91040 EVRY Cedex 

Tel: 6 077-96 60 

Telex: 692315F 

E 

Hewlett-Packard France 

5, avenue Raymond Chanas 

38320 EYBENS (Grenoble) 

Tei: (76) 62-57-98 

Telex: 980124 HP GRENOB EYBE 

C 

Hewlett-Packard France 
Rue Fernand. Forest 
Z.A. Kergaradec 
29239 GOUESNOU 
Tel: (98) 41-87-90 

Hewlett-Packard France 
Centre d'affaires Paris-Nord 
Bailment AmpAre 
Rue de la Commune de Paris 
Boite Postale 300 
93153 LE BLANC-MESML 
Tel; (1)865-44-52 
Telex: 211032F 
CEM 

Hewlett-Packard France 
Pare d'activitfe Cadera 
Quartier Jean-Mermoz 
Avenue du Prfeldent JF Kennedy 
F-33700 M^NAC (Bordeaux) 
Tel; (56) 34^X1-84 
Telex: 550105F 
CEM 

Hewlett-Packard France 
Immueble "Les 3 B" 
Nouveau chemin de la Garde 
ZAC du Bols Briand 
44085 NANTES Cedex 
Tel: (40) 50-32-22 
Telex; 711085F 
C" 

Hewlett-Packard France 
125, rue du Faubourg Bannier 
45000 ORLEANS 
Tel: (38) 68 01 63 



FRANCE (Cont'd) 

Hewlett-Packard France 
Zone Industrlelle de Courtaboeuf 
Avenue des Tropiques 
91947 Les Ulls Cedex ORSAY 
Tel: (6) 907-78-25 
Telex: 600048F 
A,C,CM,E,M,P 

Hewlett-Packard France 
Paris Porte-Malllot 
15, boulevard de L'Amlral-Bruix 
75782 PARIS Cedex 16 
Tel: (1) 502-12-20 
Telex: 613663F 
C,M,P 

Hewlett-Packard France 
124, Boulevard Tourasse 
64000 PAU 
Tel: (59) 80 38 02 

Hewlett-Packard France 
2 Allte de la Bourgonnette 
35100 RENNES 
Tel: (99) 51-42-44 
Telex: 740912F 
C,CM,E,M,P* 

Hewlett-Packard France 
98 avenue de Bretagne 
76100 ROUEN 
Tel: (35) 63-57-66 
Telex: 770035F 
C 

Hewlett-Packard France 
4, rue Ttiomas-k<ann 
Boite Postale 56 
67033 STRASBOURG Cedex 
Tel: (88) 28-56-46 
Telex: 890141 F 
C,E,M,P* 

Hewlett-Packard France 
La P^lpole III 

20, chemin du PIgeonnler de la Cipl^re 
F-31083 TOULOUSE Cedex 

Tel: (61)40-11-12 
Telex: 531639F 
A,C,E,P' 

Hewlett-Packard France 
9, rue Baudin 
26000 VALENCE 
Tel: (75) 42 76 16 

Hewlett-Packard France 
Caroior 

ZAC de Bols Briand 
57640 ¥ieY(Melz) 
Tel: (8) 771 20 22 
C 

Hewlett-Packard France 
Pare d'activlti des Prte 
1, rue Papin 

59658 VILLENEUVE D'ASCQ Cedex 

Tel: (20) 47 78 78 
Telex: 160124F 
C,E,M,P* 

GABON 

Sho Gabon 
P.O. Box 89 
LIBREVILLE 
Tel: 721 484 
Telex: 5230 



GERMAN FEDERAL 
REPUBLIC 

Hewlett-Packard GmbH 
Gescttattsstelle 
Keltltstrasse 2-4 
D-1000 BERUN 30 
Tel: (030) 21 99 
Telex: 018 3405 tipbin d 
A,C,EM,P 

Hewlett-Packard GmbH 
Vertrlebszentrun SOdwest 
Sctiickardstrasse 2 
D-7030 BdBLMGEN 
Tel: (07031) 645-0 
Telex: 7265 743 tiep 
A,C,CM,E,M,P 

Hewlett-Packard GmbH 
Vertrlebszentrum West 
Bedlner Strasse ill 
D-4030 RATINGEN 3 
Tel: (02102) 494-0 
Telex: 589 070 l^prad 
A,C,E,M,P 

Hewlett-Packard GmbH 
Gesctiattsstelle 
Schleefstr. 28a 
D-4600 DORTMUNO-41 
Tel: (0231) 45001 
Telex: 822858 hepdad 
A.C.E 

Hewlett-Packard GmbH 
Vertrlebszentrum Mitte 
Hewlett-Packard-Strasse 
D-638C BAD HOMBURG 
Tel: (06172)400-0 
Telex: 410 844 hpbtig 
A,C,E,M,P 

Hewlett-Packard GmbH 
Vertrlebszentrum Nord 
Kapstadtring 5 
D-2000 HAMBURG 60 
Tel: (040) 63804-1 
Telex: 021 63 032 tiptiti d 
A,C,E,M,P 

Hewlett-Packard GmbH 
Geschattsstelle 
Heidering 37-39 
D-300C HANNOVER 61 
Tel; (0511)6706-0 
Telex: 092 3259 
A,C,CM,E,M,P 

Hewlett-Packard GmbH 
Geschattsstelle 
Rosslauer Weg 2-4 
D-6800 MANNHEIM 
Tel: (0621) 70 OMi 
Telex: 0462105 
A,C,E 

Hewlett-Packard GmbH 

Geschattsstelle 

Messerschmittstrasse 7 

O7910NEUULM 

Tel: (0731) 70 73^) 

Telex: 0712816 HP ULM-D 

A,C,E' 

Hewlett-Packard GmbH 
Geschattsstelle 
Emmeflcher Strasse 13 
D-8500 NORNBERO 10 
Tel: (0911) 5205-0 
Telex: 0623 860 hpnbg 
C,CM,E,M,P 



Hewlett-Packard GmbH 
Vertrlebszentrum Scid 
Eschenstrasse 5 
[>8028 TAUFKIRCHEN 

Tel: (089)61 20 7-0 
Telex: 0524985 
A,C,CM,EM,P 

Hewlett-Packard GmbH 

Geschattsstelle 

Ermlisallee 

7517 WALDBRONN 2 
Tel: (07243) 602-0 
Telex: 782 838 hepk 
A,C,E 

GREAT BRITAIN 
S«e United Kingdom 

GREECE 

Hewlett-Packard A.E 
178, Kifisslas Avenue 
6th Floor 
Halandrl-ATHENS 
Greece 

Tel: 6471543, 6471673, 6472971 
Telex: 221 286 HPHLGR 
A,C,CM",E,M,P 

Kostas Karaynnis S.A. 
8, Omirou Street 
ATHENS 133 

Tel: 32 30 303, 32 37 371 
Telex: 215962 RKAR QR 
A,C*,CM,E 

Impexin 
Intelect Olv. 
209 Mesogion 
11525 ATHENS 
Tel: 6474481/2 
Telex: 216286 
P 

Haril Company 
38, Ulhalakopoulou 
ATHENS 612 
Tel: 7236071 
Telex: 218767 
M* 

Hellamco 
P.O. Box 87528 
18507 PIRAEUS 
Tel: 4827049 
Telex: 241441 
A 

GUATEMALA 

IPESA 

Avenlda Retorma 3-48, Zona 9 
GUATEMAUCITY 

Tel: 316627, 314786 
Telex: 30SS765 IPESA GU 
A,C,CM,E,M,P 

HONG KONG 

Hewlett-Packard Hong Kong, Ltd. 

G.P.O. Box 795 

5th Floor, Sun Hung Kal Centre 

30 Harbour Road 

HONGKONG 

Tel: 5-8323211 

Telex: 66678 HEWPA HX 

Cable: HEWPACK Hong Kong 

E,C,P 

CET Ltd. 

10th Floor, Hua Asia BIdg. 
64-66 Gloulester Road 
HONGKONG 

Tel: (5) 200922 
Telex: 85148 CET HX 
CM 



Schmidt & Co. (Hong Kong) Ltd. 
18th Floor, Great Eagle Centre 

23 Harbour Road 
HONGKONG 
Tel: 6-8330222 

Telex: 74766 SCHMC HX 
A,M 

ICELAND 

Hewlett-Packard Iceland 
Hoefdabakka 9 
110 Reykjavik 
Tel: (1) 67 1000 
A,C,CM,E,M,P 

INDIA 

Computer products are sold through 
Blue Star Ltd.AII computer repairs and 
maintenance service is done through 
Computer Maintenance Corp. 

Blue Star Ltd. 

SabrI Complex 2nd Roor 

24 Residency Rd. 
BANGALORE 560 025 
Tel: 55660, 578881 
Telex: 0845-430 
Cable; BLUESTAR 
A,C*,CM,E 

Blue Star Ltd. 
Band Box House 
PrabhadevI 
BOMBAY 400 025 
Tel: 4933101, 4933222 
Telex: 011-71051 
CaWe; BLUESTAR 
A,M 

Blue Star Ltd. 
Sahas 

414/2 VIr Savarkar Marg 
PrabhadevI 
BOMBAY 400 025 

Tel: 422-6155, 422-6556 
Telex: 011-71193 BSSS IN 
Cable: FROSTBLUE 
A,C*,CM,E,M 

Blue Star Ltd. 

Kalyan, 19 Vishwas Colony 

Alkapuri, BORODA, 390 005 

Tel; 65235, 65236 

Cable: BLUE STAR 

A 

Blue Star Ltd. 
7 Hare Street 
CALCUTTA 700 001 
Tel: 230131, 230132 
Telex: 021-7655 
Cable: BLUESTAR 
A,M 

Blue Star Ltd. 

133 Kodambakkam High Road 
MADRAS 600 034 

Tel: 472056, 470238 
Telex; 041-379 
Cable: BLUESTAR 
A,M 

Blue Star Ltd. 
13 Community Center 
New Friends Colony 
NEWDELHI110065 
Tel: 633773, 634473 
Telex: 031-61120 
Cable; BLUEFROST 
A,C*,CM,E,M 



Blue Star Ltd. 
15/16 CWellesleyRd. 
PUNE411 Oil 
Tel: 22775 
Cable; BLUE STAR 
A 

Blue Star Ltd, 

2-2-47/ 110B Bolarum Rd. 

SECUNDERABAD500003 

Tel: 72057, 72058 
Telex: 0155645 
Cable: BLUEFROST 
A.E 

Blue Star Ltd. 
T.C. 7/603 Poornima 
Maruthunkuzhi 
TRIVANDRUM695 013 
Tel; 65799, 65820 
Telex: 0884-259 
Cable: BLUESTAR 
E 

Computer Maintenance Corporation 
Ltd. 

115, Sarojini Devi Road 
SECUNDERABAO500 003 

Tel: 310-184, 345-774 
Telex: 031-2960 
C" 

INDONESIA 

BERCA Indonesia P.T. 

P.O.Box 496/Jkt. 

Jl. Abdul Muis 62 

JAKARTA 

Tel: 21-373009 

Telex; 46748 BERSAL lA 

Cable: BERSAL JAKARTA 

P 

BERCA Indonesia P.T. 
P.O.Box 2497/Jkt 
Antara BIdg., 12th Floor 
Jl. Medan Merdeka Selatan 17 
JAKARTA-PUSAT 
Tel: 21-340417, 341445 
Telex: 46748 BERSAL lA 
A,C,E,M 

BERCA Indonesia P.T. 
Jalan Kutai 24 
SURABAYA 

Tel: 67118 

Telex: 31 146 BERSAL SB 
Cable: BERSAL-SURABAYA 
A*,E,M,P 

IRAQ 

Hewlett-Packard Trading S.A. 

Sen/ice Operation 

Al Mansoor City 9B/3/7 

BAGHDAD 

Tel: 551-49-73 

Telex; 212-455 HEPAIRAQ IK 
C 

IRELAND 

Hewlett-Packard Ireland Ltd. 
82/83 Lower Leeson Street 
DUBUN2 

Tel: 0001 608800 
Telex: 30439 
A,C,CM,E,M,P 

Cardiac Services Ltd. 
Kilmore Road 
Artane 
DUSLIN5 

Tel: (01) 361820 
Telex: 30439 
M 



SALES & SUPPORT OFFICES 

Arranged alphabetically by country 



ISRAEL 

Eldan Electronic Instrument Ltd. 
P.O.Box 1270 
JERUSALEM 91000 
16, Otialiav St. 
JERUSALEM 94467 
Tel: 533 221, 653 242 
Telex: 25231 AB/PAKRD IL 
A,M 

Computation and Measurement 

Systems (CMS) Ltd 

1 1 Masad Street 

67060 

TEL-AVIV 

Tel: 3B8 388 

Telex: 33569 Motil IL 

C,CM,E,P 

ITALY 

Hewlett-Packard Italiana S.p.A 

Traversa 99C 

Via Giulio Petroni, 19 

1-70124 BARI 

Tel: (080) 41-07-44 

CM 

Hewlett-Packard Italiana S.p.A. 
Via Emilia. 51/C 

1-4001 1 BOLOGNA Anzola Dell'Emilla 

Tel: (051) 731061 
Telex: 511630 
C,E,M 

Hewlett-Packard Italiana S.p.A. 

Via Principe Nk:ola 43G/C 

1-95126 CATANU 

Tel: (095) 37-10-87 

Telex: 970291 

C 

Hewlett-Packard Italiana S.p.A. 
Via G. Di Vittorio 9 
1-20063 CERNUSCO 8UL 
NAVKSLK) 

(Milano) 

Tel: (02) 4459041 
Telex: 334632 
A,C,CM,E,M,P 

Hewlett-Packard Italiana S.p.A. 
Via C. Colombo 49 
1-20090 TREZZANO SUL 
NAVKUO 

(Milano) 

Tel: (02) 4459041 
Telex: 322116 
C 

Hewlett-Packard Italiana S.p.A. 

Via Nuova San Rocco a 

Capodimonte, 62/A 

1-80131 NAPOU 

Tel: (061) 7413544 

Telex: 710698 

A",C,E,M 

Hewlett-Packard Italiana S.p.A. 
Viale G. Modugno 33 
1-16156 OENOVAPEQU 
Tel: (010) 6^37-07 
Telex: 215238 
C,E 

Hewlett-Packard Italiana S.p.A. 

Via Pelizzo 15 

1-35128 PADOVA 

Tel: (049) 664888 

Telex: 430315 

A,C,E,M 



Hewlett-Packard Italiana S.pA. 
Viale C. Pavese 340 
1-00144 ROMA EUR 
Tel: (06) 54831 
Telex: 610514 
A,C,E,M,P' 

Hewlett-Packard Italiana S.p.A. 
Via di Casellina 57/C 
1-50018 SCANDKCI-FIRENZE 

Tel: (056) 753863 
C,E,M 

Hewlett-Packard Italiana S.pA. 
Corso Svizzera, 185 

1- 10144 TORINO 
Tel: (Oil) 74 4044 
Telex: 221079 
A'.CE 

IVORY COAST 

S.I.T.E.L. 

Societe Ivoirienne de 

Telecommunications 

Bd. Giscard d'Estaing 

Carrelour Marcory 

Zone 4.A. 

Boite postale 2580 

ABIDJAN01 

Tel: 353600 

Telex: 43175 

E 

S.LT.L 

Immeuble "Le General" 
Av. du General de Gaulle 
01 BP 161 
ABIDJAN 01 

Tel: 321227 
C,P 

JAPAN 

Yokogawa-Hewlett-Packard Ltd. 
152-1, Onna 
ATSUGI,Kanagawa,243 
Tel: (0462) 25-0031 
C,CM,E 

Yokogawa-Hewlett-Packard Ltd. 

Meiji-Seimei BIdg. 6F 

3-1 Hon Chiba-Cho 

CMBA,280 

Tel: 472 25 7701 

C,E 

Yokogawa-Hewlett-Packard Ltd. 
Yasuda-Seimei Hiroshima BIdg. 
6-11, Hon-dori, Naka-ku 
HR08I«U,730 
Tel: 82-241-0611 

Yokogawa-Hewlett-Packard Ltd. 
Towa Building 

2- 3, Kaigan-dori, 2 Chome Chuo-ku 
KOBE, 650 

Tel: (078) 392-4791 
C,E 

Yokogawa-Hewlett-Packard Ltd. 
Kumagaya Asahi 82 BIdg 

3- 4 Tsukuba 

KUMAGAYA, Saitama 360 
Tel: (0485) 24-6563 

CCM.E 

Yokogawa-Hewlett-Packard Ltd. 
Asahi Shinbun Dalkihl Seimei BIdg. 

4- 7, Hanabata-cho 
KUMAMOTO,860 
Tel: (096) 354-7311 
C,E 



Yokogawa-Hewlett-Packard Ltd. 
Shin-Kyoto Center BIdg. 
614, Higashi-Shiokoii-cho 
Karasuma-Nlshiiru 
Shiokoji-dori, Shimogyo-ku 
KYOTO, 600 
Tel: 075-343-0921 
C,E 

Yokogawa-Hewlett-Packard Ltd. 

Mito Mitsui BIdg 

4-73, Sanno-maru, 1 Chome 

MITO, Ibaraki 310 

Tel: (0292) 25-7470 

CCM.E 

Yokogawa-Hewlett-Packard Ltd. 

Meiii-Seimei Kokubun BIdg. 7-8 

Kokubun, 1 Chome, Sendai 

MIYAGI,9B0 

Tel: (0222)25-1011 

C,E 

Yokogawa-Hewlett-Packard Ltd. 

Nagoya Kokusai Center Building 

47-1, Nagono, 1 Chome 

Nakamura-ku 

NAGOYA, 450 

Tel: (052) 571-5171 

C,CM,E,M 

Yokogawa-Hewlett-Packard Ltd. 

Saikyoren Building 

1-2 Dote-machi, OHMIYA 

Saitama 330 

Tel: (0486) 45-8031 

Yokogawa-Hewlett-Packard Ltd. 
Chuo BIdg., 

4-20 Nishinakaiima, 5 Chome 

Yodogawa-ku 

OSAKA, 532 

Tel: (06) 304-6021 

Telex: YHPOSA 523-3624 

A,CCM,E,M.P* 

Yokogawa-Hewlett-Packard Ltd. 
27-15, Yabe, 1 Chome 
SAGAMMARAKanagawa, 229 
Tel: 0427 59-1311 

Yokogawa-Hewlett-Packard Ltd. 

Daiichi Seimei BIdg. 

7-1, Nishi Shinjuku, 2 Chome 

Shinjuku-ku,TOKY0 160 

Tel: 03-348-4611 

C,E 

Yokogawa-Hewlett-Packard Ltd. 
29-21 Takaido-Hlgashi, 3 Chome 
Suginami-ku TOKYO 168 
Tel: (03) 331-6111 
Telex: 232-2024 YHPTOK 
A,C,CM,E,M,P* 

Yokogawa Hokushin Electric Corp. 

9-32 Nokacho 2 Chome 

2 Chome Musashino-shi 

TOKYO, 180 

Tel: (0422) 54-1111 

Telex: 02822-421 YEW MTK J 

A 

Yokogawa-Hewlett-Packard Ltd. 

Meiji-Seimei 

Utsunomiya Odori Building 
1-5 Odori, 2 Chome 
UTSUNOMIYA, Tochigi 320 
Tel: (0286) 33-1 153 
CE 



Yokogawa-Hewlett-Packard Ltd. 
Yasuda Seimei Yokohama Nishiguchi 
BIdg. 

30-4 Tsuruya-cho, 3 Chome 
YOKOHAMA 221 
Tel: (045) 312-1252 
C,E 



JORDAN 

Scientific and Medical Supplies Co. 

P.O. Box 1387 

AMMAN 

Tel: 24907, 39907 
Telex: 21456 SABCO JO 
C,E,M,P 

KENYA 

ADCOM Ltd., Inc., Kenya 
P.OBox 30070 
NAIROBI 

Tel: 331955 
Telex: 22639 
E,M 

KOREA 

Samsung Hewlett-Packard Co. Ltd. 

Dongbang Yeoeuldo Building 

12- 16th Roors 

36-1 Yeoeuido-dong 

Yongdeungpo-ku 

SEOUL 

Tel: 784-2666, 784-4666 
Telex: 25166 SAMSAN K 
A,aCM,E,M,P 

Young In Scientilic Co., Ltd. 

Youngwha Building 

547 Shinsa Dong, Kangnam-ku 

SEOUL 135 

Tel: 5467771 

Telex: K23457 GINSCO 

A 

KUWAIT 

Al-Khaldiya Trading & Contracting 

P.O. Box 830 

SAFAT 

Tel: 424910,411726 
Telex: 22481 AREEG KT 
Cable: VISCOUNT 

E,M,A 

Gulf Computing Systems 

PO. Box 25125 

SAFAT 

Tel: 435969 

Telex: 23648 

P 

Photo & Cine Equipment 

P.O. Box 270 

SAFAT 

Tel: 2445111 

Telex: 22247 MATIN KT 

Cable: MATIN KUWAIT 

P 

W.J. Towell Computer Senices 

P.O. Box 5897 

SAFAT 

Tel: 2462640 

Telex: 30336 TOWELL KT 
C 

LEBANON 

Computer Information Systems S.A.L. 

Chammas Building 

P.O. Box 11-6274 Dora 

BEIRUT 

Tel: 89 40 73 

Telex: 42309 

C,E,M,P 



LIBERIA 

Unichemicals Inc. 
P.O. Box 4509 
MONROVIA 

Tel: 224282 
Telex: 4509 
E 



MADAGASCAR 

Technique et Precision 
12, rue de Nice 
P.O. Box 1227 
101 ANTANANARIVO 
Tel: 22090 
Telex: 22255 
P 



LUXEMBOURG 

Hewlett-Packard Belgium S.A./N.V. 

Blvd de la Woluwe, 100 

Woluwedal 

B-1200 BRUSSELS 

Tel: (02) 762-32-00 

Telex: 23-494 paloben bru 

A,aCM,E,M,P 

MALAYSIA 

Hewlett-Packard Sales (Malaysia) 
Sdn. Bhd. 
9th Floor 

Chung Khiaw Bank Building 
46, Jalan Raja Laut 
KUAU LUMPUR 

Tel: 03-986555 

Telex: 31011 HPSM MA 

A,C,E,M,P' 

Protel Engineering 
P.O.Box 1917 
Lot 6624, Section 64 
23/4 Pending Road 
Kuching, SARAWAK 
Tel: 36299 

Telex: 70904 PROMAL MA 
Cable: PROTELENG 
A,E,M 

MALTA 

Philip Toledo Ltd. 
Birkirkara P.O. Box 11 
Notabile Rd. 
MRIEHEL 

Tel: 447 47, 455 66 
Telex: 1649 
E,M,P 

MAURITIUS 

Blanche BIrger Co. Ltd. 

18, Jules Koenig Street 

PORT LOUIS 

Tel: 20828 

Telex: 4296 

P 

MEXICO 

Hewlett-Packard de Mexk», S.A. 

Francisco J. Allan #30 

Colonia Nueva 

Los Angeles 27140 

COAHUUt,Torreon 

Tel: 37220 

P 

Hewlett-Packard de Mexkx), S.A. 

Monti Morelos 299 

Fracclonamiento Loma Bonita 45060 

GUADALAJARA, Jalisco 

Tel: 316630/314600 

Telex: 0684 186 ECOME 

P 



MEXICO (Cont'd) 

Microcomputadoras Hewlett-Packard, 
S.A. 

Monti Pelvoux 115 
LOS LOMAS, Mexico. D.F. 
Tel: 520-9127 
P 

Hewlett-Packard Mexicana, S.A. 
de C.V. 

Av. Periferico Sur No. 6501 
Tepepan, Xoctiimiico 
16020 MEXICO D.F. 
Tel: 6-76-46-00 

Telex: 17-74-507 HEWPACK MEX 
A,C,CM,E,M,P 

Hewlett-Packard De Mexico (Polanco) 
Avenida Ejercito Nacional #579 
2day3er pfeo 

Colonia Granada 11560 
MEXICO D.F. 

Tel: 254-4433 
P 

Hewlett-Packard De Mexico, S.A. 
de C.V. 

Czda. del Valle 

409 Ote. 4tti Piso 

Colonia del Valle 

Municipio de Garza Garni 

66220 MONTERREY, Nuevo Le6n 

Tel: 78 42 41 

Telex: 038 410 

P 



MOROCCO 

Etablissement Huljert Dolbeau & File 
81 rue Karatchi 

B. P. 11133 
CASABLANCA 

Tel: 3041-82. 3068-38 
Telex: 23051, 22822 
E 

Gerep 

2, rue Agadir 
Boite Postale 156 
CASABLANCA 01 

Tel; 272093, 272095 
Telex: 23 739 
P 

Sema-Maroc 
Dept. Seric 
6, rue Lapebie 
CASABLANCA 

Tel: 260980 
Telex: 21641 

C, P 

NETHERLANDS 

Hewlett-Packard Nederland B.V. 

Startbaan 16 

1187XRAM8TB.VEEN 

P.O. Box 667 

Nil 180 ARAMSmVEEN 

Tel: (020) 547-6911 

Telex: 13 216 HEPA NL 

A,C,CM,E,M,P 

Hewlett-Packard Nederland B.V. 
Bongerd 2 

NL 2906VK CAPELLE A/D USSEL 

P.O. Box 41 

NL 2900AA CAPELLE A/D USSEL 

Tel: (10) 51-64-44 
Telex: 21261 HEPAC NL 
C,E 



Hewlett-Packard Nederland B.V. 
Pastoor Petersstraat 134-136 
NL 5612 LV EINDHOVEN 
P.a Box 2342 
NL 5600 CH EINDHOVEN 
Tel: (040)326911 
Telex: 51484 hepae nl 
A,C,E,M,P 

NEW ZEALAND 

Hewlett-Packard (N.Z.) Ltd. 
5 Owens Road 
P.O. Box 26-189 
Epsorri. AUCKLAND 
Tel; 687-159 

Gable: HEWPAK Auckland 
C,CM,E,P' 

Hewlett-Packard (N.Z.) Ltd. 
4-12 Cruickshank Street 
Kilbirnle, WELLINGTON 3 

P.O. Box 9443 

Courtenay Place. WELLMGTON 3 
Tel; 877-199 

Cable: HEWPACK Wellington 
C,CM,E,P 

Northrop Instruments & Systems Ltd. 

369 Ktiyber Pass Road 

P.O. Box 8602 

AUCKLAND 

Tel: 794-091 

Telex: 60605 

A,M 

Northrop Instruments & Systems Ltd. 

IIOMandevilleSt. 

P.O. Box 8388 

CHRISTCHURCH 

Tel: 488-873 

Telex: 4203 

A,M 

Northrop Instruments & Systems Ltd. 

Sturdee House 

85-87 Ghuznee Street 

P.O. Box 2406 

WELLINGTON 

Tel: 850^91 

Telex: NZ 3380 

A,M 

NIGERIA 

Elmeco Nigeria Ltd. 

46, Calcutta Crescent Apapa 

PO. Box 244and 

UGOS 

E 

NORTHERN IRELAND 
See United Kingdom 

NORWAY 

Hewlett-Packard Norge A/S 
Foike Bernadottes vei 50 
P.O. Box 3558 

(1-5033 FYLUNG8DALEN (Bergen) 
Tel: 0047/5/16 55 40 
Telex: 76621 hpnas n 
C,E,M 

Hewlett-Packard Norge A/S 
Osterndalen 16-18 
P.O. Box 34 
N-t345 OiTERiS 
Tel: 0047/2/17 11 80 
Telex: 76621 hpnas n 
A,C,CM.E,M,P 



OMAN 

Khimjil Ramdas 
P.O. Box 19 

MUSCAT/SULTANATE OF OMAN 

Tel: 745601 

Telex: 5289 BROKER MB MUSCAT 
P 

Suhail & Saud Bahwan 
P.O.Box 169 

MUSCAT/SULTANATE OF OMAN 

Tel: 734201 

Telex: 5274 BAHWAN MB 
E 

Imtac LLC 
P.O. Box 8676 

MUTRAH/SULTANATE OF OMAN 

Tel: 601695 

Telex: 5741 Tawoos On 

A,C.M 

PAKISTAN 

Mushko & Company Ltd. 
House No. 16, Street No. 16 
Sector F-6/3 
ISLAMABAD 
Tel: 824545 

Cable; FEMUS Islamabad 
A,E,M.P- 

Mushko & Company Ltd. 
Oosman Chambers 
Abdullah Haroon Road 
KARACHI 0302 
Tel: 624131, 524132 
Telex: 2894 MUSKO PK 
Cable: COOPERATOR Karachi 
A,E,M,P* 

PANAMA 

Electronico Balboa. S.A. 
Calle Samuel Lewis, Ed. Alfa 
Apartado 4929 
PANAMAS 
Tel: 64-2700 

Telex: 3483 ELECTRON PG 
A,CM,E,M,P 

PERU 

Cla Electro MMIca S.A. 

Los Flamencos 145, Ofc. 301/2 

San Isidro 

Casilla 1030 

UMA1 

Tel; 41-4325, 41-3705 

Telex; Pub. Booth 25306 PEC PISIDR 

CM,E,M,P 

SAMS 

Arenida Republica de Panama 3534 
San Isidro, LIMA 
Tel: 419928/417108 
Telex: 20450 PE LIBERTAD 
A,C,P 

PHILIPPINES 

The Online Advanced Systems Corp. 

2nd Floor, Electra House 

115-117 Esteban Street 

Legaspi Village, Makati 

P.O. Box 1510 

Metro MANU 

Tel: 815-38-10 (up to 16) 

Telex: 63274 ONLINE PN 

A,C,E,M,P 



PORTUGAL 

Mundinter Intercambio 
Mundial de Comircio S.A.R.L. 
Av. Antonio Augusto Aguiar 138 
Apartado 2761 
LISBON 

Tel: (19) 53-21-31, 53-21-37 
Telex: 16691 munter p 
M 

Soquimica 

Av da Liberdade, 220-2 
1298 LISBOA Codex 
Tel: 56-21-82 
Telex: 13316 SABASA 
A 

Telectra-Empresa Ttenica de 
Equipmentos Etectricos S.A.R.L. 
Rua Rodrigo da Fonseca 103 
PO. Box 2531 
LISBON 1 

Tel: (19) 68-60-72 
Telex: 12598 
CM,E 

C.PC.S.I. 

Rua de Costa Cabral 575 

4200 PORTO 

Tel: 499174/495173 

Telex: 26054 

CP 

PUERTO RICO 

Hewlett-Packard Puerto Rico 
101 Mutoz Rivera Av 
Esu. Calle Ochoa 
HATOREY, Puerto Rico 00918 
Tel: (809) 754-7800 
A,C,CM,M,E,P 

QATAR 

Computer Arabia 
P.O. Box 2750 
DOHA 

Tel: 428656 

Telex; 4806 CHPARB 

P 

Nasser Trading & Contracting 

P.O.Box 1563 

DOHA 

Tel: 422170 

Telex: 4439 NASSER DH 
M 

SAUDI ARABIA 

Modern Electronics Establishment 
Hewlett-Packard Division 
P.a Box 281 
Thouqbah 
AL-KHOBAR 31952 
Tel: 895-1760, 895-1764 
Telex; 671 106 HPMEEKSJ 
Cable: ELECTA AL-KHOBAR 
C,E,M 

Modern Electronk;s Establishment 

Hewlett-Packard Division 

P.a Box 1228 

JEDDAH 

Tel: 644 96 28 

Telex: 4027 12 FARNAS SJ 

Cable: ELECTA JEDDAH 

A,C,CM,E,M,P 

Modern Electronics Establishment 

Hewlett-Packard Division 

P.aBox 22015 

RIYADH 11495 

Tel: 476-3030 

Telex: 202049 MEERYD SJ 

A,C,CM,E,M,P 



Abdul Ghani El Ajou Corp. 

P.a Box 78 

RIYADH 

Tel: 40 41 717 

Telex: 200 931 EL AJOU 

P 

SCOTLAND 

See United Kingdom 

SENEGAL 

Societe Hussein Ayad & Cie. 

76, Avenue Georges Pompidou 

B.P. 305 

DAKAR 

Tel: 32339 

Cable: AYAD-Dakar 

E 

Moneger Distribution S.A. 

1, Rue Parent 

B.P. 148 

DAKAR 

Tel: 215 671 

Telex: 587 

P 

Systeme Sereice Conseil (SSC) 

14. Avenue du Parachois 

DAKAR ETOILE 

Tel: 219976 

Telex: 577 

CP 

SINGAPORE 

Hewlett-Packard Singapore (Sales) 
Pte. Ltd. 

08-00 Inchcape House 
450-2 Alexandra Road 
Alexandra P.O. Box 58 
SINGAPORE, 91 16 

Tel: 4731788 

Telex: 34209 HPSGSO RS 
Cable: HEWPACK, Singapore 
A,aE,M,P 

Dynamar International Ltd. 

Unit 06- 11 Block 6 

Kolam Ayer Industrial Estate 

SINGAPORE 1334 

Tel: 747-6188 

Telex: 26283 RS 

CM 

SOUTH AFRICA 

Hewlett-Packard So Africa (Pty.) Ltd. 
P.a Box 120 

Howard Place CAPE PROVMCE 7460 
Pine Park Center, Forest Drive. Pine- 
lands 

CAPE PROVINCE 7405 
Tel: (021) 63 7954 
Telex: 57-20006 
A,C.CM.E.M.P 

Hewlett-Packard So Africa (Pty.) Ltd. 

2nd Floor Juniper House 

92 Overport Drive 

DURBAN 4067 

Tel: (031) 28-4178 

Telex: 6-22954 

C 

Hewlett-Packard So Afrka (Pty.) Ltd. 

6 Linton Arcade 

511 Cape Road 

Linton Grange 

PORT EUZA8ETH 6001 

Tel: 041-301201 

Telex: 24-2916 

C 



SALES & SUPPORT OFFICES 

Arranged alphabetically by country 



SOUTH AFRICA (Cont'd) 

Hewlett-Packard So Africa (Pty.) Ltd. 

Fountain Center 

Kail(den Str. 

Monument Park Ext 2 

PRETORIA 0105 

Tel: (012) 45 57256 

Telex: 3-21063 

C,E 

Hewlett-Packard So Africa (Pty.) Ltd. 
Private Bag Wendywood 
SANDT0N2144 

Tel: 802-5111, 802-5125 

Telex: 4-20677 SA 

Cable: HEWPACK Johannesburg 

A,C,CM,E,M,P 

SPAIN 

Hewlett-Packard Espanola S.A. 

Calle Entenza, 321 

08029 BARCELONA 

Tel: 3/322 24 61,321 73 64 

Telex: 52603 hpbee 

A,C,EM,P 

Hewlett-Packard Espaflola S.A. 

Calle San Vicente S/N 

Edificio Albia II-7B 

48001 BILBAO 

Tel: 4/423 83 06 

A,C,E,M 

Hewlett-Packard Espaflola S.A. 

Crta. de la Corufta, Km. 16, 400 

Las Rozas 

E-MAORID 

Tel: (1)637.00.11 

Telex: 23515 HPE 

CM 

Hewlett-Packard Espaflola S.A. 

Avda. S Francisco Javier, S/N 

Planta 10. Edificio Sevilla 2 

41005 SEVILU 

Tel: 54/64 44 54 

Telex: 72933 

A,C,M,P 

Hewlett-Packard Espaflola S.A. 
Isabel La Catolica, 8 
46004 VALENCIA 
Tei: 0034/6/351 59 44 
CP 

SWEDEN 

Hewlett-Packard Sverige AB 

Ostra Tullgatan 3 

S-21128IIULMd 

Tel: (040) 70270 

Telex: (854) 17886 (via Spinga 

office) 

CP 

Hewlett-Packard Sverige AB 
Skalfioltsgatan 9, Kista 
Box 19 

8-16393 SPAnGA 
Tel: (08) 750-2000 
Telex: (854) 17886 
Telefax: (08) 7527781 
A,C,CM,E.M,P 

Hewlett-Packard Sverige AB 
FrOtailsgatan 30 

S-42132 VASTRA-FRdLUNDA (Gothen- 
burg) 

Tel: (031) 49-09-50 

Telex: (854) 17886 (via Spinga 

office) 

A,C,CM,E,M,P 



SUDAN 

Mediterranean Engineering & Trading 

Co. Ltd. 

P.O. Box 1025 

KHARTOUM 

Tel: 41184 

Telex: 24052 

CP 



SWITZERLAND 

Hewlett-Packard (Schweiz) AG 

Ciarastrasse 12 

CH-405B BASEL 

Tei: (61) 33-59-20 

A 

Hewlett-Packard (Schweiz) AG 
7, rue du Bois-du-Lan 
Case postale 365 
CH-1217 MEYRIN 1 
Tel: (0041) 22-83-1 1-11 
Telex:27333 HPAG CH 
CCM 

Hewlett-Packard (Schweiz) AG 

Alimend 2 

CH-8967 WIDEN 

Tei: (0041) 57 31 21 11 

Telex: 53933 hpag ch 

Cable: HPAG CH 

A,CCM,E,M,P 

SYRIA 

General Electronic Inc. 

Nuri Basha Ahnaf Ebn Kays Street 

P.O. Box 5781 

DAMASCUS 

Tei: 33-24-87 

Telex: 411 215 

Cable: ELECTROBOR DAMASCUS 
E 

Middle East Electronics 
P.O.Box 2308 
Abu Rumaneh 
DAMASCUS 
Tel: 33 45 92 
Telex: 411 771 
M 

TAIWAN 

Hewlett-Packard Taiwan 
Kaohsiung Office 

11/F, 456, Chung Hsiao 1st Road 
KAOHSIUNG 

Tei: (07) 2412318 
CE 

Hewlett-Packard Taiwan 

8th Floor, Hewlett-Packard Building 

337 Fu Hsing North Road 

TAIPEI 

Tei: (02) 712-0404 
Telex: 24439 HEWPACK 
Cable:HEWPACK Taipei 
A,CCM,E,M,P 

ing Lih Trading Co. 

3rd Roor, 7 Jen-Ai Road, Sec. 2 

TAIPE1 100 

Tei: (02) 3948191 
Cable: INGLIH Taipei 
A 

THAILAND 

Unimesa Co. Ltd. 

30 Patpong Ave., Suriwong 

BANGKOK 5 

Tel: 235-5727 

Telex: 84439 Simonco TH 

Cable: UNIMESA Bangkok 

A,CE,M 



Bangkok Business Equipment Ltd. 

5/5-6 Dejo Road 

BANGKOK 

Tel: 234-8670, 234-8671 
Telex: 87699-BEQUIPT TH 
Cable: BUSIQUIPT Bangkok 
P 

TOGO 

Societe Africaine De Promotion 

Immeuble Sagap 

22, Rue d'Atakpame 

B.P. 4150 

LOME 

Tei: 21-62-88 
Telex: 5304 
P 

TRINIDAD & TOBAGO 

Caribbean Telecoms Ltd. 

Corner McAllister Street & 

Eastern Main Road, Laventille 

P.O. Box 732 

PORT-OF-SPAIN 

Tei: 624-4213 

Telex: 22561 CARTEL WG 

Cable: CARTEL, PORT OF SPAIN 

CM,E,M,P 

Computer and Controls Ltd. 
P.O. Box 51 

66 Independence Square 
PORT-OF-SPAM 

Tei: 62-279-85 

Telex: 3000 POSTLX WG, ACCT 

L0090 AGENCY 1264 

A,P 

Feral Assoc. 
8 Fitzgerald Lane 
PORT-OF-SPAIN 

Tel: 62-36864, 62-39255 
Telex: 22432 FERALCO 
Cable: FERALCO 
M 



TUNISIA 

Precision Eiectronique S.A.R.L. 

31 Avenue de la Liberie 

TUNIS 

Tel: 893937 

Telex: 13238 

P 

Tunlsie Eiectronique S.A.R.L. 
94, Av. Jugurtha, Mutuelleviile 
1002 TUNIS-BELVEDERE 
Tei: 280144 
Telex: 13238 
CE,P 

Corema S.A. 

23, bis Rue de Marseille 

TUNIS 

Tei: 253-821 

Telex: 14812 CABAM TN 
M 

TURKEY 

E.M.A 

Mediha Eidem Sokak No. 41/6 

Yenisehir 

ANKARA 

Tei: 319175 

Telex: 46912 KTXTR 

Cable: EMATRADE ANKARA 

M 



Teknim Company Ltd. 

Iran CaddesI No. 7 

Kavakiidere 

ANKARA 

Tel: 275800 

Telex: 42155 TKNM TR 

E,CM 

Saniva Bilgisayar Sistemleri A.S. 

Buyukdere Caddesi 103/6 

Gayrettene 

ISTANBUL 

Tel: 1727030 

Telex: 26345 SANI TR 

CP 

Best Inc. 

Esentepe, Gazeteciler Sitesi 

Keskin Kalemy 

Sokak 6/3, Gayrettepe 

ISTANBUL 

Tel: 1721326 

Telex: 42490 

A 

UNITED ARAB 
EMIRATES 

Emitac Ltd. 
P.O. Box 1641 
SHARJAH 

Tel: 591181 

Telex: 68136 EMITAC EM 
Cable: EMITAC SHARJAH 
E,C,M,P,A 

Emitac Ltd. 

P.O. 80x 2711 

ABU DHABI 

Tei: 820419-20 

Cable: EMITACH ABUDHABI 

Emitac Ltd. 
P.O. Box 8391 
DUBAI, 
Tel: 377591 

Emitac Ltd. 
P.O. Box 473 
RASALKHAMAH 

Tei: 28133, 21270 

UNITED KINGDOM 

GREAT BRITAIN 

Hewlett-Packard Ltd. 
Trafalgar House 
Navigation Road 
ALTRINCHAM 
Cheshire WA14 1NU 
Tei: 061 928 6422 
Telex: 668068 
A,CE,M,P 

Hewlett-Packard Ltd. 

Miller House 

The Ring, BRACKNELL 

Berks RG12 1XN 

Tel: 0344 424898 

Telex: 848733 

E 

Hewlett-Packard Ltd. 
Elstree House, Elstree Way 
BOREHAMWOOD, Herts WD6 1SG 
Tei: 01507 5000 
Telex: 8952716 
CE 

Hewlett-Packard Ltd. 
Oakfleld House, Oakfield Grove 
Clifton BRISTOL, Avon BS8 2BN 
Tei: 0272 736806 
Telex: 444302 
CE,P 



Hewlett-Packard Ltd. 
Bridewell House 
9 Bridewell Place 
LONDON EC4V6BS 
Tei: 01 583 6565 
Telex: 298163 
CP 

Hewlett-Packard Ltd. 
Pontefract Road 

NORMANTON, West Yorkshire WF6 1RN 
Tel: 0924 895566 
Telex: 557355 
CP 

Hewlett-Packard Ltd. 
The Quadrangle 
106-118 Station Road 
REDHILL, Surrey RH1 1PS 
Tei: 0737 68655 
Telex: 947234 
CE,P 

Hewlett-Packard Ltd. 

Avon House 

435 Stratford Road 

Shirley, SOLIHULL, West Midlands 

B90 4BL 

Tel: 021 745 8800 
Telex: 339105 
CE,P 

Hewlett-Packard Ltd. 
West End House 
41 High Street, West End 
SOUTHAMPTON 

Hampshire S03 3DQ 
Tel: 0703 476767 
Telex: 477138 
CP 

Hewlett-Packard Ltd. 
Harmon House 
No. 1 George Street 
UXBRIOGE, Middlesex UX8 1YH 
Tel: 896 720 20 
Telex: 893134/5 
C,CM,E,M,P 

Hewlett-Packard Ltd. 
King Street Lane 
Winnersh. WOKINGHAM 
Berkshire RG11 5AR 
Tel: 0734 784774 
Telex: 847178 
A,CE,M,P 

IRELAND 

NORTHERN IRELAND 

Hewlett-Packard (Ireland) Ltd. 

Carrickfergus industrial Centre 

75 Belfast Road, Carrickfergus 

BELFAST BT388PH 

Tei: 09603 67333 

Telex: 747626 

CE 

SCOTLAND 

Hewlett-Packard Ltd. 
8 Woodside Place 
GUSGOW,G3 7QF 
Tel: 041 332 6232 
Telex: 779615 
CE 

Hewlett-Packard Ltd. 
SOUTH QUEENSFERRY 

West Lothian, EH30 9TG 
Tel: 031 331 1188 
Telex: 72682 
C,CM.E,M,P 



UNITED STATES 

Alabama 

Hewlett-Packard Co. 

700 Century Park Soutti, Suite 128 

B«IMINOHAM,AL 35226 

Tel: (205) 822-6802 

A,C,M,P* 

Hewlett-Packard Co. 
420 Wynn Drive 
HUNT$VILLE,AL 35805 
Tel: (205) 830-2000 
C,CM,E,M* 



Hewlett-Packard Co. 
3601 C St., Suite 1416 
ANCHOMQE,AK 99503 
Tel: (907) 563-8855 
C,E 

Arizona 

Hewlett-Packard Co. 
8080 Pointe Parkway West 
PHOEWICAZ 85044 
Tel: (602) 273-8000 
A,C.CM,E,M,P 

Hewlett-Packard Co. 
3400 East Britannia Dr. 
BIdg. C, Suite 124 
TUCSON, AZ 85706 
Tel: (602) 573-7400 
C,E,M" 

California 

Hewlett-Packard Co. 
99 South Hill Dr. 
BRISBANE, CA 94005 
Tel: (415) 330-2500 
C 

Hewlett-Packard Co. 

5060 E Clinton Avenue, Suite 102 

FRESNO, CA 93727 

Tel: (209) 252-9652 

CM 

Hewlett-Packard Co. 
1421 S. Manhattan Av. 
FUUERTON,CA 92631 
Tel: (714) 999-6700 
C,CM,E,M 

Hewlett-Packard Co. 
7408 Hollister Ave. «A 
60LnA,CA 93117 
Tel: (805) 685-6100 

C,E 

Hewlett-Packard Co. 
5400 W. Rosecrans Blvd. 
UWNDALE,CA 90260 
Tel: (213) 643-7500 
Telex: 910-325-6608 
CM 

Hewlett-Packard Co. 
2525 Grand Avenue 
Long Beacti, CA 90815 
Tel: (213)498-1111 
C 

Hewlett-Packard Co. 
3155 Porter Drive 
PALO ALTO, CA 94304 
Tel: (415) 857-8000 
CE 

H"wl8tt-Packard Co. 

4244 So. Market Court, Suite A 

SACRAMENTO, CA 95834 

Tel: (916) 929-7222 
A*,CE.M 



Hewlett-Packard Co. 
9606 Aero Drive 
SAN NEQCCA 92123 
Tel: (619) 279-3200 
C,CM,E,M 

Hewlett-Packard Co. 
5725 W. Las Posltas Blvd. 
Pleasanton, CA 94566 
Tel: (415) 460-0282 
C 

Hewlett-Packard Co. 
3003 Scott Boulevard 
SANTA CLARA, CA 95054 
Tel: (408) 988-7000 
Telex: 910-338^)586 
A,C,CM,E 

Hewlett-Packard Co. 
2150 W. Hillcrest Dr. 
THOUSAND OAKS, CA 91320 
(805) 373-7000 
C,CM,E 

Colorado 

Hewlett-Packard Co. 

2945 Center Green Court South 

Suite A 

BOULDER, CO 80301 
Tel: (303) 938-3005 

A,CE 

Hewlett-Packard Co. 
24 Inverness Place, East 
ENCLEWOOD, CO 80112 
Tel: (303) 649-5000 
A,C,CM,E,M 

Connecticul 

Hewlett-Packard Co. 
500 Sylvan Av. 
BRIDGEPORT, CT 06606 
Tel: (203) 371-6454 
CE 

Hewlett-Packard Co. 

47 Barnes Industrial Road South 

WALUNGFORD,CT 06492 

Tel: (203) 265-7801 

A,CCM,E,M 

Florida 

Hewlett-Packard Co. 
2901 N.W. 62nd Street 
FORT LAUDERDALE, FL 33309 
Tel: (306) 973-2600 
CE,M.P* 

Hewlett-Packard Co. 
6800 South Point Parkway 
Suite 301 

JACKSONVILLE, FL 32216 
Tel: (904) 398-0663 
C*,M" 

Hewlett-Packard Co. 
6177 Lake Ellenor Drive 
ORLANDO, FL 32809 
Tel: (305) 859-2900 
A,CCM,E,P* 

Hewlett-Packard Co. 
4700 Bayou Blvd. 
Building 5 

PENSACOLA,FL 32503 
Tel: (904) 476-8422 
A,CM 

Hewlett-Packard Co. 
5550 W. Idlewikl, ISO 
TAMPA, FL 33614 
Tel: (813) 884-3282 
CE,M,P 



Qcorgia 

Hewlett-Packard Co. 
2000 South Park Place 
ATUNTA,GA 30339 
Tel: (404) 955-1500 
Telex: 810-766-4890 
A,CCM,E,M,P* 

Hewlett-Packard Co. 
3607 Parkway Lane 
Suite 300 

NO«CROSS,GA 30092 
Tel: (404) 448-1894 
CE,P 

Hawaii 

Hewlett-Packard Co. 
Kawaiahao Plaza, Suite 190 
567 South King Street 
HONOLULU, HI 96813 
Tel: (808) 526-1555 
A,CE,M 

Idaho 

Hewlett-Packard Co. 
1 1309 Chinden Blvd. 
BOISE, ID 83707 
Tel: (208) 323-2700 
C 

Illinois 

Hewlett-Packard Co. 
304 Eldorado Road 
P.O. Box 1607 
BLOOMINGTON,IL 61701 

Tel: (309) 662-9411 
CM" 

Hewlett-Packard Co. 
525 W. Monroe, 1308 
CHICAGO, IL 60606 
Tel: (312) 930-0010 
C 

Hewlett-Packard Co. 
1200 East Diehl Road 
NAPERVILLE, IL 60566 
Tel; (312) 357-8800 
C 

Hewlett-Packard Co. 
5201 Tollview Drive 
ROLLRIG MEADOWS, IL 60008 
Tel: (312) 255-9800 
Telex: 910-687-1066 
A,CCM,E,M 

Indiana 

Hewlett-Packard Co. 
11911 N. Meridian St 
CARMEL, IN 46032 
Tel: (317) 844-4100 
A,C,CM,E,M 

Hewlett-Packard Co. 
3702 Rupp Drive 
FT. WAYNE, IN 46815 
Tel: (219) 482-4283 
CE 



Hewlett-Packard Co. 
4070 22nd Av SW 
CEDAR RAPIDS, lA 52404 
Tel: (319) 390-4250 
CE,M 

Hewlett-Packard Co. 
4201 Corporate Dr. 
WEST DES MOINES, lA 50265 
Tel; (515) 224-1435 
A",CM** 



Kansas 

Hewlett-Packard Co. 

7804 East Funston Road, 203 

WICHITA,KS 67207 

Tel: (316) 684-8491 

CE 

Kentucky 

Hewlett-Packard Co. 
10300 Linn Station Road, 100 
LOUISVILLE, KY 40223 
Tel: (502) 426-0100 
A,C,M 

Louisiana 

Hewlett-Packard Co. 
160 James Drive East 
ST. ROSE, LA 70087 
P.O. Box 1449 
KENNER, LA 70063 
Tel: (504) 467-4100 
A,CE,M,P 

Maryland 

Hewlett-Packard Co. 
3701 Koppers Street 
BALTIMORE, MD 21227 
Tel: (301) 644-5800 
Telex; 710-862-1943 
A,C,CM,E,M 

Hewlett-Packard Co. 
2 Choke Cherry Road 
ROCKVILLE, MD 20850 
Tel: (301) 948-6370 
A,C,CM,E,M 

Massachusetts 

Hewlett-Packard Co. 
1775 Minuteman Road 
ANDOVER, MA 01810 
Tel: (617) 682-1500 
A,CCM,E,M,P* 

Hewlett-Packard Co. 
32 Hartwell Avenue 
LEXINGTON, MA 02173 
Tel: (617) 861-8960 
CE 

Michigan 

Hewlett-Packard Co. 
4326 Cascade Road S.E 
GRAND RAPIDS, Ml 49506 
Tel: (616) 957-1970 
CM 

Hewlett-Packard Co. 

39550 Orchard Hill Place Drive 

NOVL Ml 48020 

Tel: (313) 349-9200 

A,CE,M 

Hewlett-Packard Co. 
1771 W. Big Beaver Road 
TROY, Ml 48084 
Tel: (313) 643-6474 
C 

Minnesota 

Hewlett-Packard Co. 
2025 W. Larpenteur Ave. 
ST. PAUL, MN 551 13 
Tel: (612)644-1100 
A.C,CM,E,M 

Missouri 

Hewlett-Packard Co. 

1001 E. 101st Terrace Suite 120 

KANSAS CITY, MO 64131-3368 

Tel: (816) 941-0411 

A,CCM,E,M 



Hewlett-Packard Co. 
13001 Hollenberg Drive 
BRIDGETON, MO 63044 
Tel: (314) 344-5100 
A,CE,M 

Nebrasica 

Hewlett-Packard 
10824 Old Mill Rd., Suite 3 
OMAHA, NE 68154 
Tel: (402) 334-1813 
CE,M 

New Jersey 

Hewlett-Packard Go. 
120 W. Century Road 
PARAMU$,NJ 07653 
Tel: (201) 265-5000 
A,CCM,E,M 

Hewlett-Packard Co. 
20 New England Av. West 
PISCATAWAY, NJ 08854 
Tel: (201) 562-6100 
A,C,CM,E 

New Mexico 

Hewlett-Packard Co. 
7801 Jetlerson N.E 
ALBUQUERQUE, MM 87109 
Tel; (505) 292-1330 
CE,M 

NewYorIc 

Hewlett-Packard Co. 
5 Computer Drive South 
ALBANY, NY 12205 
Tel: (518) 458-1550 
A,CE,M 

Hewlett-Packard Co. 
9600 Main Street 
CLARENCE, NY 14031 
Tel: (716) 759-8621 
CE 

Hewlett-Packard Co. 

200 Cross Keys Office Park 

FAMPORT.NY 14450 

Tel; (716) 223-9950 
A,C,CM,EM 

Hewlett-Packard Co. 
7641 Henry Clay Blvd. 
LIVERPOOL, NY 13088 
Tel: (315) 451-1820 
A,C,CM,E,M 

Hewlett-Packard Co. 
No. 1 Pennsylvania Plaza 
55th Floor 

34th Street & 8th Avenue 
MANHAHAN NY 10119 
Tel; (212) 971-0800 
CM* 

Hewlett-Packard Co. 
15 Myers Corner Rd. 
Hollowbrook Park, Suite 20 
WAPPMGER FALLS, NY 12590 
CM,E 

Hewlett-Packard Co. 
250 Westchester Avenue 
WHITE PLAINS, NY 10604 
Tel; (914) 684-6100 
CCM,E 

Hewlett-Packard Co. 
3 Crossways Park West 
WOODBURY, NY 11797 
Tel: (516) 682-7800 
A,CCM,E,M 



SALES & SUPPORT OFFICES 

Arranged alphabetically by country 



UNITED STATES (Cont'd) 

North Carolina 

Hewlett-Packard Co. 
305 Gregson Dr. 
CARY.NC 27511 
Tel: (919) 467-6600 
C,CM,E,M,P* 

Hewlett-Packard Co. 
9600-H Souttiern Pine Blvd. 
CHARLOTTE, NC 28210 
Tel: (704) 527-8780 
C* 

Hewlett-Packard Co. 
5605 Roanne Way 
GREENSBORO, NC 27420 
Tel: (919) 852-1800 
A,C,CM,E,M,P* 

Ohio 

Hewlett-Packard Co. 
2717 S. Arlington Road 
AKRON, OH 44312 
Tel: (216) 644-2270 

C,E 

Hewlett-Packard Co. 
23200 Ct»grin Bhd #100 
BEACHWOOD, OH 44122 
Tel: (216) 292-4677 
CP 

Hewlett-Packard Co. 
9920 Carver Road 
CINCMNATI, OH 45242 
Tel: (513) 891-9870 
CM 

Hewlett-Packard Co. 
16500 Sprague Road 
CLEVELAND, OH 44130 

Tel: (216) 243-7300 
A,CCM,E,M 

Hewlett-Packard Co. 
9080 Springboro Pike 
MAMSBURG, OH 45342 
Tel: (513) 433-2223 
A,CCM,E',M 

Hewlett-Packard Co. 

One Maritime Plaza, 5th Floor 

720 Water Street 

TOLEDO, OH 43604 

Tel: (419) 242-2200 

C 

Hewlett-Packard Co. 
675 Brooksedge Blvd. 
WESTERVILE, OH 43081 
Tel: (614) 891-3344 
CCM,E* 

Olilahoma 

Hewlett-Packard Co. 
3525 N.W. 56tti St. 
Suite C-100 

OKLAHOMA CITY, OK 731 12 

Tel: (405) 946-9499 
CE'.M 

Hewlett-Packard Co. 
3840 S. 103rd E. Ave., 100 
TULSA, OK 74146 
Tel: (918) 665-3300 
A",CE,M*,P* 



SEPT. 1985 



Oregon 

Hewlett-Packard Co. 
9255 S. W. Pioneer Court 
WILSONVILE, OR 97070 
Tel: (503) 682-8000 
A,CE*,M 

Pennsyhfania 

Hewlett-Packard Co. 
50 Dorchester Rd. 
HARRISBURG, PA 17112 
Tel: (717) 657-5900 
C 

Hewlett-Packard Co. 
1 1 1 Zeta Drive 
PTTTSBURGH, PA 15238 
Tel: (412) 782-0400 
A,C,E,M 

Hewlett-Packard Co 
2750 Monroe Boulevard 
VALLEY FORGE, PA 19482 
Tel: (215) 666-9000 
A,C,CM,E.M 

South Carolina 

Hewlett-Packard Co. 
Brookside Park, Suite 122 
1 Harbison Way 
CMUIilBIA,SC 29210 
Tel: (803) 732-0400 
CM 

Hewlett-Packard Co. 
555 N. Pleasanlburg Dr. 
Suite 107 

GREENVILLE, SC 29607 
Tel: (803) 232-8002 
C 

Tennessee 

Hewlett-Packard Co. 
One Energy Centr. 200 
Pellissippi Pkwy. 
KNOXVILLE,TN 37932 
Tel: (615) 966-4747 
A,C,M 

Hewlett-Packard Co. 
3070 Directors Row 
Directors Square 
MEMPHIS, TN 38131 
Tel: (901) 346-8370 
A,CM 

Hewlett-Packard Co. 

220 Great Circle Road, Suite 116 

NASHVUE,TN 37228 

Tel: (615) 265-1271 

CM,P* 



Texas 

Hewlett-Packard Co. 
1826-P Kramer Lane 
AUSTW,TX 78758 
Tel: (512) 835-6771 
CE,P* 

Hewlett-Packard Co. 
5700 Cromo Dr 
EL PASO, TX 799 12 
Tel: (915) 833-4400 
CE*,M** 

Hewlett-Packard Co. 
3952 Sandshell Drive 
FORT WORTH, TX 76137 
Tel: (817) 232-9500 
C 

Hewlett-Packard Co. 
10535 Harv«n Drive 
HOUSTON, TX 77036 
Tel: (713) 776-6400 
A,CE,M,P* 

Hewlett-Packard Co. 

511 E. John W. Carpenter Fwy. 

Royal Tech. Center 100 

RVING,TX 75062 

Tel: (214) 556-1950 

CE 

Hewlett-Packard Co. 
109 E. Toronto, Suite 100 
McALLEN,TX 78503 
Tel: (512) 630-3030 
C 

Hewlett-Packard Co. 
930 E. Campbell Rd. 
RICHARDSON, TX 75081 

Tel: (214) 231-6101 
A,CCM,E,M,P* 

Hewlett-Packard Co. 
1020 Central Parkway South 
SAN ANTONIO, TX 78216 
Tel: (512) 494-9336 
A,CE,M,P* 



Utah 

Hewlett-Packard Co. 
3530 W. 2100 South 
SALT LAKE CrrY,UT 841 19 

Tel: (801) 974-1700 
A,CE,M 

Virginia 

Hewlett-Packard Co. 
4305 Cox Road 
GLEN ALLEN, VA 23060 
Tel: (804) 747-7750 
A,CE,M,P* 

Hewlett-Packard Co. 

Tanglewood West BIdg. 

Suite 240 

3959 Electric Road 

ROANOKE, VA 24018 

Tel: (703) 774-3444 

CE,P 



Washington 

Hewlett-Packard Co. 
15815 S.E 37th Street 
8ELLEVUE,WA 98006 
Tel: (206) 643-4000 
A,CCM,E,M 

Hewlett-Packard Co 
708 North Argonne Road 
SPOKANE, WA 99212-2793 
Tel: (509) 922-7000 
C 

West Virginia 

Hewlett-Packard Co. 
501 56th 

CHARLESTON, WV 25304 
Tel: (304) 925-0492 
A,C,M 

Wisconsin 

Hewlett-Packard Co. 
275 N. Corporate Dr. 
BROOKFIELD, Wl 53005 
Tel: (414) 784-8800 
A,CE-,M 

URUGUAY 

Pablo Ferrando S.A.C. e I. 
Avenida Italia 2877 
Casilla de Correo 370 
MONTEVHEO 

Tel: 80-2586 
Telex: 802586 

A,CM,E,M 

Olympia de Uruguay S.A. 
Maquines de Oficina 
Avda. del Libertador 1997 
Casilla de Correos 6644 
MONTEVIDEO 
Tel: 91-1809, 98-3807 
Telex: 6342 OROU UY 
P 

VENEZUELA 

Hewlett-Packard de Venezuela CA. 

3A Transversal Los Ruices Norte 

EdiUcio Segre 2 & 3 

Apartado 50933 

CARACAS 1071 

Tel: 239-4133 

Telex: 261046 HEWPACK 

A,CCM,E,M,P 

Hewlett-Packard de Venezuela, CA. 

Centre Civdad Comercial Tamanaco 

Nivel C-2 (Nueva Etapa) 

Local 53H05 

Chuao, CARACAS 

Tel: 928291 

P 

Albis Venezolana S.R.L. 
Av. Las Marias, Ota. Alix, 
El Pedregal 
Apartado 81025 
CARACAS 1080A 
Tel: 747984, 742146 
Telex: 24009 ALBIS VC 
A 

Tecndogica Medica del Caribe, CA. 

Multicentro Empresarial del Este 

Ave. Libertador 

Edit. Libertador 

Nucleo "C" - Oficina 51-52 

CARACAS 

Tel: 339867/333780 
M 



Hewlett-Packard de Venezuela CA. 
Residencias Tia Betty Local 1 
Avenida 3 y con calfe 75 
MARACAIBO,EstadoZulia 
Apartado 2646 

Tel: (061) 75801-75806-75806- 
80304 

Telex: 62464 HPMAR 
CE' 

Hewlett-Packard de Venezuela CA. 

Urb. Lomas de Este 

Torre Trebol — Piso 1 1 

VALENCIA, Estado Carabobo 

Apartado 3347 

Tel: (041) 222992/223024 

CP 

YUGOSLAVIA 

Do Hermes 
General Zdanova 4 
YU-11000BEOGRAD 
Tel: 340 327, 342 641 
Telex: 11433 

A, CE,P 

Hermes 
Titova 50 

YU-61000 UUBUANA 
Tel: 324 856, 324 858 
Telex: 31583 
CE,M,P 

Elektrotehna 
Titova 51 

YU-61000 LJUBUANA 
CM 

ZAIRE 

Computer & Industrial Engineering 
25, Avenue de la Justice 

B. P. 12797 
KINSHASA, Gombe 
Tel: 32063 
Telex: 21552 

CP 

ZAMBIA 

R.J. Tilbury (Zambia) Ltd. 
P.O. Box 32792 
LUSAKA 

Tel: 215590 
Telex: 40128 
E 

ZIMBABWE 

Field Technical Sales (Private) Limited 

45, Kelvin Road North 

P.O. Box 3458 

HARARE 

Tel: 705 231 

Telex: 4-122 RH 

E,P 



Manual Part Number 64621-90903 

Printed in U.S.A., JUNE 1983 WHo^ HEWLETT 

Replaces: 64621-90901, March 1982 m^CM PACKARD