SERVICE MANUAL
PC40-ll |
C= commodore
COMPUTERS
SERVICE MANUAL
PC40-III
MARCH, 1989 PN-314134-01
CBM INTER-COMPANY
(NOT FOR RESALE)
Commodore Business Machines, Inc.
1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A.
Commodore makes no expressed or implied war-
ranties with regard to the information contained
herein. The information is made available solely on
_ anas is basis, and the entire risk as to quality and
- accuracy is with the user. Commodore shall not be
liable for any consequential or incidental damages
in connection with the use of the information con-
tained herein. The listing of any available replace-
ment part herein does not constitute in any case
a recommendation, warranty or guaranty as to
quality or suitability of such replacement part.
Reproduction or use without expressed permission,
of editorial or pictorial content, in any matter is
prohibited.
This manual contains copyrighted and proprietary information. No part
of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, electronic, mechanical,
photocopying, recording or otherwise, without the prior written permis-
sion of Commodore Electronics Limited.
Copyright © 1989 by Commodore Electronics Limited.
All rights reserved.
PC40-IIT SERVICE MANUAL
TABLE OF CONTENTS
SECTION 1 — SPECIFICATIONS
SECTION 2 — THEORY OF OPERATIONS
SECTION 3 — TROUBLESHOOTING GUIDE
SECTION 4 — PARTS
SECTION 5 — IC PINOUTS, SCHEMATICS
APPENDIX A — POWER SUPPLIES
APPENDIX B — DISK DRIVES
APPENDIX C — KEYBOARD
APPENDIX D — OPTIONS
APPENDIX E — TECHNICAL UPDATES
PC40-III SERVICE MANUAL
SECTION 1
SPECIFICATIONS
DESCRIPTION
PC40-III SERVICE MANUAL
This specification describes the Functional Requirements for the PC40-III computer. This system consists of a processor, memory,
control unit and keyboard. This system is compatible with the IBM AT series of computers. The monitor for the system is
an independent unit and must be VGA compatible.
STANDARD FEATURES
MICROPROCESSOR
SPEEDS
MEMORY CAPACITY
VIDEO OUTPUT
VIDEO DISPLAY RAM
PARALLEL OUTPUT
SERIAL OUTPUT
80286
6, 8, 12 MHz user selectable
1 MByte on board
Video Graphics Array compatible Horizontal scan frequency 31.5 KHz
256 KByte
Centronics (IBM) Compatible
RS-232 IBM Compatible
MOUSE PORT Commodore 1352 mouse Hardware and Software Compatible with Microsoft Bus
Mouse
AutoConfig BIOS
BATTERY BACKED UP CLOCK
EXPANSION SLOTS 3 AT style slots
1 XT style slot
40 MByte hard disk (formatted)
(AT style drive with embedded controller)
1.2 MByte Floppy Disk (formatted)
DISK STORAGE
112 WATT POWER SUPPLY
OPTIONAL FEATURES
Math Coprocessor 80287.
Disk and Tape storage
1 40 MByte hard disk drive inside the case.
1 5.25" 1.2 MByte floppy drive accessible from the front of the unit.
1 unused slot that can be used for a second floppy or a streaming tape unit.
Either or both floppy drives may be 3.5” drives.
Expansion slots
The three full length expansion slots conform to the standard AT bus structure, therefore, all options that are available for
the AT on the after sale market are available on this unit.
The one XT expansion slot is for short cards that do not require a full length slot.
VIDEO FEATURES
ALPHANUMERIC MODES
MODE # COL X ROW CHAR MATRIX RESOLUTION COLORS STANDARD
0, 1 40 X 25 8 X 8 320 X 200 16 CGA (1)
9X 16 360 X 400 16 OF 256K VGA (2)
2, 3 80 X 25 8X8 640 X 200 16 CGA (1)
9X 16 720 X 400 16 OF 256K VGA (2)
7 80 X 25 9X 14 720 X 350 MONOCHROME MDA
9X 16 720 X 400 MONOCHROME VGA (2)
54 132 X 43 7X9 924 X 387 COLOR ENHANCED
55 132 X 25 7X 16 924 X 400 COLOR ENHANCED
56 132 X 43 7X9 924 X 387 MONOCHROME ENHANCED
57 132 X 25 7X 16 924 X 400 MONOCHROME ENHANCED
IBM, AT and XT are registered trademarks of International Business Machine.
AutoConfig is a registered trademark of Commodore Business Machine.
1-1
GRAPHICS MODES:
MODE # RESOLUTION
4,5 320 X 200
6 640 X 200
D 320 X 200
E 640 X 200
F 640 X 350
10 640 X 350
11 640 X 480
12 640 X 480
13 320 X 200
NOTES
COLORS
4
4 OF 256K
2
2 OF 256K
16 OF 256K
16 OF 256K
MONOCHROME
16 OF 256K
2 OF 256K
16 OF 256K
256 OF 256K
(1) All 200 line modes are double scanned for 400 line resolution.
(2) The VGA implementation of these modes is the default.
VIDEO SIGNALS
Vertical Horizontal sync
Resolution Frequency Polarity
350 lines 31.5 KHz +
400 lines 31.5 KHz -
480 lines 31.5 KHz -
600 lines* 35.2 KHz -
Vertical sync
Frequency
70.1 Hz -
70.1 Hz +
59.9 Hz -
56.2 Hz -
*Requires an Analog MultiSync compatible monitor.
BLOCK MEMORY MAP
Standard Memory
640 KBytes range 0 to 655360 decimal (Oh to 9FFFFh)
384 KBytes range 1048576 to 1441792 decimal (100000h to 160000h)
The top 384 KBytes of memory can be disabled to function with third party add on boards.
KEYBOARD FEATURES
standard
United States ASCII 101
International 102 key
optional
Dvorak
Polarity
PC40-III SERVICE MANUAL
STANDARD
CGA (1)
VGA (1) & (2)
CGA
VGA (1) & (2)
VGA (1)
VGA (1)
VGA
VGA
VGA/MCGA
VGA
VGA/MCGA (1)
Special keyboards and drivers are available to customize the keyboard for the following countries.
Germany, Spain, France, Italy and the United Kingdom.
ADDITIONAL FEATURES
Numeric keypad
4 cursor keys in an inverted T formation
OTHER FEATURES
Security lock for keyboard lock out
Built in speaker
External Configuration switches
Battery backed-up real time clock/calendar.
Metal Case (can support monitor)
MultiSync is a registered trademark of NEC
1-2
PC40-III SERVICE MANUAL
SPEED SELECTION
One of the three operating speeds is selected by either a program or by the operator.
Default speed is 6 MHz. The operator or program can change the speed by issuing the following command strings.
Control Alternate S for standard 6 MHz
Control Alternate T for turbo 8 MHz
Control Alternate D for double 12 MHz
PHYSICAL SPECIFICATIONS
Height 5.75 inches 14.6 cm
Depth 15 inches 38.1 cm
Width 14 inches 35.6 cm
Weight 21 pounds 9.55 Kg
Minimum Clearances
Right side 4 inches 10.2 cm
Back side 4 inches 10.2 cm
ENVIRONMENT SPECIFICATION
ENVIRONMENTAL
—temperature—
Operational 4 to 40 C. (+39 to +122 F)
Storage —40 to +60 C. (-40 to +160 F)
Gradient +10 C/Hour (+18 F/Hour)
—humidity—
Relative 8% to 80% RH (no condensation)
Gradient 20% per Hour (no condensation)
Wet Bulb 26 C, 78 C (no condensation), maximum
VIBRATION
Operational 0.048 in. Dbl. Amplitude (5 - 17 Hz)
0.73 G, 17 - 150 Hz
0.33 G, 200 to 500 Hz
use linear interpolation for acceleration levels between 150 Hz and 200 Hz
Non-Operate 1.0 G, 5 - 2000 Hz, sweep of .067 decades/minute
SHOCK
Operational 10 G, 11 mS Half Sine Wave; any axis.
Non-Operate 50 G, 25 mS Square Wave; any axis.
25 G, 25 mS Square Wave; heads over data.
ALTITUDE
Operational — 457 to 2,972 Meters (— 1,500 to + 9,750 Ft)
Non-Operate — 457 to 12,192 Meters (—1,500 to +40,000 Ft)
ACOUSTIC NOISE 45 dBA at 1 meter
REGULATORY APPROVALS:
STANDARD DESCRIPTION
USA/Canada:
UL 478
Electronic Data Processing Units and Systems
FCC FCC Class B, Part 15 Subpart J
CSA 22.2 Data Processing Equipment, Consumer and Commercial Products.
EUROPE
VDE
IEC 435
PC40-IIT SERVICE MANUAL
SECTION 2
THEORY OF OPERATIONS
e SYSTEM BLOCK DIAGRAM .
e SYSTEM OVERVIEW
e NOTES — OPERATIONS GUIDE
PC40-I1I SERVICE MANUAL
SYSTEM OVERVIEW
(To be released)
2-2
PC40-III SERVICE MANUAL
NOTES FROM OPERATIONS GUIDE
AUTOCONFIG™
AUTOCONFIGuration is a unique feature of Commodore PC personal computers like the PC40-III, allowing the computer
to automatically sense additional peripheral devices plugged into the expansion bus. Once these additional devices are detected,
the resident peripherals on the PC40-III motherboard are adjusted so as not to conflict with expansion peripherals. The
AUTOCONFIG™ feature can prevent hardware damage to peripherals and motherboard, as well as ease the installation of
expansion cards.
The AUTOCONFIG™ process is described in this section.
Video
The PC40-III first examines the expansion bus for any expansion Advanced Video Adapter BIOS in the OC0000h — OC7FFFh
memory range. If an expansion video BIOS is found, then an external VGA or EGA controller is assumed to be on the bus
and the onboard VGA controller is disabled to avoid conflict. If an expansion video BIOS is not found, the video output
is configured in accordance with the default CONFIG Control video setting, as defined by the CONFIG dip switches 1, 2 and 3.
You can add an expansion MDA or CGA compatible controller in conjunction with the onboard VGA controller or provide
two video screens. (This makes many CAD packages easier to use.)
NOTE: When using the PC40-III’s onboard video controller, a VGA compatible monitor such as Commodore Models 1403
and 1450 (monochrome) or 1950 (color) must be connected to the 15 pin video output connector (no matter what video mode
you have selected).
If you want to use two video screens, there are several things you should remember. First, you should use a CGA, MDA or
compatible adapter — one that has no BIOS ROM of any kind.
Also, if you were to use an MDA/Herc adapter (monochrome) and you have the CONFIG switches set for VGA color, the
PC40-III will boot using your VGA monitor and you will see a blinking cursor on your monochrome monitor, indicating that
it has been initialized. If, while using the MDA/Herc adapter in the expansion port, you have the CONFIG switches on the
back of the System Unit set to MDA/Herc, your PC40-III will use the monochrome monitor as the boot monitor and the
VGA monitor will be initialized with the blinking cursor.
In either case, you can switch between the VGA and the monochrome monitors by using the MS-DOS MODE command.
The syntax for the MODE command is as follows:
¢ MODE MONO — sets the MDA as the default monitor
¢ MODE co80 — places the onboard VGA adapter into 80 column mode and sets it as the default monitor
¢ MODE co40 — places the onboard VGA adapter into 40 column mode and sets it as the default monitor
Serial Port (COMn:)
Before the onboard serial port is enabled a scan of the two standard COMn: hardware locations is made. If serial hardware
(serial card/modem) is found operational, possible bootup message(s) may be:
EXPANSION COM at 03F8h
and/or
EXPANSION COM at 02F8h
If both available COM: addresses are occupied by expansion boards, then the onboard serial port will not be enabled. The
onboard serial port will be configured and tested at I/O address 03F8h if no expansion COM:’s are found and will be con-
figured and tested to the unused COM: address if only one expansion COM: is found.
If the onboard serial port is configured and tested successfully a message will be output during bootup:
ONBOARD COM at 03F8h
or
ONBOARD COM at 02F8h
2-3
PC40-IIT SERVICE MANUAL
Parallel Port (LPTn: or PRN:)
Before the onboard parallel port is enabled a scan of the three standard LPTn: hardware locations is made. If parallel hard-
ware (e.g., a printer card) is found operational, possible bootup message(s) may be:
EXPANSION LPT at 0378h
and/or
EXPANSION LPT at 0278h
and/or
EXPANSION LPT at 03BCh
If all available LPT: addresses are occupied by expansion boards, then the onboard parallel port will not be enabled. The
onboard parallel port will be configured and tested at I/O address 03BCh if no expansion LPT:’s are found, and will be con-
figured and tested to the unused LPT: address if two expansion LPT:’s are found. If only one expansion LPT: is found, the
onboard parallel port will be enabled to the first available I/O address, when searching in the following sequence:
03BCh, 0378h, 0278h
If the onboard parallel port is configured and tested successfully, a message will be output during bootup:
ONBOARD LPT at 03BCh
or
ONBOARD LPT at 0378h
or
ONBOARD LPT at 0278h
Mouse Port
Acheck is made for a standard Microsoft Bus Mouse. If it is found in the I/O channel then the onboard Microsoft compatible
mouse hardware is never enabled. The following message will appear during bootup:
EXPANSION MOUSE at 023Ch
If no expansion mouse is found the onboard mouse is enabled and tested. If mouse is operational then the following message
will appear during bootup:
ONBOARD MOUSE at 023Ch
NOTE: The onboard mouse hardware is enabled/tested independent of the presence of the actual mouse. The bootup messages
will appear even if the Commodore PC Mouse Kit is not attached.
80287 Numeric Coprocessor
A test is made for the presence of an 80287 Numeric Coprocessor during bootup. If an 80287 is detected the following message
will be output:
80287 Numeric Coprocessor
NOTE: 80287 coprocessors are available in 5, 6, 8 and 12 MHz speeds. However, the units are downwardly compatible only
— for example, an 8 MHz coprocessor will function if the PC40-III is running at 6 or 8 MHz, but a 6 MHz unit will not
function properly if the PC40-ITI is running at 12 MHz. In order to use the 80287 at all three CPU speeds (6, 8, 12 MHz),
an 80287-8 (an 8 MHz part) is necessary.
NOTES FOR THE PROGRAMMER
It is possible to override the configuration done at bootup. We STRONGLY recommend that only advanced programmers
with experience with low-level hardware/software interaction attempt this.
NOTE: If software override of the default configuration is performed, the presence of any expansion hardware should be
taken into account to prevent hardware conflict resulting in damage of the expansion hardware or the PC40-III motherboard.
Configuration is performed via the COMMODORE CONFIGURATION REGISTER at I/O address 0230h. This register is
read/write with only bit7 changing its meaning from read to write. The register values are shown in the following table.
2-4
PC40-III SERVICE MANUAL
COMMODORE CONFIGuration REGISTER — I/O addr 230h
[rw | bie? | vito | vies | bite | bits | viz | bitr [dito |
Ww venb’ rtc Xx mouse com! com0 1pto
mono — indicates that the onboard video adapter is setup as a monochrome adapter when high, color when low.
venb’ — when set low the onboard video adapter will be enabled.
rte © — when set high the onboard real-time clock will be enabled.
x — this bit is reserved for future use.
mouse — when set high the onboard mouse will be enabled.
coml1 _com0 Iptl__1ptd
low low — onboard serial port is disabled. low low — onboard parallel port is disabled.
low high — serial port enabled at I/O addr 02F8h low high — parallel port enabled at I/O addr 03BCh
high low -— serial port enabled at I/O addr 03F8h high low — parallel port enabled at I/O addr 0378h
high high — this configuration is reserved. high high — parallel port enabled at I/O addr 0278h
THE PC40-11 HARDWARE CONFIGURATION
Using the PC40-III Setup Utility
Once MS-DOS has finished booting and the C> prompt has appeared, you can use the built-in Setup utility to give the system
detailed information on your PC40-III configuration. To run the Setup utility, hold down the Control and Alt keys and
simultaneously press the Esc key. The main menu of the Setup utility will appear and will look like this:
Commodore Setup Utility
Date 23.08.88 Hard Disk Type Information
Time 14:23:08
Diskette 1 1.2M
Diskette 2 NONE
Hard Disk 1 28
Sma dceuit 940 17 512 940 62MB
: 940 17 512 940 46¢B
oprocessor NONE 615 17 NONE 615 20MB
Base Memory 640 KB 462 17 256 511 30MB
Extended Memory 584 KB 733 17 NONE 733 30MB
Base memory found: 640 KB 900 17 NONE 901 112MB
Extended memory found: 384 KB 820 17 NONE 820 20MB
Use |, | to select items 855 17 NONE 855 35 MB
Use +,¢ to select predefined 855 17 NONE 855 49MB
values 306 17 128 319 20MB
Use <PgDn> to view more hard disk 733 17 NONE 733 42MB
types 0 0 0 0 0 MB
Press <Esc> to abort SETUP 612 17 0 635 20MB
Press <End> to exit and update
Type Cyln Head Sect W-pc L-zone Size
306 17 128 305 10MB
615 17 300 615 20MB
615 17 300 615 30MB
PON DNIANNANYNDWhDOODHD HS H&
COMMODORE SETUP UTILITY MAIN MENU
2-5
PC40-III SERVICE MANUAL
As noted on the Setup screen, you can use the cursor keys and the keyboard to define or change the system configuration,
as follows:
¢ Use the up and down cursor keys to move from option to option in the main menu.
© Use the left and right cursor keys to select the predefined entries for each option.
© Use the keyboard to type in any information that is not predefined.
© Use PgDn to tell the pulldown menu (see Figure below) to display additional hard disk types.
Following is specific information about the various Setup menu options.
Setting the Date and Time for the Real Time Clock/Calendar
The PC40-III has a Real Time Clock/Calendar with a battery backup. This means that once set, the clock/calendar will keep
the correct date and time even when the computer is turned off. You use the first two lines of the Setup Utility to set the
Real Time Clock/Calendar, as follows:
Date: Allows you to set the correct date into the Real Time Clock. This option does not have any predefined entries; simply
enter the date from the keyboard, in the format dd/mm/yy.
Time: Allows you to set the correct time into the Real Time Clock, without invoking MS-DOS. This option also does not have any
predefined entries; simply enter the time from the keyboard, in the format hh:mm:ss, where hh = 00-23,mm =00-59,and ss = 00-59.
Setting the Floppy Disk Drive Options
You can have a maximum of two floppy diskettes configured into your PC40-III. The next two Setup menu options, Diskette 1
and Diskette 2, allow you to tell the system how many floppy drives are available and what type they are. Here’s how to set
these options:
Diskette 1: Predefined entries: None, 360 Kb 5.25, 1.2 Mb 5.25, 720 Kb 3.5, 1.44 Mb 3.5. The floppy drive in your PC40-III
is always considered Diskette 1. Since PC40-III is equipped with a high density (1.2 MB) drive, select 1.2 Mb 5.25 for Diskette 1.
Diskette 2: Predefined entries: None, 360 Kb 5.25, 1.2 Mb 5.25, 720 Kb 3.5, 1.44 Mb 3.5. If you have not installed a second
floppy drive in your PC40-III, select None for Diskette 2. If you have installed a second floppy drive, select whichever drive
type (360 Kb 5.25, 1.2 Mb 5.25, 720 Kb 3.5, 1.44 Mb 3.5) applies to the installed drive.
Setting the Hard Disk Drive Options
Hard Disk 1 and Hard Disk 2, the next two options in the Setup utility, define how many hard disk drives are available and
what kind of hard disk drives they are. Hard disk drives are identified by a pre-assigned Drive Type (1, 2, etc.). This number
tells the PC40-III the drive manufacturer and capacity.
Commodore Setup Utility
Date 23.08.88 Hard Disk Type Information
Time 14:26:26 Type Cyln Head Sect W-pc L-zone Size
Diskette 1 1.2 17 977 17 300 977 40MB
Diskette 2 NONE 18 977 17 NONE 977 56MB
Hard Disk 1 28 19 1024 17 512 1023 59NB
Hard Disk 2 NONE 20 733 17 300 732 30NMB
Video SPECIAL 21 733 17 300 732 42MB
Coprocessor NONE 22 733 17 300 733 30MB
Base Memory 640 KB 23 306 17 0 336 10MB
Extended Memory 384 KB 24 805 26 O 820 40MB
Base memory found: 640 KB 25 776 33. =«-0)~=— 800 «100 MB
Extended memory found: 384 KB 26 745 28 0 800 40MB
Use ft, | to select items 27 625 a") eh. a
Use >,< to select predefined 28 17 1000 40 MB
0
0
0
anh orhhonyndanryio
values 29 965 10 17 1000 80 MB
Use <PgDn> to view more hard disk 30. 782 064 «(28 800 42MB
types 31 00 O 0 OMB
Press <Esc> to abort SETUP 32 00 0 0 OMB
Press <End> to exit and update
SETUP UTILITY PULLDOWN MENU FOR HARD DISK DRIVE TYPE
2-6
PC40-IIT SERVICE MANUAL
Here’s how to define your hard disk configuration:
Hard Disk 1: Your PC40-III comes equipped with a 40 MB hard disk drive. This drive is always considered Hard Disk 1.
The Drive Type for this drive is shown on a sticker located on the back of your System Unit. Find this number and type it
in after Hard Disk I.
The PC40-III Setup utility includes a menu of hard disk drive types with their individual ID numbers. You can page through
the menu by pressing the PgDn key. For example, the opening Setup screen on Page 2-3 lists drive types 1 through 16. If
you press PgDn, the Setup screen will be as shown on Page 2-4, with drive types 17 through 32 listed.
Hard Disk 2: This option is not supported by the onboard controller.
Other Setup Options
Video: Tells system what the default video is. Factory-set default is special. To change this setting, see the permissible default
modes listed in Appendix H.
Coprocessor: Tells system if an 80287 Numeric Coprocessor (NCP) is installed. Factory-set default is mone. Select Yes if you
have installed an 80287 Numeric Coprocessor (see Appendix N for information on using an 80287 Numeric Coprocessor).
Base memory: Lets you customize base memory for specific applications.
Extended Memory: Tells system how much extended memory is available. The default 384 Kbytes of extended memory can
be enabled or disabled as required by setting the CONFIG Control dip switch 4.
SETTING THE MICROPROCESSOR CLOCK SPEED
The 80286 microprocessor in the PC40-III is capable of running at three different clock (i.e., processor or CPU) speeds:
e Standard speed = 6 Mhz
¢ Turbo speed = 8 MHz
© Double speed 12 MHz
The PC40-III is preset to the standard 6 MHz speed. You can switch between the clock speeds by using special key combina-
tions or by using the MS-DOS ATSPEED command.
To set the clock speed from the keyboard, use these key sequences:
e CTRL-ALT-S for standard speed (6 MHz)
¢ CTRL-ALT-T for turbo speed (8MHz)
e CTRL-ALT-D for double speed (12 MHz)
NOTE: Some software may require that you select standard or turbo speeds for normal operation.
To set the clock speed using the ATSPEED command, first make-sure the MS-DOS prompt is showing on the screen. Then
type the word ATSPEED, followed by a space, a dash (—), and then a letter (S, T, or D) denoting the desired speed. For
instance, if you are in standard speed and you want to change to turbo speed (8 MHz), type the following and press Enter:
ATSPEED —T
Extended Memory Dip Switch
Dip switch 4 enables or disables the 384K of extended memory in the PC40-III.
ENABLE EXT. MEM. [if
DISABLE EXT. MEM.
4
THE RESET SWITCH
The Reset switch protrudes slightly on the right side of the machine, just behind the keyboard connector. The switch provides
an alternative to cycling power when an application program may have ‘‘crashed”’ the computer. Pressing this switch will
effectively reboot the computer as if the power had been cycled OFF and then ON. All information in the computer’s RAM
memory will be lost. Be careful not to press this button during disk access, or you may lose information that was being written
to mass storage devices (e.g., hard disks or floppy disks) while the switch was depressed.
2-7
PC40-III SERVICE MANUAL
OOFFFF
0A0000
OBFFFF
0c0000
OCFFFF
008000
1MB
OEFFFF
0F0000
INTERNAL USE
0F8000
32K AT ROM BIOS
OFFFFF
100000
384K RAM (EXTENDED MEMORY)
1SFFFF
15MB
PC40-I11 MEMORY MAP
PC40-III SERVICE MANUAL
JUMPER SETTINGS ON MOTHERBOARD
PAD 301 JMP 903
PAD 302 JMP 904
Jumper Locations on Motherboard
| JUMPER _ FUNCTION DEFAULT RESULT
JMP 903 Disable HD Not Installed HD Installed
JMP 904 HD Type Location A Conner HD
Location B Quantum HD
PAD 301 80287 Clock Mode | +3Mode 8 MHz Part runs up to 12 MHz
PAD 302 80287 Clock Speed CPU Clock (+3) 8 MHz Part runs up to 12 MHz
PAD 301 & PAD 302 may be changed to take full advantage of using a 12 MHz 80287. This is a dealer installation only.
IRQ Vectors Used in the PC40-IiT
PC40-III SERVICE MANUAL
There are two interrupt controllers on the PC40-III:
CPU
Interrupt
Cascade 2
IRQ 0 — System Timer (built-in)
1 — Keyboard (built-in)
2 — Cascade #2
3 — COM2 (built-in or expansion)
4 — COMI (built-in or expansion)
5 — XT Compact HD (unused)
6 — Floppy (built-in)
7 — LPT1,2,3 (All ports: built-in plus expansion)
IRQ 8 — Real Time Clock
9 — Onboard Mouse
10 — Unused
11 — Unused
12 — Unused
13 — Unused
14 — AT Hard Disk (built-in or expansion)
15 — Unused
2-10
PC40-III SERVICE MANUAL
SECTION 3
TROUBLESHOOTING GUIDE
TECHNICAL SERVICE NOTES
IMPORTANT:
¢PC40-III PCB’S RETURNED FOR CREDIT MUST BE SHIPPED IN AN ANTI-STATIC BAG, AVAILABLE
THROUGH THE COMMODORE PARTS DEPT. ANY PCBS RETURNED FOR CREDIT BY SERVICE
CENTERS WHICH ARE NOT PACKAGED CORRECTLY WILL BE SENT BACK TO THE SERVICE CENTER
AND NO CREDIT WILL BE ISSUED.
¢PC40-III HARD DRIVES RETURNED FOR CREDIT MUST BE INSERTED IN AN ANTI-STATIC BAG AND
PACKED IN A COMMODORE SPECIFIED HIGH DENSITY FOAM SHIPPING BOX, BOTH AVAILABLE
THROUGH THE PARTS DEPT. FAILURE TO DO SO WILL VOID WARRANTY.
COMPONENT REPAIR:
PC40-III MAIN BOARD IS A MULTI-LAYERED PCB ASSEMBLY. COMPONENT REPAIR BEYOND THE
SOCKETTED CHIP LEVEL RESULTING IN NON-REPAIRABLE DAMAGE WILL VOID WARRANTY. USE
STATIC PRECAUTIONS WHEN SERVICING THIS PCB ASSEMBLY.
10.
11.
12.
13.
14,
15.
16.
17.
18.
19.
20.
21.
22.
23.
PC40-III SERVICE MANUAL
TROUBLESHOOTING ERROR MESSAGES
Error Messages
. DMA 1 error
. DMA 2 error
. Interrupt controller 1 error
. Interrupt controller 2 error
. PIO error
. Parity error
. Real time clock is not working
. Illegal shutdown code in CMOS
. Virtual Mode CPU error
Parity error on main circuit board
Parity error on expansion bus
Non-recoverable error-Processor halted
Press F1 key to continue
Battery Failure
Base memory configuration error
Extended memory configuration error
Floppy 0 configuration error
Floppy | configuration error
Coprocessor (80287) configuration error
The realtime clock has not been initialized
Keyboard
Key switch is off. Turn it on to continue
Boot failure, check disk and hit any key to
try again
Troubleshooting Guide
Customer Response
See your dealer
See your dealer
See your dealer
See your dealer
See your dealer
See your dealer
See your dealer
See your dealer.
See your dealer
See your dealer
See your dealer
See your dealer
Press F1 key
Run Setup Utility/See your dealer
Run Setup Utility
Run Setup Utility
Run Setup Utility
Run Setup Utility
Run Setup Utility
Run Setup Utility
Check keyboard
Turn keylock on
Check for non-MS-DOS disk in
Drive A:; run Setup Utility
Test OB
Test 0C
Test OD
Test OE
Test OF
Test 10
Test 1E
Test 02
Test 26
Misc
Misc
Misc
Misc
Test 11
Test 17
Test 18
Test 1A
Test 1A
Test 1D
Test 1E
Test 14
Misc
Service POD Test (H)
3-1
PC40-II SERVICE MANUAL
POWER ON DIAGNOSTICS
PC40-III Trouble Shooting — Section 3
The Commodore 80286 ROM bios contains a ‘‘Power on Diagnostic’? program which tests the functions of hardware and
checks the configuration prior to passing control to the operating system.
The number of the test routine being run is passed to addr 03 78 (H) prior to the start of each test section.
The 80286 processor is initialized by the ‘‘RESET”’ signal. Refer to RESET description in IC pinout section, note that ““VCC”’ and
“CLK” to CPU must be correct and ‘‘HOLD”’ must not be active for 34 ticks from leading edge to trailing edge of initial reset.
RESET will terminate all instruction execution and local bus activity until it is negated. Prior to fetching, decoding and executing,
the first instruction, located at physical address FF FF FO (H), the 80286, in real address mode, processes some micro code
located in its internal ROM, this takes about 38 ticks.
Test 01 (H) 0000 0001 (B)
The first test performed by the power on diagnostic checks the 8088 flags, the arithmetic logical unit, and the CPU registers.
If a failure is detected in Test 01, a ‘‘HALT”’ instruction is executed. This will stop program execution and prevent the CPU
from using the local bus. The 80286 can be forced out of the halted state by ‘‘RESET”’’, ‘NMI’ or “INTR”’ (when “INTR”’
is used for RESTART, the interrupt enable bit of flag register must be on (set to 1), and the effective address computed from
CS:IP will point to the next instruction after the halt instruction).
***Failure in test 01 indicates defective 80286.
Test 02 (H) 0000 0010 (B)
This routine checks to see if a ‘“SHUTDOWN”’ has occurred. A shutdown can indicate a severe error which would prevent
the CPU from further processing.
NOTE: A halt or shutdown condition is signaled externally, by the 80286 as a bus operation. Low states on SO’, SI’, COD/INTA’,
and a high state on M/IO’ indicate a halt or shutdown. The state of address line 1 will indicate which condition, Al
high is halt, Al low is shutdown.
After the test number is moved to the parallel port a check for keyboard reset is conducted and the program branches to test
04 (H) if it has.
The check for shutdown begins by examining the 8242 keyboard controller status port. In all ten shutdown conditions are
tested, of these, three unexpected shutdown conditions, numbers 6, 7 or 8, any one of which if true, will generate the console
message:
‘Illegal Shutdown Code in CMOS”’
NOTE: Branch information for shutdown routines are stored in CMOS memory. The shutdown command is sent to the 8242,
the UPI status port, which will halt the CPU. Return depends on the shutdown code in CMOS memory.
An error code, F6, F7 or F8, (HEX) is sent to the parallel port before calling the display routine which generates the above
message.
In real address mode a shutdown could occur under the following conditions:
Interrupt number 8, interrupt number 13, or a ““CALL INT’’ or ‘‘PUSH”’ instruction which wraps stack segment when SP
is ODD.
Routines also perform valid shutdowns to exit protected mode. During these the DMA page register will be initialized and
interrupt control words (ICW) 1, 2, 3 and 4 will be reinitialized. Other routines within the test enable ‘‘NMI’’, parity and
set the I/O check bit.
***Failures in test 02 could indicate problems on the local bus, or expansion bus. This would include: 80286, FE3000, FE3010,
or any third party cards.
Test 03 (H) 0000 0011 (B)
Eprom checksum test verifies contents of eprom by adding bytes and checking for result of zero. A compensation byte is fac-
tored into the addition to make the sum zero.
Detection of an error results in a halt condition and would invalidate tests 01 and 02.
***Failure in test 03 indicates defective ROM.
PC40-III SERVICE MANUAL
Test 04 (H) 0000 0100 (B)
Test 04 checks the DMA page registers by writing and reading bits starting at address 80 (H).
***Failure in test 04 indicates possible defective FE3010, or local bus.
Test 05 (H) 0000 0101 (B)
Timer 1 and timer 2 are checked for correct operation. Interrupts are masked off during the test.
***Failure in test 5 indicates possible defective FE3010.
Test 06 (H) 0000 0110 (B)
Memory refresh test. Timer and DMA are setup to initiate refresh cycles every 15.1 microseconds. Size of virual memory is
calculated.
***Failure in test 06 indicates possible FE3010, Refresh logic or memory problem.
Test 07 (H) 0000 0111 (B)
Test 07 checks the 8242 keyboard controller by writing and reading the keyboard buffers.
***Failure in test 07 indicates possible defective 8242 or associated circuitry.
Test 08 (H) 0000 1000 (B)
Test 08 writes and reads the first 128K of RAM and verifies block size is 128K. First pass writes addresses into data, the second
pass writes the complement of the address into data. Memory is cleared after test. The battery status is also confirmed in test 08.
***Failure in test 08 indicates possible defective RAM or RAM logic.
Test 09 (H) 0000 1001 (B)
Test and configure video. A search is made to determine if MDA, CGA or a special video adapter is configured, if not the
onboard VGA is enabled and a call to VGA bios is executed. The dip switches are read to determine the default video mode.
NOTE: The mode register setting in the 5720 controls the reset signal to the onboard VGA controller chip. If no special video
adapters are found on the expansion bus then ‘‘NOVID’”’ from the 5720 to the PVGA is negated.
On completion of this test the title and copyright message are displayed.
Test 0A (H) 0000 1010 (B)
Test RAM from 128K to 640K. A display message is generated indicating that the base RAM of 128K, Test 08, is OK.
Blocks of 128K, starting at 128K are then tested by writing, reading and verifying RAM. The first pass writes addresses to data,
that is, the address which defines the physical location is also used as the bit pattern that is being written. The second pass writes
complement of address into data.
The test displays results in blocks of 128K to the console each time a 128K boundary is reached.
At completion of the onboard memory test the CPU is placed in virual mode and a test for virtual memory (over 1 MEG) is started.
NOTE: See test 26 (H).
***Failure in test OA indicates a defective RAM.
Test 0B (H) 0000 1011 (B)
DMA controller #1 register check.
NOTE: Appendix L of the PC40-III operator guide lists error messages starting with this test, see page 85 of operations guide
part number 319983-01.
Four current address registers (16 bits wide, each) and four current word count registers (16 bits wide, each) for each of the
four DMA channels are written to and read from to verify operation.
A failure in test OB will generate the following display on the console:
‘SDMA I error’
The beeper will sound, and a halt instruction will be executed.
***Failure in test OB indicates A defective FE3010.
3-3
PC40-III SERVICE MANUAL
Test OC (H) 0000 1100 (B)
DMA controller #2 register check. The second functional 8237 containing four current address registers (16 bits wide, each)
and four current word count registers (16 bits wide, each) within the FE3010 are written to and read from to verify operation.
Successful completion of the test OC will set the modes for DMA channels 0 through 3 and enable cascading by channels 4,
5 and 6 (DMA 1). : :
A failure in test OC will generate the following display on the console:
‘SDMA 2 error’’
The beeper will sound, and a halt instruction will be executed.
***Failure in test OC indicates a defective FE3010.
Test 0D (H) 0000 1101 (B)
Interrupt controller #1 test. Patterns are written to, and read from the interrupt mask register (IMR) which controls the inter-
rupt request register (IRR).
A verification is made that no interrupts can occur if ‘‘IMR”’ is set to FF (H). A vector is initialized to a temporary interrupt
service routine in the event of a failure.
A test for correct timer 0 interrupt is also made.
A failure in test OD will generate the following display on the console:
‘Interrupt controller 1 error’’
The beeper will sound, and a halt instruction will be executed.
***A failure in test OD indicates a defective FE3010.
Test OE (H) 0000 1110 (B)
Interrupt controller #2 test. The second functional 8259 contained in the FE3010 is tested as in test OD, without timer test.
A failure in test OE will generate the following display on the console:
‘Interrupt controller 2 error’’
The beeper will sound, and a halt instruction will be executed.
***A failure in test OE indicates a defective FE3010.
Test OF (H) 0000 1111 (B)
Check peripheral in/out register. Write and read from PIO register.
A failure in test OF will generate the following display on the console:
**PIO error’
The beeper will sound, and a halt instruction will be executed.
***A failure in test OF indicates a defective FE3010.
Test 10 (H) 0001 0000 (B)
RAM parity test. Blocks of RAM are written to and read from, parity check for odd parity is made. Parity disabled after
successful test.
NOTE: PC40-III does not use parity, third parity boards that use parity will enable parity.
‘NMI’? is enabled and a service routine for a parity error generates the following console message.
‘‘Parity error’
The beeper will sound, and a halt instruction will be executed.
***Failure in test 10 indicates a defective RAM, third party card, NMI, or local bus.
Test 11 (A) 0001 0001 (B)
Test CMOS clock for battery failure and checksum failure.
Beeper will sound if failure is detected. Console will display:
‘‘Battery failure’? or ‘“CMOS checksum failure’? or both.
***Failure of test 11 indicates a defective battery, defective oscillator, or M146818A.
3-4
PC40-III SERVICE MANUAL
Test 12 (H) 0001 0010 (B)
This test is disabled. It is used only in manufacturing tests.
The beeper will sound for a set length prior to the start of test 13 (H). In a system which has passed all tests to this point
the beeper sound heard now would be the one heard in the power up routine.
Test 13 (H) 0001 0011 (B)
Setup interrupt controller and move vector tables to RAM. Vector addresses are fetched from top 8K module.
NOTE: Vectors for video were setup in test 09.
Master and slave interrupts are enabled at this point.
Test 13 does not create any error messages.
Test 14 (AH) 0001 0100 (B)
Keyboard test. Functional test of the 8242 keyboard controller at U203. A test for a stuck key on keyboard is performed.
Check is made to see if key lock is locked.
A failure in test 14 will display the following error message on console:
‘*Keyboard error’’
***Error indicates a defective 8242 controller or a defective keyboard.
Test 15 (H) 0001 0101 (B)
Test and configure the parallel port. Parallel port addresses are setup, reads and writes to ports are done. Set time out.
No error messages are generated by this test.
NOTE: PPC1 at U602 controls parallel output.
Test 16 (H) 0001 0110 (B)
Configure serial COM1 and COM2 for 8250 at U604. Read serial interrupt ID, set number of serial channels.
No error messages are generated by this test.
Test 17 (FD) 0001 0111 (B)
Configure memory less than 640K. Parity (for EXPANSION RAM) is enabled.
Memory was tested in test OA, and ‘““CMOS STATUS”? set. A check for a warm boot (ALT/CNTRL/DEL) is made and a
comparison of the old and new memory configuration is performed. If a memory size mismatch is detected, the beeper will
sound and the following non-fatal error message will be displayed on the console:
‘*Base memory configuration error’
The new configuration is stored.
***Check the settings for RAM size in the setup utility if you encounter this message.
Test 18 (H) 0001 1000 (B)
Configure memory over 1 megabyte (virtual memory). Check is made on address line 20, a low indicates virtual address mode.
CMOS status is checked as in test 17, a memory size mismatch will sound the beeper and generate the following non-fatal
error message on the console:
‘*Extended memory configuration error’
The new configuration is stored.
***Check the settings for RAM size in the setup utility if you encounter this message.
Test 19 (H) 0001 1001 (B)
Configure keyboard test. Setup keyboard buffers, enable keyboard interrupt and test if key switch is turned to the on position.
If the key switch is off the following message will be displayed on the console:
‘*Key switch is off. Turn it on to continue.’’
NOTE: You are in a loop until you turn on the key switch.
PC40-III SERVICE MANUAL
Test 1A (H) 0001 1010 (B)
Configure the floppy disk drive. Calculate number of floppy drives present. Check drive type, compare settings stored in CMOS,
if a mismatch the following message will be displayed on console:
‘“‘Floppy 0 configuration error’’
***Check settings in setup utility if above message is displayed.
Test checks second floppy configuration, if a mismatch the following message will be displayed on the console:
“Floppy 1 configuration error’’
***Check settings in setup utility if above message is displayed.
New configuration is stored in CMOS. Floppy interrupt is enabled.
NOTE: Refer to installation instructions when adding a second floppy to the system. It may be necessary to change jumpers
on drive for proper operation.
Test 1B (H) 0001 1011 (B)
Configure the hard drive. Check configuration if a mismatch hard drive will not be setup.
No error message is generated.
Test 1C (H) 0001 1100 (B)
Test number is not moved to parallel port for this configuration. This routine only turns on the game card bit in the ‘““EQUIP
FLAG’’.
No error message is generated.
Test 1D (H) 0001 1101 (B)
Configure 80287 coprocessor. Check if 80287 is present. Enable 80287 interrupt and set ‘‘EQUIP FLAG” if it is.
Compare configuration with CMOS, store new configuration, beep the speaker, and display the following message is setup
changed.
‘*.. Coprocessor (80287) configuration error’’
***Check setup utility for correct settings if this message is displayed.
Test 1E (H) 0001 1110 (B)
Check CMOS clock to see if it was initialized and is working. Enable timer interrupt. Sound beeper, and initialize if failure
detected, then display one of the following messages on the console:
‘‘.. The Real Time Clock has not been initialized’
OR: ‘*.. Real Time Clock error’’
***Check the RTC chip, M146818A at U201 if second message above is displayed.
Test 1F (H) 0001 1111 ®)
Generate a new CMS checksum and save it in CMOS RAM. Call made to auto configuration program at this point.
No error message generated.
Test 20 (H) Not Implemented
Test 21 (H) 0010 0001 (B)
Initialize ROM drivers, including hard drive. Checksum generated, and all ROMS tested.
System will now begin boot up.
System speed is determined, 6 MHz, 8MHz or 12MHz.
***Refer to operations manual for opening screen display.
Tests 22, 23 Not Implemented
PC40-III SERVICE MANUAL
Test 24 (H) 0010 0100 (B)
Test operation of the RTC chip. Recheck battery, make sure clock is counting, test memory.
System will execute a halt instruction on memory failure. No error message is generated.
Test 25 (H) 0010 0101 (B)
Used in manufacturing to loop through diagnostics.
Test 26 (H) 0010 0110 (B)
Virutal memory test (over 1 megabyte). Call made to this routine from test 09.
Display Message: ‘‘Testing Extended RAM”’
Display Message: ‘‘Total System RAM = XXXX°”’ at finish.
During this test the exception interrupt vector tables and descriptor tables are built, and moved from ROM to RAM.
A test of address line 20 is made (controls real or virtual CPU mode). If not in virtual mode display following message:
“Test __ 26: Virtual Mode CPU error’’
And send F3 (H) (1111 0011 to parallel port. Then execute a halt instruction.
Test address lines 19 through 23 are tested. Shutdown if error. Exception interrupt codes are moved to the parallel port prior
to shutdown. The following list defines the code sent to the port and the type of exception interupt ( EXECP INT ).
81 (H) EXECPINT 01 Single Step
82 (H) EXECPINT02 NMI
83 (H) EXECP INT 03 _Breakpoint
84 (H) EXECP INT 04 Into Detect
85 (H) EXECP INT 05 _ Boundary
86 (H) EXECP INT 06 _ Invalid OP Code
87 (H) EXECPINT0O7 —
88 (H) EXECP INT 08 Double Exception
89 (H) EXECP INT 09 _ Processor Segment Error
8A (H) EXECPINT10 —
8B (H) EXECP INT 11 Segment Not Present
8C (H) EXECP INT 12 Stack Segment Not Present
8D (H) EXECP INT 13 _ General Protection Error
8E (H) EXECPINT 14 —
8F (H) EXECPINT15 —
90 (H) EXECP INT 16 _ Processor Extension Error
Power on diagnostic program is finished at the time of boot up ( end of test 21 ).
Note that during execution of ‘‘POD”’ calls are made to auto configure and to miscellaneous interrupt routines.
All error messages listed in appendix L of operations guide are listed in the overview above with the exception of the following
which are generated from the miscellaneous interrupt routines.
10 ‘‘Parity error on main circuit board’’
11 ‘‘Parity error on expansion bus’’
12 ‘‘Non-recoverable error - Processor halted’’
13. ‘‘Press F1 key to continue’’
Messages 10, 11 are generated after a parity error has been detected and a memory check has determined that it was on the
main board, or the expansion bus. If the check finds the error the CPU is halted and message 12 is displayed. If no error
is found after the check, message 13 is displayed and processing will continue.
PC40-III SERVICE MANUAL
SECTION 4
PARTS SECTION
3: 20 DR
NYO N NY | | =| =| |S SO ee
Ne Se OS Oy ew Ne eS
PC40-III MAJOR PARTS LIST
Refer to Service Reference Diagram
Top Cover
Spacer Plate
Mounting Bracket
PBC Guide
Main Chassis Base
Foot
Bezel
Keyswitch Assy.
Plate Logo
Name Plate
FD Hole Cover
LED Power On
LED Hard Drive
Power Supply Assy
Floppy Disk Drive
Hard Disk Drive
Extension Card Panel
Keyboard Assy.
1352 Mouse Option
312226-01
313011-01 Sub:-02
313066-02 Sub:-01
251118-01
312225-01
380128-01
312244-01
313061-01
380133-05
316468-01
312679-01
380016-01
380020-02
390269-02 (US)
380825-02
313065-01
380120-01
312709-01 (US/Canada)
-1352
Floppy Drive Cable 380012-08
Hard Drive Cable 312695-01
PCB Assy. 313055-01
Ground Cable (HD) 380811-01 (Not shown)
Power Cord 903508-15 (US) (Not shown)
PC40-III Service Manual 314134-01
1403 Monitor Service Manual 314882-01
PC40-ITI MAJOR PARTS LIST
Software Sub. Assy. (US) 315835-01
Includes
DOS 3.30A Manual 319293-01
319292-01
319983-01
317768-01
Basis 3.22 Manual
Operations Guide
Disk Assembly
PC40-III SERVICE MANUAL
©
TOP COVER
312226-01
POWER SUPPLY
390269-02
(US)
(45)[ For isk
DRIVE
380825-02
RWI 9a
S¥
SPACER PLATE
313011-01
MOUNTING
BRACKET
313066-02
©. ©
HARD DISK
DRIVE @) HD CABLE
313065-01 312695-01
KEYBOARD ASSY.
312702-02
MAIN CHASSIS
BASE
312225-01
Nee a JE
=a
=rS vee iy —| uae ) 5 @) PCB ASSY.
yo | 1-| -9 313055-01
=e Cot eS?
C0 = c =
= 303 5 =
Service Reference Diagram
41
PC40-II] SERVICE MANUAL
COMPONENT PARTS LIST
-PCB ASSEMBLY #313055-01
Commodore part numbers are provided for reference only and do not indicate the availability of parts from Commodore.
Industry standard parts (Resistors, Capacitors, Connectors) should be secured locally. Approved cross-references for TTL chips,
Transistors, etc. are available in manual form through the Service Department, order #314000-01.
IC COMPONENTS
80286 12 MHZ PROCESSOR
CRYSTAL, OSCILLATORS (Continued)
900560-01 | CRYSTAL, 32.768 KHZ
900556-13 | CRYSTAL, 1.8 MHZ
900558-91_| CRYSTAL, 14.318 MHZ
901521-30
901521-20
901521-63
901521-13
901521-46
318066-01
3901 10-01
390203-01
390313-01
390279-01
318827-01
390322-01
390324-01
901527-03
390364-01
901882-01
901883-01
PVGA-1A PARADISE VIDEO
PPC1, PRINTER INTERFACE
WD37C65, FLOPPY CONTROLLER
IMS171, INMOS COLOR LOOKUP
TABLE
8250, SERIAL INTERFACE
M14818A RTC/CMOS RAM
8242 KEYBRD CONTROL
MOS 5720, MOUSE-I/O CONTROL
PAL20L8 VGA DECODER #0
PAL20L8 VGA DECODER #1
PAL20L10 I/O DECODER
PAL20L10 HDC DECODER
PALI6L8 DRAM DECODER
DRAM, 64 X 4 (256K BIT) @100NS
DRAM, 256 X 4 (1 MEG BIT DRAM)
@ 100NS
EPROMI, VGA BIOS - LOW (27128-15)
EPROM2, VGA BIOS - HIGH (27128-15)
EPROM3, PC40 III BIOS - LOW
(21728-12)
EPROM4, PC40-III BIOS - HIGH
(27128-12) .
U102,U103,U107,U110,
U901,U902,U106
U104,U105,U502,U603
U721,U807
U413,U715,
U718,U719,U1201
U717
U1204
U305
U803,U1202
U403
U404
U704
U701
U702,U703
U705,U1205
U903,U904
U412,U411,U716
U402
U1002
U720
U405-U409,U410
OSCILLATOR, 48.00 MHZ
OSCILLATOR, 36.00 MHZ
OSCILLATOR, 25.175 MHZ
OSCILLATOR, 28.322 MHZ
OSCILLATOR, 9.6 MHZ
RESISTOR NETWORKS
150 OHM 6P, SEL SIP
68 OHM, 8PIN, 4 ELEMENT
33 OHM, 8 PIN, 4 ELEMENT, SIL
1K OHM, 8 PIN, 4 ELEMENT, SIL
4.7K 6 PIN, 5 ELEMENT, SIP
4.7K, 8 PIN, 7 ELEMENT, SIP
10K, 8 PIN, 7 ELEMENT, SIP
4.7K, 10 PIN, 9 ELEMENT, SIP
10K, 10 PIN, 9 ELEMENT, SIP
330 OHM, 6 PIN, 5 ELEMENT, SIP
RESISTORS 5% @ 1/4 WATT
901550-39 | CARBON FILM, 3.9K OHM
901550-64 | CARBON FILM, 10 OHM
901550-63 | CARBON FILM, 22 OHM
901550-105} CARBON FILM, 33 OHM
901550-94 | CARBON FILM, 68 OHM
901550-45 | CARBON FILM, 75 OHM
901550-124] CARBON FILM, 160 OHM
901550-52 | CARBON FILM, 220 OHM
901751-70 | CARBON FILM, 210K OHM, 1%
901550-12 | CARBON FILM, 22K OHM
901550-58 | CARBON FILM, 470 OHM
901550-01 | CARBON FILM, 1K OHM
901550-49
901550-18
901550-19
CARBON FILM, 100 OHM
CARBON FILM, 2.2K OHM
CARBON FILM, 4.7K OHM
901550-03
901550-20
CARBON FILM, 5.1K OHM
CARBON FILM, 10K OHM
901550-84 | CARBON FILM, 1M OHM
901600-28 | CARBON FILM, 2.2 OHM
901550-17 | CARBON FILM, 1.2 OHM
901550-110] CARBON FILM, 51 OHM
901550-92 | CARBON FILM, 20K OHM
901550-70 | CARBON FILM, 300 OHM
RP1001
RP701,702
RP101-106,601,602,
RP703,RP704
604,
R503-R506,R210-R212
R102,812
R402,603,R1206,609,
701,813,410
R114,1001,101,409,401,
R209
R801,R411
R1201
R804,R902,R507,R207
R210
R1202
R206,207
R204,407,702, 1204,412,
502,508, 1003, 1004
RI15,R117
R604,R608
R105,R404,R606,901,
R803,R1002,R904,806,
R406,R509,R903,811
R805
R202,R501,R605,905,
302,R113,R116
R203,R601,R602,R807,
RESISTORS 1% @ 1/4 WATT :
CARBON FILM, 150 OHM
CARBON FILM, 365 OHM
CARBON FILM, 2K OHM
CARBON FILM, 4.64K OHM
CARBON FILM, 340 OHM
R107-R109,1005,1006
R110
R111,R112
R104
R106
RADIAL CERAMIC CAPACITORS 5% @ 50 VOLT
RADIAL LEAD, 22pF
RADIAL LEAD, 27pF
RADIAL LEAD, 47pF
RADIAL CERAMIC .0047uF
RADIAL LEAD, 100pF
RADIAL LEAD, 10pF
RADIAL LEAD, 1000pF
MONO., RAKIAL LEAD, .luF
C601,C402
C202
C201
C603,C621-626,C514-
C532
C401
C206,C627,C207
C203-CB102,CB115,
CBI1011,CB1014,
CB2031-2034,CB205,
CB206,CB3011,CB3012,
4-2
PC40-IIT SERVICE MANUAL
COMPONENT PARTS LIST
PCB ASSEMBLY #313055-01 (Continuea)
900022-03 | MONO., RAKIAL LEAD, .luF CB302,CB3031-3039, BATTERY, NICAD 3.6V BT201,BT202
CB3041-3048,CB401-412 FUSE, PICO, 4A FU601
CBS01,CB502,CB6011, DELAY LINE 10 TAP @ 20 NS DL701
CB6012,CB602-605, TRANSISTOR 2N3904 Q601,Q801,Q1201
CB6051,CB6052,CB706, PIEZO BEEPER QMB12 PZ801
CB716,CB722,CB8011, PUSH BUTTON N.O. SWITCH PBSO1
CB8012,CB8021, PIANO DIP SWITCH, I PIN, 4 POS. swi0l
CB8022,CB902,1001, SOCKET, 28 PIN, DIP U108,U109,U1101,
CB901,CB905,116, U1102
SOCKET, 40 PIN, DIP
CB1002,1121,CB1101, U302
CB1102 SOCKET, 68 PIN, PLCC U301,U601
C301,C101 SOCKET, 84 PIN, PLCC U303,304,801,802
CB118-125,707-714,403- SOCKET, 100 PIN, PLCC
407,409-411,CB415, D-SUB, 9 PIN, RT. ANGLE MALE
CB416,CB701-705,715, D-SUB, 15 PIN, RT. ANGLE FEMALE
717-721 ,803,CB903, D-SUB, 25 PIN, RT. ANGLE MALE
904,1201-1205,413, D-SUB, 25 PIN, TR. ANGLE FEMALE
EXPANSION CONNECTOR, 62 PIN
EXPANSION CONNECTOR, 36 PIN
900019-07 | .047 UF
900022-05 | MONO., RADIAL LEAD, .33uF
MONO., RADIAL LEAD, .22uF
DIN, TK PIN, ROUND, FEMALE
JACK, RCA RT. ANGLE, FEMALE
HEADER, 3 PIN, SIL
CAP ELECT., TAN, 10uF
ELECT., ALUM., RADIAL, 47uF
C501-C506,C508-C510,
C512
C1202
HEADER, 2 PIN, SIL
HEADER, 34 PIN, DIL
HEADER, 40 PIN, DIL
POWER CONNECTOR, 6 PIN.
SHORTING BLOCKS, 2 POS.
JUMPER
EMI FILTER 100PF
EMI FILTER 22000PF
EMI FILTER 2200PF
EMI FILTER MURRATA
DSS306-SSY5101M
EMI FILTER 150 PF
FERRITE BEADS (AXIAL)
EM1624-1631,1201
EMI1203
EMI201,202
EMI101-105
EMI607-623
FB403,404,101,1001,
FBI103
FB104,601-608,405, 102
FB201-204
CR201,CR202,CRS501,
CRS502,CR601-CR603
FERRITE BEADS (AXIAL) 390304-02 | IC, WD37C6S5A
FERRITE BEADS THREE TURN
DIODE 1N4148
4-3
PC40-III SERVICE MANUAL
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PC40-III SERVICE MANUAL
MOUSE PORT
CN6O1 (5mm)
VIDEO PORT
CNI101 (3/16")
vy
5
3
Signal
Vertical
Horizontal
Vertical Q
Horizontal Q
Button (3)
Button (1)
+ 5V
Ground
Button (2)
OONOOADN —
SERIAL PORT
CN603 (5mm)
139 12g lle 10e 9g 87 aS 5S aia 3a 2g!
o GPIII~IPI ISA
25. 24. 23. 22.21, 20,19 17. 16. 15.14
GII~I~D?
Computer Peripheral
Side Side
——_ 1 CHASSIS GROUND
——— 2 TxD ——————
—— 3 RxD
———_ _ 4——__ RTS
—— §5——_-CTS
—— 6 ———— DSR-——_——_—_——_
————_ 7 SIG GND——————_-
——-_ 8 DCD——____—__—_
—_—_——— (8 oe HV
10 ——————- - 12V
20 —————_ DTR-_———>
—_——— 22 ——_——_ Rl
I
|
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1 2 3 4 §
Computer
Side
1
2
3
4
5
6
7
8
9
12
—— 15
—_
“NO
14°15 16 17 18 19 20 21 22 23 24 25
e.°@ e e ®@
1§ 14 13 12 11
Function
Red Video
Green Video
Blue Video
Monitor ID Bit 2 (not used)
ground
Red Return (ground)
Green Return (ground)
Blue Return (ground)
Key (no pin)
Sync Return (ground)
Monitor ID Bit 0 (not used)
Monitor ID Bit 1 (not used)
Horizontal Sync
Vertical Sync
not used
PARALLEL PORT
CN602 (Smm)
@©ee @ @ ®@
8 9 10 11 12 13
ACK
BUSY
PE
SsLCT —————_——-
AUTO FDXT ————>
ERROR
INIT ———_—————>
SLCT IN-—————>
18-25 ————- GND—____—_-
PC40-III SERVICE MANUAL
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4-6
PC40-III SERVICE MANUAL
SECTION 5
e IC PINOUTS
e SCHEMATICS
INFORMATION IN THIS SECTION IS FOR REFERENCE ONLY.
COMMODORE WILL NOT SUPPLY COMPONENT PARTS FOR
OEM ASSEMBLIES.
PC40-III SERVICE MANUAL
IC PIN OUTS & SIGNAL DESCRIPTIONS
1) 80286 CPU 390300-01
2) FE3000A CPU CNTRL 390316-01
3) FE3010B PERP CNTRL 390317-02
4) FE3020 ADDR BUFFER 390319-01
5) FE3030 DATA BUFFER 390318-01
6) PVGA-1A PARADISE VIDEO 390302-01
7) PPCI1 PRINTER INTERFACE 318091-01
8) WD37C65 FDC 390304-03
9) 8250 SERIAL INTERFACE 380205-01
10) 5720 MOUSE CONTROL 318087-01
5-1
PC40-IIT SERVICE MANUAL
1) 80286 CPU 390300-01
Component Pad Views—As viewed from underside of P.C. Board Views—As viewed from the component
component when mounted on the board. side of the P.C. board.
a . a . - -) a
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DIZISISIVISISIITI SIDS Salas
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Sans nie ne. GS a
ev. 30 NC we. Le] is
Oo cc NTR NTR ie
© aeset 29 RCSET
a i se NC. NAC. [54 ay
§ 27 nul nul
v0 26 Yss Yss [8]
$ 5 PcReO pcaco (61)
4 2 Yee Yoo {42
a] 23 ROADY atidr (05
3 2 HOLO HOLO [64
3 2 HLOA wpa [55]
-% 20 COO/INTA COD/inTa [66]
19 “/d ui (67
Ais] 18 cock LOCK [68] ayy
18
SYMBOL
CLK
D15-D0
A23-A0
BRE
om nm
nN
SieP FFL
id
le
eierierdon
PIN NO.1 MARK gg gio
TYPE NAME AND FUNCTION
I
Vo
oO
Oo
SYSTEM CLOCK provides the fundamental timing for 80286 systems. It is divided by two inside the 80286 to generate the processor clock. The internal
divide-by-two circuitry can be synchronized to an external clock generator by a LOW to HIGH transition on the RESET input.
DATA BUS inputs data during memory, I/O, and interrupt acknowledge read cycles; outputs data during memory and I/O write cycles. The data bus is
active HIGH and floats to 3-state OFF during bus hold acknowledge.
ADDRESS BUS outputs physical memory and I/O port addresses. AO is LOW when data is to be transferred on pins D7-0. A23-A16 are LOW during
I/O transfers. The address bus is active HIGH and floats to 3-state OFF during bus hold acknowledge.
BUS HIGH ENABLE indicates transfer or data on the upper byte of the data bus. D15-8. Eight-bit oriented devices assigned to the upper byte of the data
bus would normally use BHE to condition chip select functions. BHE is active LOW and floats to 3-state OFF during bus hold acknowledge.
BHE and AO Encodings
BHE Value AO Value Function
0 0 Word transfer
0 1 Byte transfer on upper half of data bus (D15-8)
1 0 Byte transfer on lower half of data bus (D7-0)
1 1 Will never occur
BUS CYCLE STATUS indicates initiation of a bus cycle and, along with M/IO and COD/INTA, defines the type of bus cycle. The bus is in a Ts state
whenever one or both are LOW, Si and 50 are active LOW and float to 3-state OFF during bus hold acknowledge.
80286 Bus Cycle Status Definition
COD/INTA M10 Si Bus Cycle Initiated
Interrupt acknowledge
Will not occur
Will not occur
None; not a status cycle
IF Al = 1 then halt; else shutdown
Memory data read
Memory data write
None; not a status cycle
Will not occur
V/O read
V/O write
None; not a status cycle
Will not occur
Memory instruction read
Will not occur
None; not a status cycle
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PC40-IIT SERVICE MANUAL
SYMBOL TYPE NAME AND FUNCTION
M/0
COD/INTA
LOCK
READY
HOLD
HLDA
INTR
RESET
Vss
Vee
CAP
oO
Oo
oO
Om
| ll
MEMORY I/O SELECT distinguishes memory access from I/O access, if HIGH during Ts, 2 memory cycle or a halt/shutdown cycle is in progress. It
LOW, an I/O cycle or an interrupt acknowledge cycle is in progress. M/TO floats to 3-state OFF during bus hold acknowledge.
CODE/INTERRUPT ACKNOWLEDGE distinguishes instruction fetch cycles from memory data read cycles. Also distinguishes interrupt acknowledge cycles
from.1/O cycles. COD/INTA floats to 3-state OFF during bus hold acknowledge. Its timing is the same as M/TO.
BUS LOCK indicates that other system bus masters are not to gain control of the system bus for the current and the following bus cycle. The LOCK signal
may be activated explicitly by the “LOCK” instruction prefix or automatically by 80286 hardware during memory XCHG instructions, interrupt acknowledge,
or descriptor table access. LOCK is active LOW and floats to 3-state OFF during bus hold acknowledge.
BUS READY terminates a bus cycle. Bus cycles are extended without limit until terminated by READY LOW. READY is an active LOW synchronous input re-
quiring setup and hold times relative to the system clock be met for correct operation. READY is ignored during bus hold acknowledge.
BUS HOLD REQUEST AND HOLD ACKNOWLEDGE control ownership of the 80286 local bus. The HOLD input allows another local bus master to
request contro! of the local bus. When control is granted, 80286 will float its bus drivers to 3-state OFF and then activate HLDA, thus entering the bus
hold acknowledge condition. The local bus will remain granted to the requesting master until HOLD becomes inactive which results in the 80286 deactivating
HLDA and regaining control of the local bus. This terminates the bus hold acknowledge condition. HOLD may be asynchronous to the system clock. These
signals are active HIGH.
INTERRUPT REQUEST requests the 80286 to suspend its current program execution and service a pending external request. Interrupt requests are masked
whenever the interrupt enable bit in the flag word is cleared. When the 80286 responds to an interrupt request, it performs two interrupt acknowledge bus
cycles to read an 8-bit interrupt vector that identifies the source of the interrupt. To assure program interruption, INTR must remain active until the first
interrupt acknowledge cycle is completed. INTR is sampled at the beginning of each processor cycle and must be active HIGH at least two processor cycles
before the current instruction ends in order to interrupt before the next instruction. INTR is level sensitive, active HIGH, and may be asynchronous to
the system clock.
NON-MASKABLE INTERRUPT REQUEST interrupts the 80286 with an internally supplied vector value of 2. No interrupt acknowledge cycles are performed.
The interrupt enable bit in the 80286 flag word does not affect this input. The NMI input is active HIGH, may be asynchronous to the system clock, and
is edge triggered after internal synchronization. For proper recognition, the input must have been previously LOW for at least four system clock cycles and
remain HIGH for at least four system clock cycles.
PROCESSOR EXTENSION OPERAND REQUEST AND ACKNOWLEDGE extend the memory management and protection capabilities of the 80286
to processor extensions. The PEREQ input requests the 80286 to perform a data operand transfer for a processor extension. The PEACK output signals the pro-
cessor extension when the requested operand is being transferred. PEREQ is active HIGH and floats to 3-state OFF during bus hold acknowledge. may
be asynchronous to the system clock. PEACK is active LOW.
PROCESSOR EXTENSION BUSY AND ERROR indicate the operating condition of a processor extension to the 80286. An active BUSY input stops 80286 pro-
gram execution on WAIT and some ESC instructions until BUSY becomes inactive (HIGH). The 80286 may be interrupted while waiting for BUSY to become in-
come inactive. An active ERROR input causes the 80286 to perform a processor extension interrupt when executing WAIT or some ESC instructions. These inputs
are active LOW and may be asynchronous to the system clock. These inputs have internal pull-up resistors.
SYSTEM RESET clears the internal logic of the 80286 and is active HIGH. The 80286 may be reinitialized at any time with a LOW to HIGH transition
on RESET which remains active for more than 16 system clock cycles. During RESET active, the output pins of the 80286 enter the state shown below:
80286 Pin State During Reset
Pin Value Pin Names
1 (HIGH) 350, 51, PEACK, A23-A0, BHE, LOCK
0 (LOW) M/10, COD/INTA, HLDA (Note 1)
3-state OFF D15-D0
Operation of the 80286 begins after a HIGH to LOW transition on RESET. The HIGH to LOW transition of RESET must be synchronous to the system
clock. Approximately 38 CLK cycles from the trailing edge of RESET are requried by the 80286 for internal initialization before the first bus cycle, to fetch
code from the power-on execution address, occurs.
A LOW to HIGH transition of RESET synchronous to the system clock will end a processor cycle at the second HIGH to LOW transition of the system
clock. The LOW to HIGH transition of RESET may be asynchronous to the system clock; however, in this case it cannot be predetermined which phase
of the processor clock will occur during the next system clock period. Synchronous LOW to HIGH transitions of RESET are required only for systems
where the processor clock must be phase synchronous to another clock.
SYSTEM GROUND: 0 Volts.
SYSTEM POWER: +5 Volt Power Supply.
SUBSTRATE FILTER CAPACITOR: a 0.047 pF + 20% 12V capacitor must be connected between this pin and ground. This capacitor filters the output
of the internal substrate bias generator. A maximum DC leakage current of 1 »A is allowed through the capacitor.
For correct operation of the 80286, the substrate bias generator must charge this capacitor to its operating voltage. The capacitor chargeup time is 5 milliseconds
(max.) after Vec and CLK reach their specified AC and DC parameters. RESET may be applied to prevent spurious activity by the CPU during this time.
After this time, the 80286 processor clock can be synchronized to another clock by pulsing RESET LOW synchronous to the system clock.
NOTE: HLDA is only Low if HOLD Is inactive (Low).
PC40-IT SERVICE MANUAL
2) FE3000A CPU CNTRL 390316-01
PIN TYPE SYMBOL FUNCTION
18 I ENPAL2 ENABLE EXTERNAL WAIT STATE
Active high — Disables external wait state
generator.
19 I F16 16 BIT MEMORY OPERATION
Active high — Indicates that the current memory
cycle
20 I HLDA HOLD ACKNOWLEDGE FROM THE 80286 ae
Active high — Indicates that the 80286 has rele
en Prien the bus in response to a CPUHRQ signal.
A0 HLDAI1 21 I HRQ1 HOLD REQUEST
Al NENDCY Active high — Bus request from a DMA controller.
EAIOCK 2 eye 22 I IOCRDY EXPANSION BUS READY
ENPAL2 68 S1 Active high — Signal from the expansion bus to in-
F16 67 ‘SO dicate that the current cycle may complete.
han < ae 23 I MDPINO PARITY BIT FROM RAM BANK 0
4 Parity bit from on board RAM bits 0-7.
repent FE3000A FARADAY 4% NENEAGE 24 1 MDPINI_ PARITY BIT FROM RAM BANK 1
baretons 2 bral re Parity bit from on board RAM bits 8-15,
I MNIO MEMORY I/O SELECT
oN - Masle Active high — Signal from the 80286 indicating the
NBUSY 58 NIOCHK next cycle is a memory cycle.
NCS287 57 NERROR 26 I NAEN1 ENABLE DMA CHANNELS 0-3 TO USE DATA
NIRQI3 56 UNUSED BUS
NDMAMR 55 IOCHCK
RS 54 LSAO Active low
27 I NAEN2 ENABLE DMA CHANNELS 5-7 TO USE DATA
BUS
Active low
28 I NBUSY BUSY STATUS ASSERTED BY 80287
Active low
29 I NCS287 =: 80287 1/0 CHIP DECODE
Active low
30 oO NIRQIZ3) INTERRUPT REQUEST 13
Active low — Co-processor error
31 I NDMAMR DMA MEMORY READ COMMAND
PIN TYPE SYMBOL FUNCTION Active low — Memory read command from a DMA
1 VSS GROUND controller
2 Vo NXBHE BUS HIGH ENABLE 32 ¢) RST287 RESET TO 80287
Active low — Indicates the current bus cycle will Active high
transfer a byte on the upper byte. 33 SYSCLK SYSTEM CLOCK
3 Vo NYIOR I/O READ COMMAND System clock in phase with and half the frequency
Active low — Indicates a read of an I/O device. of the PROCLK. (ie: 6, 8, or 1OMHz)
4 Vo NYIOW 1/0 WRITE COMMAND 34 Oo RESCPU RESET TO 80286
Active low — Indicates a write of an I/O device. Active high — Reset to CPU from a command to
5 1/0 NYMEMR MEMORY READ COMMAND exit protected mode or an external reset.
Active low — Indicates a read of memory. 35 (¢) REFDET REFRESH DETECT
6 VO NYMEMW MEMORY WRITE COMMAND Signal that toggles each time there is a refresh cycle
Active low — Indicates a write of memory. to the RAM.
7 oO AIOW EXTENDED I/O WRITE COMMAND 3% oO Ql START OF BUS CYCLE.
Active high — Used for external wait state Active high — Indicates start of a bus cycle to the
generator. external wait state generator.
8 oO AS REAL TIME CLOCK ALE 37 oO PCK PARITY CHECK
Active high — Used to latch the address in the Active high — Indicates a RAM parity error has
clock calender chip (Motorola 146818) been detected.
9 BALE BUS ADDRESS LATCH ENABLE 38 oO PCLK CLOCK TO 8042
Active high — Or of ALE and HLDA. 39 Oo PROCLK PROCESSOR CLOCK TO 80286
10 Oo CPUHRQ BUS HOLD REQUEST TO 80286 Clock twice the processor speed. (ie: 12, 16, or 20
Active high — Bus request to 80286 CPU caused by MHz)
refresh or a DMA cycle. 40 oO NPCLK INVERTED CLOCK TO 8042
+) i ¢) CILOFF DATA LATCH CONTROL 41 VO NRFSH REFRESH CYCLE
Active high — Latch data bits 0-7 of first bus cycle Active low — Indicates the current bus cycle Is a
of a word transfer on a byte device. RAM refresh cycle.
12 oO DMARDY READY TO DMA 42 vss GROUND
Active high — Indicates that the DMA may com- 43 VDD +5 VOLTS SUPPLY
plete its cycle. “4 \YVvO XA0 ADDRESS A0
13 oO DMACLK CLOCK TO DMA DEVICES Active high — System address bit 0
Clock in sync with and half the frequency of the 4s oO NDENO GATE DATA 0-7
SYSCLK (ie: 3, 4, or 5 MHz) Active low
14 I AO 80286 ADDRESS AO 46 NDEN1 GATE DATA 8-15
Active high — Address bit 0 from the 80286. Active low
15 I Al 80286 ADDRESS Al 47 DIR245 BYTE SWAP DIRECTION
Active high — Address bit 1 from the 80286. Signal to control byte swap direction on a 16 bit
16 I EAIOCK ENABLE I/O CHECK transfer on a 8 bit device.
Active high — Enable error signa! from the expan- 4 8600 NERFSH ENABLE REFRESH ADDRESS
sion bus. Active low — Signal to enable the refresh address
17 I EMBRMCK ENABLE RAM PARITY CHECK CONTROL to the address bus during a RAM refresh cycle.
Active high — Enable parity check from on board 400 NNPCS 80287 CHIP SELECT
RAM.
Active low
5-4
PIN
50
51
61
62
67
69
70
n
4
@8 8283a
&
TYPE SYMBOL
o
oO
° 000
oO 0O=O—
NEDMMR
NINTA
NNMI
NBZ286
LSAO
IOCHCK
UNUSED
NERROR
NIOCHK
NIOS16
NNMICS
NRAMSL
NRESIN
NENFAST
NZROWS
OUTI
RC
S!
XA3
XD7
NENDCY
HLDA1
F119M
F14M
NRESET
NREADY
X18284
X28284
X1284
X2284
DTNR
FUNCTION
ENABLE DMA MEMORY READ
Active low — Gates a memory read to the bus dur-
ing a DMA cycle.
INTERRUPT ACKNOWLEDGE
Active low — Interrupt acknowledge to the inter-
rupt controllers.
NMI OUTPUT TO 80286
Active low — Non-maskable interrupt to 80286.
80287 BUSY TO 80286
Active low
LATCHED SYSTEM ADDRESS A0
Active high — System address bit 0 during a CPU
bus cycle.
1/O DEVICE ERROR
Active high — Indicates an error from the expan-
sion bus.
UNUSED
Must be left open
80287 ERROR
Active low — Error from the 80287.
1/O CHECK
Active low — Error signal from the expansion bus.
16 BIT 1/0 TRANSFER
Active low — Signal from the expansion bus to in-
dicate that the current bus cycle is a 16 bit 1/O
transfer.
NMI PORT DECODE
Active low — Decode of NMI enable port.
ON BOARD RAM DECODE
Active low
RESET IN
Active low — External reset in used to generate a
system reset.
ENABLE LOOK AHEAD DECODE
Active low — Causes early eneration of memory
read and write signals with zero wait states.
ZERO WAIT STATES
Active low — Indicates the current bus cycle should
have no wait states.
TERMINAL COUNT OF TIMER CHANNEL 1
Active high — Terminal count from timer channel
1
RESET TO CPU 80286
Active high — Input to generate RESET to CPU.
BUS CYCLE STATUS S0 FROM 80286
BUS CYCLE STATUS S1 FROM 80286
ADDRESS A3
Active high — System address bit 3
SYSTEM DATA BUS BIT 7
Active high
TERMINATE CURRENT CYCLE
Active low — Signal from external wait state
generator to end the current bus cycle.
HOLD ACKNOWLEDGE TO DMA
Active high — Hold acknowledge to one of DMA
controllers.
1.19 MHz CLOCK TO TIMER
14.318 MHz SIGNAL TO EXPANSION BUS
ENABLE BUS SWAP
Active low — Gates data during the swap of a byte
on a 16 bit transfer on a 8 bit device.
RESET TO SYSTEM LOGIC
Active low
SYNCHRONIZED READY TO CPU
Active low — Ready to CPU indicating that the
current bus cycle may terminate.
CRYSTAL TO 8284 CLOCK GENERATOR
CRYSTAL TO 8284 CLOCK GENERATOR
CRYSTAL TO 82284 CLOCK GENERATOR
CRYSTAL TO 82284 CLOCK GENERATOR
DATA DIRECTION CONTROL
Active low — A low indicates a bus read cycle.
ADDRESS LATCH ENABLE
Active high — Signal to latch the address from the
80286.
+5 VOLTS SUPPLY
PC40-IIT SERVICE MANUAL
5-5
DMACLK
PIN
SCBIANEAWN
12
13
14
21
R RR BR
TYPE
Vo
Vo
Vo
vo
vo
Vo
Vo
vo
I
Oo Om mm
=~ =m
3) FE3010A (@)
SawronenanSSSasFk
FE3010A FARADAY
SYMBOL
VSS
DATA(0)
DATA(1)
DATA(2)
DATA(3)
DATA(4)
DATA(65)
DATA(6)
DATA(7)
HLDA
DMARDY
DMACLK
NMASTER
KBINT
IRQ3
IRQ4
IRQS
IRQ6
IRQ7
INTR
OUT 1
VSS
TCLK
SPKR
NIRQS
IRQS
LALVSSSSSSISS
GROUND
DATA BIT 0
DATA BIT 1
DATA BIT 2
DATA BIT 3
DATA BIT 4
DATA BIT 5
DATA BIT 6
DATA BIT 7
HOLD ACKNOWLEDGE
Active high — Acknowledge from the CPU (80286)
for a request for the bus from the DMA controller.
DMA READY
Active high — Signal to indicates that DMA may
complete its current cycle.
DMA CLOCK
System Clock DMACLK
6 MHz 3 or 6 MHz
8 MHz 4 or 8 MHz
10 MHz 5 MHz
BUS MASTER
Active low — Signal to indicate that a master on
the expansion bus has control of the bus.
KEYBOARD INTERRUPT
Active high
INTERRUPT REQUEST 3
Active high
INTERRUPT REQUEST 4
Active high
INTERRUPT REQUEST 5
Active high
INTERRUPT REQUEST 6
Active high
INTERRUPT REQUEST 7
INTERRUPT REQUEST TO CPU (80286)
Active high
TIMER CHANNEL 1 OUTPUT
GROUND
TIMER CLOCK
(1.19 MHz clock for timer)
SPEAKER
INTERRUPT REQUEST 8
Active low
INTERRUPT RQUEST 9
Active high
27
39
af 8 8B
70
1
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PC40-IIT SERVICE MANUAL
IRQ10
IRQI1
IRQ12
AL(0)
AL(1)
AL(2)
AL(3)
AL(4)
AL(5)
AL(6)
AL(7)
AL(8)
AL(9)
AH(0)
AH(1)
VSS
VDD
AH(2)
AH(3)
AH(4)
AH(S5)
AH(6)
AH(?)
AH(8)
AH(9)
AH(10)
AH(11)
AH(12)
AH(13)
NRFSH
ALE
NRTCCS
NINTA
IRQIS
IRQ14
NIRQI3
NCLEAR
VSS
DACK2
DACK1
DACKO
NDACKEN
HRQ
TO
AEN
DRQ7
PERP. CNTRL 390317-02 (-02)
INTERRUPT REQUEST 10
Active high
INTERRUPT REQUEST 11
Active high
INTERRUPT REQUEST 12
Active high
ADDRESS BIT 0
ADDRESS BIT 1
ADDRESS BIT 2
ADDRESS BIT 3
ADDRESS BIT 4
ADDRESS BIT 5
ADDRESS BIT 6
ADDRESS BIT 7
ADDRESS BIT 8
ADDRESS BIT 9
ADDRESS BIT 10
ADDRESS BIT 11
GROUND
+5 VOLTS SUPPLY
ADDRESS BIT 12
ADDRESS BIT 13
ADDRESS BIT 14
ADDRESS BIT 15
ADDRESS BIT 16
ADDRESS BIT 17
ADDRESS BIT 18
ADDRESS BIT 19
ADDRESS BIT 20
ADDRESS BIT 21
ADDRESS BIT 22
ADDRESS BIT 23
REFRESH ADDRESS
Active low — Signal to enable the refresh to the ad-
dress bus during a RAM refresh cycle.
ADDRESS LATCH ENABLE
Active high
REAL TIME CLOCK CHIP SELECT
Active low
INTERRUPT ACKNOWLEDGE FROM CPU
(80286)
Active low — Interrupt acknowledge to the inter-
rupt controllers.
INTERRUPT REQUEST 15
Active high
INTERRUPT REQUEST 14
Active high
INTERRUPT REQUEST 13
Active low — Error interrupt from (80287).
SYSTEM CLEAR
Active low
GROUND
DMA ACKNOWLEDGE BIT 2
DMA Channel
-DACK2_DACK1_DACKO__Acknowledge__
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 Illegal
1 0 1
1 1 0 6
1 1 1 1
DMA ACKNOWLEDGE BIT 1
DMA ACKNOWLEDGE BIT 0
DMA ACKNOWLEDGE ENABLE
Active low — Signal to enable DACKO, DACK1,
and DACK2 decodes.
DMA REQUEST TO CUP (80286)
Active high
DMA END OF OPERATION
Active high — Signal to indicate the DMA con-
troller has finished its cycle.
DMA AEN
Active high — Signal to indicate that the current
bus is a DMA cycle.
CHANNEL 7 DMA REQUEST
Active high
PIN
73
14
1S
16
71
78
19
TYPE SYMBOL
I
oO
Vo
Vo
Oo
oO
DRQ6
DRQS
DRQ3
DRQ2
DRQI
DRQO
SYSALE
NIOR
NIOW
NMEMR
NMEMW
VDD
FUNCTION
CHANNEL 6 DMA REQUEST
Active high
CHANNEL 5 DMA REQUEST
Active high
CHANNEL 3 REQUEST
Active high
CHANNEL 2 DMA REQUEST
Active high
CHANNEL 1 DMA REQUEST
Active high
CHANNEL 0 DMA REQUEST
Active high
SYSTEM ALE
Active high — Signal to latch the address in the ad-
dress latch.
I/O READ COMMAND
Active low
I/O WRITE COMMAND
Active low
MEMORY READ COMMAND
Active low
MEMORY WRITE COMMAND
Active low
+5 VOLTS SUPPPLY
PC40-III SERVICE MAN UAL
PIN
65
62
82
16
SESSSRSRRROK
TYPE SYMBOL
vo
vo
vo
vo
vo
NMASTER
HLDA
ADSTB
NRAMCS
NYMEMW
NYMEMR
NGIMEMR
NMEMW
NMEMR
NSMEMW
NEBHE
Sawmronennnsasaerrrre
PC40-IlI SERVICE MANUAL
4) FE3020 ADDR BUFFER 390319-01
NPROMSEL
NABHE
MEM245DIR
NSMEMW
NSMEMR
NMEMW
GDD9
14 vccs
73 GDD8
72 Als
~ Tl Alé
70 Al3
69 Al2
68 LA20
67 NYMEMW
66 NRAMCS
65 NMASTER
FE3020 FARADAY = @ F— sctwenr
63 NBHE
62 LASO
61 HLDA
60 ADSTB
59 AB
58 A22
57 NMEMR
56 NEBHE
55 GDD7
54 vcc7
FUNCTION
MASTER
Active low — Signal from the AT bus which allows
the bus master (o control the bus.
HOLD ACKNOWLEDGE
Active high — Signal from the 80286 to indicate
that the bus has been released in response to a CPU
HRQ signal.
ADDRESS STROBE
Active high — Signal from the FE3010 that latches
the address.
RAM CHIP SELECT
Active low — On board RAM chip select.
MEMORY WRITE COMMAND
Active low — Signal to indicate a write of memory
during a CPU, DMA, or Master cycle.
MEMORY READ COMMAND
Active low — Signal to indicate 2 read of memory
during a CPU or Master cycle.
GATE MEMORY READ
Active low — Signal to indicate a read memory dur-
ing a DMA cycle.
AT BUS MEMORY WRITE COMMAND
Active low — Signal to indicate a write of memory
during a CPU, DMA, or Master cycle.
AT BUS MEMORY WRITE COMMAND
Active low — Signal to indicate a read of memory
during a CPU, DMA, or Master cycle.
PC BUS MEMORY WRITE COMMAND
Active low — Signal to indicate a write of memory
below 1MB during a CPU, DMA, or Master cycle.
PC BUS MEMORY READ COMMAND
Active low — Signal to indicate a read of memory
below 1 MB during a CPU, DMA, or Master cycle.
AT BUS BYTE HIGH ENABLE
Active low — Indicates a transfer of data on the
upper byte of the data bus.
80386 BUS BYTE HIGH ENABLE
Active low — Indicates a transfer of data on the
upper byte of the data bus.
oo
-_
SSE KMSSSBRSVSSSAREGRSSSEw avg By
14
BadgKssoeranrak
vo NABHE
O NPROMSEL
oO MEM245
DIR
1 LASO
V/o ADR(0)
vo Al
Vo A2
vo A3
vo Ad
Vo AS
vo A6
Vo AT
Vo A8&
vo A9
vo Al0
1/O All
Vo Al2
1/O Al3
Vo Al4
Vo AlS
1/0 Al6
V/o Al?
1/0 Al8
1/0 Al9
Vo A20
1/o LA20
Vo A20GT
I A21
I A22
I A23
1/0 ADDO
1/0 ADD1
vo ADD2
Vo ADD3
V/o ADD4
Vo ADDS
Vo ADD6
1/o ADD7
1/o ADD8
1/o ADD9
1/O ADD10
Vo ADD11
Vo ADD12
Vo ADD13
Vo ADD14
vo ADD15
1/0 ADD16
Vo ADD17
Vo ADD18
vo ADD19
N/C
vccl
vcCc2
vcc3
vCcc4
vccs
VvCC6
vcc7
vccs
vcco
GDD1
GDD2
GDD3
GDD4
GDDI1
GDDS
GDD6
GDD7
GDD8
GDD9
GDD10
FE3000 BUS BYTE HIGH ENABLE
Active low — Indicates a transfer of data on the
upper byte of the data bus.
PROM SELECT
Active low — BIOS PROM select
MEMORY BUFFER DIRECTION
Direction control for the on board memory buffers.
FE3000 ADDRESS BIT 0
FE3000/FE3010 ADDRESS BIT 0
80286/FE3010 ADDRESS BIT 1
80286/FE3010 ADDRESS BIT 2
80286/FE3010 ADDRESS BIT 3
80286/FE3010 ADDRESS BIT 4
80286/FE3010 ADDRESS BIT 5
80286/FE3010 ADDRESS BIT 6
80286/FE3010 ADDRESS BIT 7
80286/FE3010 ADDRESS BIT 8
80286/FE3010 ADDRESS BIT 9
80286/FE3010 ADDRESS BIT 10
80286/FE3010 ADDRESS BIT 11
80286/FE3010 ADDRESS BIT 12
80286/FE3010 ADDRESS BIT 13
80286/FE3010 ADDRESS BIT 14
80286/FE3010 ADDRESS BIT 15
80286/FE3010 ADDRESS BIT 16
80286/FE3010 ADDRESS BIT 17
80286/FE3010 ADDRESS BIT 18
80286/FE3010 ADDRESS BIT 19
80286 ADDRESS BIT 20
FE3010 ADDRESS BIT 20
8042 GATE ADDRESS
Active high — ENable address bit 20
80286/FE3010 ADDRESS BIT 21
80286/FE3010 ADDRESS BIT 22
80286/FE3010 ADDRESS BIT 23
AT BUS ADDRESS BIT 0
AT BUS ADDRESS BIT 1
AT BUS ADDRESS BIT 2
AT BUS ADDRESS BIT 3
AT BUS ADDRESS BIT 4
AT BUS ADDRESS BIT 5
AT BUS ADDRESS BIT 6
AT BUS ADDRESS BIT 7
AT BUS ADDRESS BIT 8
AT BUS ADDRESS BIT 9
AT BUS ADDRESS BIT 10
AT BUS ADDRESS BIT 11
AT BUS ADDRESS BIT 12
AT BUS ADDRESS BIT 13
AT BUS ADDRESS BIT 14
AT BUS ADDRESS BIT 15
AT BUS ADDRESS BIT 16
AT BUS ADDRESS BIT 17
AT BUS ADDRESS BIT 18
AT BUS ADDRESS BIT 19
5V + 5%
5V + 5%
Vv
iV
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
PIN
65
n
69
4)
82 &8 4
TYPE
1
o 38
DATA3
DATA2
DATAI
DATAO
5) FE3030 DATA BUFFER 390318-01
Son
s PPP PEP re
= sos eee eeeceecee
AQSSEESS SSA 54 548
OS haeerzaoeaaaaade
SawrouenanSBSaSerree
SSSYRRROB
SYMBOL
10CK
PCK
NGTPIO
NWRPIO
ENIOCK
ENRAMCK
NRESET
NSELDATA
NINTA
HLDA
ACK
NF24S5DIR
DTR
ADDRESS(0)
ND646 EN
DGATECTL
FE3030 FARADAY
14
T3
nT
1
70
69
68
67
6
65
64
63
62
61
60
59
58
57
56
55
34
FUNCTION
1/0 DEVICE ERROR
Active high — This signal from the FE3000 in-
dicates an error from the PC/AT bus.
PARITY CHECK
Active high — This signal from the FE3000 in-
dicates a parity error from the on board RAM.
GATE PIO
Active low — This signal gates the IOCK and PCK
signals on to the data bus during a status read.
WRITE PIO
Active low — Write the error enable register.
ENABLE IO CHECK
Active high
ENABLE PARITY CHECK
Active high
RESET
Active low — System reset from the FE3000.
SELECT DATA
Active low — This signal gates the E data bus.
INTERRUPT ACKNOWLEDGE
Active low — This signal gates the interrupt vector
on the EDATA bus to the CPU.
HOLD ACKNOWLEDGE
Active high — Signal from the 80286 to indicate
that the bus has been released in response to a CPU
HRQ signal.
ACKNOWLEDGE
Active high — Signal to indicate that the current cy-
cle is a DMA cycle.
MASTER
Active low — Signal from the AT bus which allows
the bus master to control the bus.
BYTE SWAP DIRECTION
Controls the data bus direction for byte swap.
BYTE SWAP ENABLE
Active low — This signal enables the byte swap bus.
DATA DIRECTION
This signal determines the data direction on the bus.
AT BUS ADDRESS BIT 0
DATA BUS ENABLE D (0:7)
Active low — This signal enables the data bit 0-bus.
DATA GATE CONTROL
Active high — Signal to latch read data 0-7 on a 16
bit read of a 8 bit device.
Br~RLSSRSHoBsSSSsay
VIRseens
vo
vo
vo
vo
Vo
vo
vo
vo
vo
1/O
Vo
Vo
vo
Vo
vo
Vo
1/0
vo
Vo
vo
Vo
1/0
Vo
NC24SEN
PC40-III SERVICE MANUAL
DATA BUS ENABLE D (8:15)
Active low — This signal enables the data bit 8-15
bus.
NYIOW 1/0 WRITE COMMAND
Active low — Signal to indicate a 1/O write during
a CPU, DMA, or Master cycle.
NYIOR 1/0 READ COMMAND
Active low — Signal to indicate a I/O read during a
CPU, DMA, or Master Cycle.
NIOW PC BUS I/O WRITE COMMAND
Active low — Signal to indicate a I/O write during
a CPU, DMA, or Master Cycle.
NIOR PC BUS I/O WRITE COMMAND
Active low — Signal to indicate a I/O read during a
CPU, DMA, or Master Cycle.
NRTCCS REAL TIME CLOCK CHIP SELECT
Active low
NRTCRD REAL TIME CLOCK READ
Active low
NRTCWR_ REAL TIME CLOCK WRITE
Active low
DO 80286 DATA BIT 0
D1 80286 DATA BIT 1
D2 80286 DATA BIT 2
D3 80286 DATA BIT 3
D4 80286 DATA BIT 4
DS 80286 DATA BIT 5
D6 80286 DATA BIT 6
D7 80286 DATA BIT 7
D8 80286 DATA BIT 8
D9 80286 DATA BIT 9
D10 80286 DATA BIT 10
Dll 80286 DATA BIT 11
D12 80286 DATA BIT 12
D13 80286 DATA BIT 13
D14 80286 DATA BIT 14
D15 80286 DATA BIT 15
DATAO AT DATA BUS BIT 0
DATA1 AT DATA BUS BIT 1
DATA2_ AT DATA BUS BIT 2
DATA3 = AT DATA BUS BIT 3
DATA4 = AT DATA BUS BIT 4
DATAS AT DATA BUS BIT 5
DATA6 AT DATA BUS BIT 6
DATA7 AT DATA BUS BIT 7
DATA8 AT DATA BUS BIT 8
DATA9 AT DATA BUS BIT 9
DATA10_ AT DATA BUS BIT 10
DATA11_ AT DATA BUS BIT 11
DATA12_ AT DATA BUS BIT 12
DATA13_ AT DATA BUS BIT 13
DATA14_ AT DATA BUS BIT 14
DATA15_ AT DATA BUS BIT 15
EDATAO PERIPHERAL DATA BUS BIT 0
EDATA1 PERIPHERAL DATA BUS BIT 1
EDATA2 PERIPHERAL DATA BUS BIT 2
EDATA3 PERIPHERAL DATA BUS BIT 3
EDATA4 PERIPHERAL DATA BUS BIT 4
EDATAS PERIPHERAL DATA BUS BIT 5
EDATA6 PERIPHERAL DATA BUS BIT 6
EDATA7 PERIPHERAL DATA BUS BIT 7
vcci 5V + 5%
vCC2 5V + 5%
vcc3 5V + 5%
vVCC4 5V + 5%
VCCS 5V + 5%
VCC6 5V + 5%
vcc7 5V + 5%
vCcs 5V + 5%
GDD1 GROUND
GDD2 GROUND
GDD3 GROUND
GDD4 GROUND
GDDS5 GROUND
GDD6 GROUND
GDD7 GROUND
GDD8 GROUND
GDD9 GROUND
GDD10 GROUND
PIN PIN PLCC PGA
SYMBOL TYPE PINS PINS
RSET IN 36 Ll
MCLK IN 1% G12
VCLKO IN S% HI3
VCLK1 IN/OUT 74 H12
VCLK2 IN/OUT 73 Hll
Ald IN 28 G1
Al8 IN 27 G3
All IN 24 F2
Al6 IN 23 F3
Al5 IN 22 El
DAIS IN/OUT 20 D1
DA14 IN/OUT 19 D2
DA13. IN/OUT 18 Cl
DA12 IN/OUT 17 C2
DAllL IN/OUT 16 Bl
DA1O IN/OUT 14 Al
DA9 IN/OUT 13 B3
DA8 IN/OUT 12 A2
DAT IN/OUT 46 MS
DAG IN/OUT 45 N4
DAS IN/OUT 44 M4
DA4 IN/OUT 43 N3
DA3 IN/OUT 42 M3
DA2 IN/OUT 41 N2
DAI IN/OUT 40 M2
DAO IN/OUT 39 N1
EMEM IN 21 E2
EION IN 33 32
BHEN IN 9 A4
MRDN IN 31 H3
MWRN IN 32 v1
IORN IN 29 Hl
IOWN IN 30 H2
MD1S IN/OUT 89 8 Aj13
MD14 IN/OUT 9 B12
MD13_ IN/OUT 91 Al2
MD12 IN/OUT 92 Bll
MD11 IN/OUT 93 All
MD10 IN/OUT 94 B10
MD9 IN/OUT 95 Al0
MD8 IN/OUT 9% BS
PC40-III SERVICE MANUAL
6) PVGA-1A VIDEO CNTRL 390302-01
DESCRIPTION
Active high signal from external circuit during power up
Up to 36 MHz for 120 ns DRAMS
Up to 44.5 MHz for 100 ns DRAMS
25.175 MHz reference clock input
28.322 MHz clock input*
User defined external clock input*
Address bus bit 19
Address bus bit 18
Address bus bit 17
Address bus bit 16
Address bus bit 15
Multiplexed data bit 15 with Monitor type input
Multiplexed data/address bus bit 14
Multiplexed data/address bus bit 13
Multiplexed data/address bus bit 12
Multiplexed data/address bus bit 11
Multiplexed data/address bus bit 10
Multiplexed data/address bus bit 9
Multiplexed data/address bus bit 8
Multiplexed data/address bus bit 7
Multiplexed data/address bus bit 6
Multiplexed data/address bus bit 5
Multiplexed data/address bus bit 4
Multiplexed data/address bus bit 3
Multiplexed data/address bus bit 2
Multiplexed data/address bus bit 1
Multiplexed data/address bus bit 0
Enable display memory. Active high
Programmable enable I/O. Active low or high
Bus high byte enable. Active low
Display memory read strobe. Active low
Display memory write strobe. Active low
I/O read strobe. Active low
I/O write strobe. Active low
Display memory data bit 15
Display memory data bit 14
Display memory data bit 13
Display memory data bit 12
Display memory data bit 11
Display memory data bit 10
Display memory data bit 9
Display memory data bit 8
5-10
PIN
PIN PLCC PGA
SYMBOL TYPE PINS PINS DESCRIPTION
MD7
MD6
MDS
MD4
MD3
MD2
MD1
MDO
RAS10N
CAS10N
OEI10N
WEIN
WEON
RAS32N
CAS32N
OE32N
WE3N
WE2N
MA8
MA7
MA6
MAS
MA2
MAI
MAO
MA4
MA3
VID7
VID6
VIDS
VID4
VID3
VID2
VID1
VIDO
PLCK
BLNKN
HSYNC
VSYNC
RPLTN
SKDBKN
WPLTN
REDY
IRQ
DS16N
EBROMN
EABUFN
EDBUFN
DIR
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
97
98
ARALSSSSESSSASGRASSSESSRRSSZauansy
£ESS238E
SSa 3eg
4LARG+ Base
A9
ce
B8
ci
A7
A6
B6
C6
F13
F12
Fll
C13
D12
E13
E12
D13
C12
B13
Mil
M12
M13
L12
K13
312
513
LB
K12
M6
N6
N7
N8&
M8
N9
N10
N12
M10
Nll
NS
B4
M9
‘ Kil
K2
BS
L2
Ml
Fl
L7
G13
A8
B2
G2
M7
N13
Gil
B7
Display memory data or configuration bit 7 upon power up
Display memory data or configuration bit 6 upon power up
Display memory data or configuration bit 5 upon power up
Display memory data or configuration bit 4 upon power up
Display memory data or configuration bit 3 upon power up
Display memory data or configuration bit 2 upon power up
Display memory data or configuration bit 1 upon power up
Display memory data or configuration bit 0 upon power up
Row address strobe bank 0 (Memory Maps 1 & 0). Active low
Column address strobe bank 0. Active low
Output enable bank 0. Active low
Write enable bank 0 upper byté (Memory map 1). Active low
Write enable bank 0 lower byte (Memory map 0). Active low
Row address strobe bank 1 (Memory maps 3 and 2). Active low
Column address strobe bank 1. Active low
Output enable bank 1. Active low
Write enable bank 1 upper byte (Memory map 3). Active low
Write enable bank 1 lower byte (Memory map 2). Active low
Display memory multiplexed RAS/CAS address bit 8
Display memory multiplexed RAS/CAS address bit 7
Display memory multiplexed RAS/CAS address bit 6
Display memory multiplexed RAS/CAS address bit 5
Display memory multiplexed RAS/CAS address bit 2
Display memory multiplexed RAS/CAS address bit 1
Display memory multiplexed RAS/CAS address bit 0
Display memory multiplexed RAS/CAS address bit 4
Display memory multiplexed RAS/CAS address bit 3
Video color look up table address bit 7
Video color look up table address bit 6
Video color look up table address bit 5
Video color look up table address bit 4
Video color look up table address bit 3
Video color look up table address bit 2
Video color look up table address bit 1
Video color look up table address bit 0
Pixel clock
Color monitor blank pulse. Active low
Color monitor horizontal synchronization pulse. Active high
Color monitor vertical synchronization pulse. Active high
Read color look up pallet. Active low
Card select feedback during memory or I/O access. Active low
Write color look up pallet. Active low
A tristate active high ready output to signal processor that memory access
is available
Programmable processor interrupt request. Active low or high with tristate
Programmable enable 16 bit word transfer. Active low
Enable BIOS ROM. Active low
Enable processor address buffer. Active low
Enable processor data buffer. Active low
Directional control for processor data bus. Bits 0 through 15 high for
read cycles
+5V DC
+5V DC
+5V DC
+5V DC
GND
GND
GND
GND
GND
GND
PC40-III SERVICE MANUAL
7) PPC1 PARALLEL PRINTER CNTRL 318091-01
1
2
3
4
5
6
1
8
9
PIN CODE DESCKivtION
SSSGARRER ES eeu sHMaune
SSSSRASESESBSNRREGE
GND
D7
DATO
AO
GND
DATI
Al
DAT2
A2
DAT3
A3
DAT4
A4
DATS
AS
GND
DAT6
PAPE
Ground
Data Bit 7 In
Data Bit 0 Out
Address Line 0
Ground
Data Bit 1 Out
Address Line 1
Data Bit 2 Out
Address Line 2
Data Bit 3 Out
Address Line 3
Data Bit 4 Out
Address Line 4
Data Bit 5 Out
Address Line 5
Ground
Data Bit 6 Out
Paper Out
Data Bit 7 Out
Printer busy
Interrupt #7
Acknowledge
Chip Select
Printer Select
Error
Strobe
Autofeed
Initial Reset
Select From Printer
V/O Write
1/O Read
Reset
Data Bit 0 In
Data Bit 1 In
+5V
Data Bit 2 In
Data Bit 3 In
Data Bit 4 In
Data Bit 5 In
Data Bit 6 In
PC40-IlI SERVICE MANUAL
D6
DS
D4
D3
D2
vcc
D1
DO
RSTN
IORN
IOWN
SLCN
ININ
AFXN
STBN
ERRN
SLCT
CEN
ACKN
IRQ
D/P PIN
NUMBER MNEMONIC
RD
V1
2/2
3/3
4/4
5/5
6/6
7-14
7-14
18/15
16/16
17
17/18
18/19
19/20
20/21
21/
/22
/23
22/24
23/
128
/%6
24/27
-WR
cs
Ao
TC
DBO thru
DB7
DMA
IRQ
TDOR
LDCR
RST
RDD
CLK2
XT2
XT2
DRV
CLK1
XTI
xTl
PCVAL
SIGNAL
NAME
READ
WRITE
CHIP SELECT
ADDRESS LINE
DMA
ACKNOWLEDGE
TERMINAL
COUNT
DATA BUS 0 thru
DATA BUS 7
DIRECT MEMORY
ACCESS
INTERRUPT
LOAD
OPERATIONS
REGISTER
LOAD CONTROL
REGISTER
RESET
READ DISK
DATA
CLOCK2
XTALZ
XTAL2
DRIVE TYPE
CLOCK1
XTALI
XTALI
PRECOMPEN-
SATION VALUE
PC40-III SERVICE MANUAL
8) WD37C65 FDC 390304-03
1
2
3
4
5
6
7
8
9
DMA
IRQ
LDCR
ADD
1/O FUNCTION
Vo
- =— = ©
=O
Control signal for transfer of data or status onto the data bus by the WD37C65.
Control signal for latching data from the bus into the WD37C65 Buffer Register.
Selected when 0 (low) allowing RD or WR operation from the Host.
Address line selecting data (-1) or status (-0) information. (AO - logic 0 during WR Is illegal).
Used by the DMA controller to transfer data from the WD37C65 onto the bus. Logical equivalent to CS and A0-1. In
Special or PC/AT Mode, this signal is qualified by DMAEN from the Operations Register.
This signal indicates to WD37C65 that data transfer is complete. If DMA operational mode is selected for command execu-
tion, TC will be qualified by DACK, but not in the programmed I/O execution. In PC/AT or Special Mode, qualification by
requires the Operations Register signal DMAEN to be logically true. Note also that in PC/AT Mode, TC will be quali-
fied by DACK, whether in DMA or non-DMA Host operation. Programmed I/O in PC/AT Mode will cause an abnormal ter-
mination error at the completion of a command.
8-Bit, bi-directional, tri-state, data bus. DO is the least significant bit (LSB). D7 is the most significant bit (MSB).
DMA request for byte transfers of data. In Special or PC/AT mode, this pin Is tri-stated, enabled by the DMAEN signal from
the Operation Register. This pin is driven in the Base Mode.
Interrupt request indicating the completion of command execution or data transfer requests (in non-DMA mode). Normally
driven in base mode. In Special or PC/AT Mode, this pin is tri-stated, enabled by the DMAEN signal from the Operations
Register.
Not connected in the 44 Pin PLCC.
Address decode which enables the loading of the Operations Register. Internally gated with WR creates the strobe which
latches the data bus into the Operations Register.
Address decode which enables loading of the Control Register. Internally gated with WR creates the strobe which latches the
two LSBs from the data bus into the Control Register.
Resets controller, placing microsequencer in idle. Resets device outputs. Puts device in Base Mode, not PC/AT or Special
Mode.
This is the raw serial bit stream from the disk drive. Each falling edge of the pulses represents a flux transition of the encoded
data.
TTL level clock input used for non-standard data rates; is 9.6MHz for 300 Kb/s, and can only be selected from the Control
Register.
XTAL oscillator drive output for 44 Pin PLCC (See Figure 6). Should be left floating if TTL inputs used at pin 23.
XTAL oscillator input used for non-standard data rates. It miay be driven with TTL level signal.
Drive type input indicates to the device that a two-speed spindle motor is used if logic is 0. In that case, the second clock input
will never be selected and must be grounded.
TTL level clock input is used to generate all internal timings for standard data rates. Frequency must be 16MHz + 0.1%, and
may have 40/60 or 60/40 duty cycle.
XTAL oscillator drive output for 44 Pin PLCC (See Figure 6). Should be left floating if TTL inputs used at pin 26.
XTAL oscillator input requiring 16MHz crystal. This oscillator is used for all standard data rates, and may be driven with a
TTL level signal.
PRECOMPENSATION VALUE select input. This pin determines the amount of write precompensation used on the inner
tracks of the diskette. Logic 1 - 125ns, Logic 0 - 187 ns.
5-13
D/P PIN
NUMBER MNEMONIC
25/28
26/29
27/30
28/31
29/32
30/33
31/34
32/35
33/36
34/37
35/38
36/39
37/41
38/42
39/43
40/44
HS
WE
WD
DIRC
STEP
DSI
vss
DS2z
MOi, DS3
M02, DS4
SIGNAL
NAME
GROUND
DRIVE SELECT 2
PC40-IIT SERVICE MANUAL
1/0 FUNCTION
0000 6 86
°
(3 ~)
Sen rie: ihe (HCD) output selects the head (side) of the floppy disk that is being read or written. Logic 1 - side 0.
ic 0 - side 1.
Pa igus output becomes true, active low, just prior to writing on the diskette. This allows current to flow through the write
head.
This HCD output is WRITE DATA. Each falling edge of the encoded data pulse stream causes a flux transition on the media.
This HCD output determines the direction of the head stepper motor. Logic 1 - outward motion. Logic 0 - inward motion.
This HCD output issues an active low pulse for each track to track movement of the head.
This HCD output, when active low is DRIVE SELECT 1 in PC/AT Mode, enabling the interface in this disk drive. This signal
comes from the Operations Register. In Base, or Special Mode, this output is #1 of the four decoded Unit Selects, as specified
in the device command syntax.
Ground.
This HCD output when active low is DRIVE SELECT 2, in PC/AT Mode, enabling the interface in this disk drive. This signal
comes from the Operations Register. in Base or the Special Mode, this output is #2 of the four decoded Unit Selects as spect-
fied in the device command syntax.
This HCD output when active low is MOTOR ON enable for disk drive #1, in PC/AT Mode. This signal comes from the
Operations Register. In the Base or Special Mode, this output is #3 of the four decoded Unit Selects as specified in the device
command syntax.
This HCD output when active low is MOTOR ON enable for disk drive #2, in PC/AT mode. This signal comes from the Oper-
ations Register. In the Base or Special Mode, this output is #4 of the four decoded Unit Selects as specified in the device
command syntax.
This HDC output when active low causes the head to be loaded against the media in the selected drive.
This HCD output when active low causes a REDUCED WRITE CURRENT when bit density is increased toward the inner
tracks, becoming active when tracks greater than 28 are accessed. This condition is valid for Base or Special Mode, and
is indicative of when write precompensation is necessary. In the PC/AT mode, (on two-speed disk drives) this signal will
be active when 250 MFM or 125 FM data rate is selected.
Not connected in the 44 Pin PLCC.
This Schmitt Trigger (ST) input senses status from the disk drive indicating active low, when a diskette is WRITE
PROTECTED.
This ST input senses status from disk drive indicating active low, when the head is positioned over the outermost track,
This ST input senses status from the disk drive indicating active low, when the head Is positioned over the beginning of a track
marked by an index hole.
Input power supply.
5-14
PIN
NUMBER
1-8
10
11
2
14
5
RBRSORRSSSGS
PIN NAME
DATA BUS
RECEIVE CLK
SERIAL INPUT
SERIAL OUTPUT
CHIP SELECT
CHIP SELECT
CHIP SELECT
BAUDOUT
EXTERNAL CLOCK IN
EXTERNAL CLOCK OUT
DATA OUT STROBE
DATA OUT STROBE
GROUND
DATA IN STROBE
DATA IN STROBE
DRIVER DISABLE
CHIP SELECT OUT
ADDRESS STROBE
REGISTER SELECT A2
REGISTER SELECT Al
REGISTER SELECT A0
NO CONNECT
INTERRUPT
OUTPUT 2
REQUEST TO SEND
DATA TERMINAL
READY
OUTPUT 1
MASTER RESET
CLEAR TO SEND
DATA SET READY
RECEIVED LINE
SIGNAL DETECT
RING INDICATOR
+5V
SYMBOL
D0-D7
RCLK
SIN
SOUT
cso
cs
(o7}
BAUDOUT
XTAL 1
XTAL 2
DOSTR
DOSTR
vss
DISTR
DISTR
DDIS
CSOUT
ADS
$343
INTRPT
fa Bags9 338
PC40-IIT SERVICE MANUAL
9) 8250 SERIAL INTERFACE 380205-01
1
2
3
4
5
6
7
8
9
FUNCTION
3-state input/output lines. Bi-directional communication lines between WD8250 and Data Bus. All assembled data TX
and RX, control words, and status information are transferred via the DO-D7 data bus.
This input is the 16X baud rate clock for the receiver section of the chip (may be tied to BAUDOUT pin 15).
Received Serial Data In from the communications link (Peripheral device, modem or data set).
Transmitted Serial Data Out to the communication link. The SOUT signal is set to a (logic 1) marking condition upon
a MASTER RESET.
When CSO and CS} are high, and CSz2 is low, chip is selected. Selection is complete when the address strobe ADS latches
the chip select signals.
16X clock signal for the transmitter section of the WD8250. The clock rate is equal to the oscillator frequency divided
by the divisor loaded into the divisor latches. The BAUDOUT signal may be used to clock the receiver by tying to (pin
9) RCLK.
These pins connect the crystal or signal clock to the WD8250 baud rate divisor circuit. See Fig. 3 and Fig. 4 for circuit
connection diagrams.
When the chip has been selected, a low DOSIR or high DOSTR will latch data into the selected WD8250 register (a CPU
write). Only one of these lines need be used. Tie unused line to its inactive state. DOSTR — high or DOSTR — low.
System signal ground.
When chip has been selected, a low DISTR or high DISTR will allow a read of the selected WD8250 register (a CPU read).
Only one of these lines need be used. Tie unused line to its inactive state. DISTR — high cr DISTR — low.
Output goes low whenever data is being read from the WD8250. Can be used to reverse data direction of external transceiver.
Output goes high when chip is selected. No data transfer can be initiated until CSOUT is high.
When low, provides latching for Register Select (A0, Al, A2,) and Chip Select (CSO, CS1, C52)
NOTE: The rising edge (1) of the signal is required when the Register Select (AO, Al, A2) and the Chip Select (CSO,
CS1, CS2) signals are not stable for the duration of a read or write operation. If not required, the ADS input
can be tied permanently low.
These three inputs are used to select a WD8250 internal register during a data read or write. See Table below.
No Connect
Output goes high whenever an enabled interrupt is pending.
User-designated output that can be programmed by Bit 3 of the modem control register = 1, causes OUT2 to go low.
Output when low informs the modem or data set that the WD8250 is ready to transmit data. See Modem Control Register.
Output when low informs the modem or data set that the WD8250 {is ready to communicate.
User designated output can be programmed by Bit 2 of Modem Control Register = 1 causes OUTI to go low.
When high clears the registers to states as indicated in Table 1.
Input from DCE indicating remote device is ready to transmit. See Modem Control Register.
Input from DCE used to indicate the status of the local data set. See Modem Control Register.
Input from DCE indicating that it is receiving a signal which meets its signal quality conditions. See Modem Control Register.
Input, when low, indicates that a ringing signal is being received by the modem or data set. See Modem Control Register.
+5 Volt Supply.
5-15
PC40-III SERVICE MANUAL
10) 5720 MOUSE CONTROL 318087-01
RSO
NRESET
PSCLK
BAO
BAI
VDD
PNBIORC
BAEN
PIN SIGNAL NAME PAD TYPE
1 VDD
2 NBDACKO
3 BA3
4 BA2
5 BA1
6 BAO
7 PSCLK
8 NRESET
9 RSO
10 PNWAIT
il RS1
12 IOCHRDY
13 RS2
14 BDO
15 BDI
16 BD2
17 BD3
18 VSS
19 VSS
20 BD4
21 BDS
22 BD6
23 BD7
24 PNBDACK2
25 NIDIR
26 NOVID
27 NBR
28 PNMONO
29 NBM
30 NBL
31 HQ
31 HP
33 vQ
34 vP
INP
INP
INP
INP
INP
INP
INP Schmitt trigger
INP
INP with pullup
INP
OUT open drain
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I/O with pullup
I/O with pullup
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V/O with pullup
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I/O with pullup
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OUT
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INP Schmitt trigger with pullup
INP with pullup
INP Schmitt trigger with pullup
INP Schmitt trigger with pullup
INP Schmitt trigger with pullup
INP Schmitt trigger with pullup
INP Schmitt trigger with pullup
INP Schmitt trigger with pullup
SSSLRRSS-Mvavasee
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OUT tristate
OUT tristate
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INP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
INP Schmitt trigger
INP Schmitt tri,ger
INP
INP
INP
INP
INP
INP
INP
INP
INP
5-16
PC40-III SERVICE MANUAL
Schematic #313056, Rev. C
Sheet 1 of 12
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5-17
PC40-II] SERVICE MANUAL
Schematic #313056, Rev. C
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5-18
Schematic #313056, Rev. C
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Schematic #313056, Rev. C
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Sheet 9 of 12
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PC40-III SERVICE MANUAL
APPENDIX A
POWER SUPPLY SECTION
¢ PC40-111 POWER SUPPLY SCHEMATIC
(VDE, BS1, SEV, 5AA)
e PC40-111 POWER SUPPLY SCHEMATIC
(CSA, UL)
INFORMATION IN THIS SECTION IS FOR REFERENCE ONLY.
COMMODORE WILL NOT SUPPLY COMPONENT PARTS FOR
OEM ASSEMBLIES.
PC40-III SERVICE MANUAL
PC40-111 POWER SUPPLY 390269
Input Requirements VDE, BS1 CSA, UL
AC INPUT Parameter _| | 390269-01 390269-02
Voltage 230 VAC 110 VAC
- Voltage Range 180 - 270 VAC 90 - 135 VAC
Frequency (Hz) 50 Hz 50 - 60 Hz
Surge Protection 3 KV, 25 A for 30 usec 3 KV, 25 A for 30 usec
(maximum)
Inrush Current 40 A for
(maximum) 30 usec
CP2 7x6)
BOTTOM VIEW
CN1
A-l
PC40-IlT SERVICE MANUAL
NOTE: FOR REFERENCE ONLY, —COLOR CODES AND SPECIFICATIONS MAY CHANGE.
Connector CN1 : CPU
PWR GOOD 150.0 +10%
-12V 150.0 + 10%
+12V 150.0 + 10%
GND 150.0 + 10%
GND 150.0 + 10%
+5V 150.0 + 10%
Connector CN1 (Recommended)
| Vendor | Housing | Pin |__Remarks
350715-1 350552-1 MATE-n-LOK
BURNDY UPH 600 {| UHM2200 | — ~~ |
Connector CN2 : HD 1
Prin [SIGNAL | AWG | COLOR | LENGTH Gam |
330.0 +20%
330.0 +20%
330.0 +20%
330.0 +20%
Connector CN2 (Recommended)
Vendor | Housing [Pin | Remarks
AMP 1-480424-0 | 611117-1 MATE-n-LOK
J.S. TERM LCP-04 SLc2IT20 | — |
PC40-III SERVICE MANUAL
330.0 +20%
330.0 +20%
330.0 +20%
330.0 +20%
Connector CN3 (Recommended)
| Vendor | Housing | Pin | Remarks
1-480424-0 | 611117-1 | MATE-n-LOK
J.S. TERM LCP-04 sLc2iTz0 | — |
Connector CN4 = FDD 2
| PIN | SIGNAL COLOR | LENGTH (mm)
18 ORG 150.0 +10%
18 BLU 150.0 + 10%
18 BLU 150.0 +10%
18 150.0 + 10%
NOTE: Cable CN4 shall be daisy-chained from connector CN3.
Connector CN4 (Recommended)
[vendor [Housing [Pin | Remarks |
1-480424-0 | 611117-1_ | MATE-n-LOK
J.S. TERM LCP-04 SLC21IT20 | — |
PC40-III SERVICE MANUAL
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PC40-IlT SERVICE MANUAL
APPENDIX B
DISK DRIVE SECTION
¢ PC40-III 40MB HARD DRIVE
¢ PC40-III Hard Drive PN #313065-01
Vendor : Quantum
Model : Prodrive 40AT
Reprinted with Permission of Quantum Corp. All rights reserved.
e PC40-III FLOPPY DISK DRIVE
¢ PC40-III Floppy Disk Drive PN #380825-02
Vendor : Chinon.
Model : FZ506 ;
Reprinted with Permission of Chinon America Inc. All rights reserved.
e 910, 920 ADD ON NOTES
INFORMATION IN THIS SECTION IS FOR REFERENCE ONLY.
COMMODORE WILL NOT SUPPLY COMPONENT PARTS FOR
OEM ASSEMBLIES.
The information included in this section is for reference only. Vendors are subject to change without notice.
Commodore service will provide alignment procedures and test diagnostics to authorized service centers for field repairs. The
drive exchange program will be in effect and Commodore service will not provide discrete components for field replacement.
PC40-IIT SERVICE MANUAL
PC40-I1I HARD DRIVE 313065-01
GENERAL DESCRIPTION
The Quantum ProDrive Series™ is a family of ten 32-inch form factor hard disk drives using non-removable rigid disk plat-
ters as storage media. These drives feature formatted capacities ranging from 42 to 168 megabytes and a variety of interfaces.
This manual covers the ProDrive™ 40AT and ProDrive 80AT, which feature an IBM PC-AT® embedded controller and are
available with or without an adapter board. With the adapter board, the ProDrive 40AT/80AT can plug directly into a 16-bit
expansion slot in an IBM PC AT or compatible personal computer. Without the adapter board, the ProDrive 40AT/80AT
is compatible with other AT-Bus architectures and can be plugged into an embedded AT adapter or into an existing adapter
board in a PC AT compatible.
The ProDrive 40AT features 42 megabytes of formatted capacity on two disks with three movable heads; the ProDrive 80AT
provides 84 megabytes of formatted capacity on three disks with six movable heads. Media defects and error recovery are
efficiently managed within these products and can be fully transparent to the user. The ProDrive Series drives feature an in-
novative design using an integrated controller, minimum number of parts, and close control of product quality during manufac-
ture, resulting in low cost, highly reliable products.
NOTE: Throughout this manual, ProDrive 40AT/80AT or ProDrive will refer to either the ProDrive 40AT or the
ProDrive 80AT. ProDrive 40AT and ProDrive 80AT will be used to refer specifically to the 42 and 84
megabyte versions, respectively.
SPECIFICATIONS
Key features of the ProDrive 40AT/80AT include:
e Formatted storage capacity of 42 or 84 megabytes
Industry standard 3%-inch form factor
19 millisecond average access time
Data transfer rate up to 4.0 megabytes/second using programmed I/O
64K-byte look-ahead DisCache®
48-bit computer generated Error Correcting Code (ECC) with 11-bit burst correction capability
Automatic retry for read disk errors
Transparent defect mapping
High-performance in-line defective sector skipping and reassignment of new defective sectors without need
to reformat
Patented AIRLOCK® automatic shipping lock and dedicated landing zone
Read/Write with 1:1 interleave operation
Emulation of IBM PC AT task file register and all AT fixed disk commands
Ability to daisy-chain two drives on the interface
PHYSICAL SPECIFICATIONS
Environmental Limits
Ambient Temperature — Non-Operating: —40°F to 140°F (—40°C to 65°C)
42°F/hr (20°C/hr) gradient
Operating: 39°F to 122°F (4°C to 50°C)
23°F/hr (10°C/hr) gradient
Ambient Relative Humidity — Non-Operating: 5% to 95% without condensation
Maximum wet bulb = 115°F (46°C)
Operating: 8% to 85% without condensation
Maximum wet bulb = 79°F (26°C)
Altitude (relative to sea level) — Non-Operating: — 200 (— 60M) to 40,000 ft. (12 km)
Operating: — 200 (— 60M) to 10,000 ft. (3 km)
©Copyright 1988, Quantum Corporation. All rights reserved.
ProDrive™ and ProDrive Series™ are trademarks of Quantum Corporation
AIRLOCK® and DisCache® are registered trademarks of Quantum Corporation
Printed in U.S.A.
B-1
PC40-Ill SERVICE MANUAL
Mechanical Dimensions (Exclusive of Faceplate)
Height = 1.625 in. (41.3 mm)
Width = 4.0 in. (101.6 mm)
Depth = 5.75 in. (144.9 mm)
Weight = 1.9 Ib. (0.88 kg)
Heat Dissipation
Average Power Consumption (idle): 8 Watts (27.3 BTU/Hr)
Typical Power Consumption (30% Seeking): 9Watts (30.7 BTU/Hr)
Shock and Vibration
The table below lists specified levels for shock and vibration applied to any of the three mutually perpendicular axes (the prin-
cipal drive base axes). The term ‘‘operating’’ implies that the drive will be fully functional while being subjected to the shock
or vibration level listed during operation. ‘‘Non-operating’’ implies that there will be no change in performance once the drive
is powered up after being subjected to the listed shock or vibration in the powered-down (non-operating) condition.
Vibration and Shock Specification
Operating Non-Operating
VIBRATION:
5-500 Hz Sine Wave (Peak to Peak) 0.50 G 2.00 G
1 Oct/Min Sine Sweep
SHOCK: 10 G (1 soft error/shock)
Y% Sine Wave of 60 G
11 msec Duration (10 hits maximum) (6 G No soft errors)
In addition, the ProDrive as packaged in the shipping container will withstand drops onto a concrete surface from 48 inches
on all surfaces, six edges and three corners. It will withstand vibration applied to the container of 0.5 G, 5-100 Hz (0 to Peak)
and 1.5 G, 100-500 Hz (0 to Peak).
PERFORMANCE SPECIFICATIONS
Capacity
ProDrive 40AT ProDrive 80AT
Formatted capacity (MB) 42* 84*
Number of 512 byte sectors 82,029 164,058
*40, and 80 megabytes, respectively when a megabyte is defined as 220 bytes
Data Transfer Rates Buffer to AT-Bus - Up to 4.0 Mbytes/second using programmed I/O
Disk to Buffer - Up to 1.25 Mbytes/second in bursts
Seek Times/Miscellaneous Times
TYPICAL MAXIMUM
NOMINAL NOMINAL WORST CASE
DESCRIPTION CONDITION CONDITION CONDITION
Single Track Seek (msec)
Average Seek (msec)
Y Stroke Seek (msec)
Full Stoke Seek (msec)
Average Rotational Latency (msec)
Sequential Head Switch (msec)
Power-Up Time (sec)
PC40-Ill SERVICE MANUAL
NOTES: Quoted seek times include head settling time but do not include command overhead or latency time. Seek time is
the time required for the actuator to seek and settle on track.
Seek times are measured by averaging 1000 seeks of the indicated length. Average seek time is the average of 1000
random seeks. In the rare occurrence of a seek error, any individual seek may take up to 5 seconds for recovery.
Sequential head switch time is the time required for the head to move from the end of the last sector on a track
to the beginning of the next sequential sector, located on the next track, same cylinder. This time is fixed by the
track skewing feature of the drive. (See Appendix B.)
Power-up time is the time from the supply voltages reach operating range to the time the drive is able to accept all
commands.
Nominal conditions are defined as 25°C ambient temperature, nominal supply voltages, and no applied shock or
vibration. Worst case conditions are defined as worst case extremes of temperature and supply voltages.
Media Quality
The ProDrive features defect management, which eliminates the need to manually indentify defects. Defect management is
completely transparent to the user. See Appendix C for a detailed description of the ProDrive’s defect handling procedure
and ECC capability.
Error Rates
Random Data Errors (2):
Defect Data Errors (3):
Unrecoverable Data Errors (4):
Seek Errors (5):
Error rates are defined as follows:
1 error per 1910 bits read (maximum)
1 error per 10/2 bits read (maximum)
1 error per 10!4 bits read (maximum)
1 error per 10° seeks (maximum)
1) A data error is one (1) sector read incorrectly. Data error rates are defined as average rates measured over at least 1000
different sectors under any of the specified conditions except applied shock or vibration.
2) Random errors are those which do not exhibit a repeating error pattern, i.e, the error does not occur twice in a row within
a specified number of retry reads; the default is eight. (Retries are terminated once data is read correctly.) The sectors
will not be automatically reallocated since the errors are probably not due to media defects.
3) Defect errors are those which exhibit a repeating error pattern, i.e., the error occurs twice in a row within eight retry reads,
and cannot be read without error up to that point. Such errors are likely due to media defects.
4) Unrecoverable errors are those whose final retry error pattern is uncorrectable using ECC: retry reads are terminated by
either a repeating error pattern, or eight attempts without reading correctly. :
5) A seek error is any seek in which the drive does not locate the desired cylinder, or any seek in which the drive must go
through a full recalibration routine to locate the desired cylinder. A full recalibration takes approximately five seconds.
FUNCTIONAL SPECIFICATIONS
Nom Rotational Speed (RPM)
Max Recording Density (bpi)
Max Flux Density (fci)
Track Density (tpi)
Data Cylinders
Data Tracks
R/W Heads
Encoding Scheme
PHYSICAL FORMAT
ProDrive 40AT ProDrive 80AT
3,662 +0.3% 3,662 + 0.3%
22,055 22,055
14,700 14,700
1,000 1,000
834 834
2,502 5,004
3 6
RLL 2,7
PC40-IIT SERVICE MANUAL
LOGICAL FORMAT
The logical layout is how the drive appears to an AT-Bus system.
ProDrive 40AT ProDrive 80AT
Data Cylinders
Sectors/Track
R/W Heads
RELIABILITY SPECIFICATIONS
MTBF (Mean Time Between Failure): 50,000 POH (Power On Hours) typical usage
PM (Preventative Maintenance): Not required
MTTR (Mean Time To Repair): 30 minutes
Start/Stop: 10,000 cycles
ACOUSTICS
Idle Mode: 45 dBa maximum at | foot in any direction
All dimensions in millimeters
ProDrive Mechanical Dimensions
B-4
PC40-III SERVICE MANUAL
MOUNTING/DIMENSIONS (DIMENSIONS EXCLUSIVE OF FACEPLATE)
The drive may be mounted in any orientation.
Clearance from the drive to any other surface (except shock mount brackets or faceplate) should be 0.10 inch minimum.
HEIGHT 1.625 in. 41.3 mm
WIDTH 4.0 in. 101.6 mm
DEPTH 5.75in. 146.1 mm
WEIGHT 1.9 lb. 0.88 kg
144.9
£.25
2.74.15 k 12.7+.15
101.6+.30
DIMENSIONS ARE IN MILLIMETERS; SCREW SIZE IS 6-32
41.2+.40
PC40-IlT HARD DRIVE
B-5
PC40-III SERVICE MANUAL
POWER REQUIREMENTS
No damage or loss of data occurs if power is applied or removed in any order or manner, except that data may be lost in
the sector being written to at the time of the power loss. This includes opening up or shorting out either voltage or return
line, and transient voltages + 10% to —100% from nominal, while powering up or down.
VOLTAGE +12V +5V
NOMINAL +12V +5V
TOLERANCE +10% +5%
CURRENT
TYPICAL (IDLE) 0.5A 0.5A
TYPICAL (SEEKING) 0.8A 0.6A
MAXIMUM (POWER-UP) 1.6A 0.65A
RIPPLE AND NOISE (MAXIMUM) 100mVp-p 50mVp-p
AVERAGE POWER CONSUMPTION 8W
TYPICAL POWER CONSUMPTION (30% SEEK) 9W
MAXIMUM POWER 11W
POWER RESET LIMITS
When powering up, the drive remains reset (inactive) until both supplies reach the upper threshold value. When powering
down, the drive becomes reset when either supply voltage drops below the lower threshold value. Hysteresis is 50m V minimum.
5V 4.50V TO 4.20V
12V 10.4V TO 9.70V
PC40-III Power Connector - HD
| PIN | Signal |
+12 Volts
Ground
Ground
+5 Volts
DC POWER CONNECTOR
The DC power connector (J1) is a 4-pin DuPont Connector (SK 20055-000) mounted on the back edge of the Printed Circuit.
Board (PCB) near the AT-Bus connector. See Figure 1. The recommended mating connector (P2) (AMP P/N 1-480424-0)
utilizes AMP pins [P/N 350078-4 (strip) or P/N 61173-4 (loose piece)]. J1 pins are labeled on the connector.
Pin 1 +12 volts DC
Pin 2 +12 volt return (ground)
Pin 3 +5 volt return (ground)
Pin 4 +5 volts DC
NOTE: Pins 2 and 3 are connected on the drive.
FIGURE 1 — DC POWER CONNECTOR (J1)
PC40-IlI SERVICE MANUAL
AT-BUS INTERFACE CONNECTOR
One AT-Bus interface cable connector (J2) is required for the ProDrive. Details of the signals required can be found in AT-Bus
Interface and Commands.
Connection to J2 is through a 40-pin Universal Header connector. A connector sketch is shown in Figure 2. A key slot is
provided to prevent incorrect installation of the mating connector. The recommended mating connector for J2 is xxxxx.
NOTE: Unkeyed mating connectors should not be used due to the possibility of plugging the connector in backwards.
CENTER KEY SLOT
<——— (BOTTOM VIEW)
POSITION #1 INDICATOR
goooodo00000000000000o0
goooo0ndg00o0o00000000o0
FIGURE 2 — AT-BUS INTERFACE CONNECTOR (J2)
JUMPER OPTIONS
Configuration of a ProDrive 40AT/80AT disk drive varies depending on the system in which it is to be installed. This section
describes the user-selectable hardware options available on the disk drive PCB. These jumpers should be set prior to installa-
tion. Figure 3 identifies the location of the shorting plugs and terminators on the drive PCB.
NOTE: Additional jumper options are provided on the adapter board for systems in which the adapter board is used with
the drive.
DC CONNECTOR (J1) MICROPROCESSOR
HDA CONNECTORS
BACK OF =
DRIVE FACE PLATE
SIDE
Mn Oy
AT-BUS CONNECTOR (32)
FIGURE 3 — Shorting Plug Locations on the Drive PCB
PC40-III SERVICE MANUAL
SELF SEEK TEST OPTION
The self seek test continuously exercises the actuator of the drive. When shorting plug option SS is installed, the drive will
perform random seek patterns, verifying track IDs after every seek. The pattern will repeat as long as power is applied to
the drive, until the shorting plug is removed, or until an error has occurred.
The ProDrive is sent from the factory with shorting plug SS not installed (Self Seek Test disabled).
DRIVE SELECT
Two drives can be daisy-chained on the AT-Bus interface. When two drives are attached, one must be configured as the primary
drive, and the other as the secondary drive, using the Drive Select (DS) jumper. With the DS shorting plug installed, the drive
is configured as the primary drive (Drive 0); with no shorting plug on jumper DS, the drive is configured as the secondary
drive (Drive 1).
The ProDrive is sent from the factory with the DS shorting plug installed (Drive 0)
RESERVED JUMPER
The third jumper is reserved for future use.
FACEPLATE LED OPERATION
The green LED located on the faceplate illuminates when the drive is executing a command. It lights at the beginning of a
command and does not go off until the command is completed or aborted.
ADAPTER BOARD
This section is relevant only for systems which implement the ProDrive AT-Bus drive with the adapter board.
ADAPTER BOARD JUMPER OPTIONS
Five jumpers labeled J2 through J6 are provided on the adapter board; the functions of these jumpers are described below.
See Figure for the locations of the jumpers on the PCB.
J2 - Allows the drives interrupt logic to control IRQ14. This jumper is provided for compatibility with systems whose
BIOS does not read the STATUS register when the drive issues an interrupt.
© for systems that do not read the STATUS register, jumper from the center pin of J2 to E4;
© for systems that do read the STATUS register, jumper from the center pin of J2 to E3.
J3 - Always open. Option for grounding pin #34 of the drive interface.
J4 - Forwards IO CH RDY to the drive for use with systems running Chips & Technologies chip set.
JS - Secondary board enable.
J6 - For manufacturers use only; do not install a jumper.
INTRODUCTION
The ProDrive 40AT/80AT uses the standardized IBM rC AT Bus interface and is available with or without an Adapter Board.
With the Adapter Board, the ProDrive can plug directly into a 16-bit expansion slot on an AT compatible computer. Without
the Adapter Board, the drive is compatible with other AT-Bus architectures and can be plugged into an embedded AT Adapter
or existing Adapter Board.
ADAPTER BOARD
The Adapter Board is an IBM PC AT I/O bus-compatible interface. The I/O extended bus connector is required for data
bus D8-D15, IRQ14 and IO CS16. The Adapter Board buffers data and control signals between the drive and the host system,
and performs address decoding of the Host Address Bus. The Task File Registers, which accept commands from the host
system BIOS, are located on the drive itself.
NOTE: Some host systems will not read the STATUS register after the drive issues an interrupt. In such cases, the interrupt will
not be acknowledged. A jumper option is provided on the Adapter Board to overcome this problem. This jumper allows
interrupts to be controlled by the drive’s interrupt logic. See jumper option J2.
AT-BUS INTERFACE CHARACTERISTICS
The AT-Bus interface supports one or two hard disk drives per adapter board, and will accomodate two adapter boards for
a total of four drives. Regardless of the number of drives, there is a master/slave relationship between the host and the drive.
The drive always maintains control of the bus; there is no arbitration.
ELECTRICAL CHARACTERISTICS
All signals are TTL compatible with a logic one being greater than 2.0 volts but less that 5.25 volts, and a logic zero being
greater than 0.0 volts but less than 0.7 volts.
B-8
PC40-IIT SERVICE MANUAL
AT-BUS INTERFACE SIGNALS
The AT-Bus interface connector is a 40-pin shrouded connector with two rows of 20 male pins on 100 mil centers. The connec-
ting cable is a 40-conductor flat ribbon with a maximum length of 18 inches. Table 1 describes each signal on the AT-Bus
interface. Refer to Table 1 for the AT-Bus interface pinouts and their relationship with the AT system bus.
NOTE: The direction Table 1 is in reference to the drive, i.e., IN means to the drive. PINS are in reference to the 40-pin
AT-Bus connector.
TABLE 1 — AT-Bus Interface Pin Assignments
SIGNAL NAME DIR PIN DESCRIPTION
— HOST RESET IN 1 Reset signal from the host system; active low during system power-up.
GROUND 2 Ground between host system and drive.
HOST DATA I/O 3-18 16-bit bi-directional data bus between the host and the drive.
DO-D15 DO-D15 are used to transfer 8-bit information for register and ECC
READ/WRITE. Data Bit D7 is disabled when the host reads the digital input
register.
These are tri-state lines with 24mA drivers.
GROUND 19 Ground between host system and drive.
KEY 20 Unused pin for keying ribbon cable to the drive.
-—HOST IO CH RDY OUT 21 Enables host wait state generation to lengthen the I/O read and write cycles.
Driven low by the drive immediately upon detecting a valid I/) address select.
GROUND 22 Ground between host system and drive.
— HOST IOW IN 23 Write strobe. Clocks data from the OF — HOST to the drive over data lines
DO-D7 and/or D8-D15 on the rising edge of HOST IOW.
GROUND 24 Ground between host system and drive.
— HOST IOR IN 25 Read strobe. Clocks data from the drive to host data lines DO-D7 and/or
D8-D15 on the rising edge of — HOST IOR.
GROUND 26 Ground between host system and drive.
RESERVED 27 Reserved for future definition.
HOST ALE IN 28 Address Latch Enable from the host. Not currently used, but provided to main-
tain compatibility.
RESERVED 29 Reserved for future definition.
GROUND 30 Ground between host system and drive.
HOST IRQI4 OUT 31 Interrupt signal to the host. Active only when the drive is selected and the
drive interrupt enable bit is high. Goes to a high impedance state when the
drive is not selected or the interrupt enable bit is low. The interrupt is cleared
upon receiving the next command, when the status register is read or when
the drive is reset.
-—HOST I0 CS16 OUT 32 Informs the host that one of the drive registers has been enabled and that the
drive is prepared to perform a 16-bit I/O transer. Open collector output with
24mA driver.
HOST ADDR 1 IN 33 Address line from the host to the drive that is used to select a register on the
drive.
GROUND 34 Ground between host system and drive.
HOST ADDR 0 IN 35 Address line from the host to the drive that is used to select a register on the
drive.
HOST ADDR 2 IN 36 Address line from the host to the drive that is used to select a register on the
drive.
— HOST CSO IN 37 Decoded address select from the host indicating that access to one of the 8
task file registers is desired.
- HOST CSI IN 38 Decoded address select from the host indicating that access to one of the 3
diskette function registers is desired.
— HOST SLAVE OUT 39 Indicates the presence of a second drive. When this signal is low, a second
drive is present. Open collector output with 24mA driver.
GROUND 40 Ground between host system and drive.
PC40-Ill SERVICE MANUAL
AT SYSTEM BUS SIGNALS
The table below presents the signals on the AT system bus that are used by the AT-Bus interface. You should refer to Figure
for the AT-Bus interface pinouts and their relationship with the AT system bus.
NOTE: The direction in Table 2 is in reference to the host system, i.e., IN means to the host system. PINS are in reference to the
40-pin AT system bus connector.
TABLE 2 — AT System Bus Pin Assignments
SIGNAL NAME DIR PIN DESCRIPTION
SA0-SA9 OUT A22-A31 System address bus
SDO0-SD15 1/O A2-A9 & System address bus
C11-C18
AEN OUT All Signal indicating a DMA address is on the system address bus. Active when
high.
-IOW OUT B13 Signals that the enabled I/O device should read the data on the data bus.
Active when low.
—-IOR OUT B14 Signals that the enabled I/O device should gate data onto the system data
bus. Active when low.
BALE OUT B28 Indicates a valid system address is available. Active when changing from
high to low.
IRQI4 IN D7 System interrupt request indicating an I/O device needs attention. Active
when changing low to high.
RESET OUT B2 Used to reset or initialize system hardware at power up. Active when high.
-—I0 CH RDY IN Al0 Pulled low during a bus transaction by an enabled I/O device to lengthen
the read/write cycles. Open collector onto host bus.
AT-Bus Interface Pin Assignments
DISK CONNECTOR AT BUS CONNECTOR
PIN NO SIGNAL NAME DIRECTION PIN NO SIGNAL NAME
1 -HOST RESET “ INV RESET DRV
2 GROUND a GROUND
3 HOST DATA 7 = SD7
4 HOST DATA 8 — SD8
5 HOST DATA 6 =, SD6
6 HOST DATA 9 — SD9
7 HOST DATA 5 — SD5
8 HOST DATA 10 = SD10
9 HOST DATA 4 —_ SD4
10 HOST DATA 11 <> SD11
11 HOST DATA 3 =P SD3
12 HOST DATA 12 a SD12
13 HOST DATA 2 a SD2
14 HOST DATA 13 — SD13
15 HOST DATA 1 — SD1
16 HOST DATA 14 ee SD14
17 HOST DATA 0 < SDO
18 HOST DATA 15 — SD15
B-10
PC40-Ill SERVICE MANUAL
AT-Bus Interface Pin Assignments (continued)
DISK CONNECTOR
SIGNAL NAME
-HOST IO CH RDY
GROUND
-HOST IOW
GROUND
-HOST IOR
GROUND
RESERVED
HOST ALE
RESERVED
GROUND
HOST IRQI4
-HOST IOCS16
HOST ADDR 1
GROUND
HOST ADDRO
HOST ADDR2
-HOST CSO
-HOST CS1
-HOST SLV
GROUND
DIRECTION
AT BUS CONNECTOR
PIN NO
NOTES: All grounds are connected together on the ground plane of the adapter board.
-HOST CSO, -HOST CS1 and -HOST SLV are generated on the adapter board; there are no directly related AT-Bus
signals.
CABLE CONNECTOR
DESCRIPTION
DC POWER PLUG
DC POWER PIN
I/O CONNECTOR
Recommended [1]
Connectors
DISK DRIVE [2]
CONNECTOR
AMP 1-4807222-0
AMP 350079-4
BURNDY FRHL40R-2
[1] THESE NUMBERS ARE FOR SIZE REFERENCE ONLY
[2] PROVIDED BY DRIVE VENDOR
[3] PROVIDED BY COMMODORE
HOST (CPU) [3]
CONNECTOR
AMP 1-480424-0
AMP 350078-4
SIGNAL NAME
GROUND
NO CONNECTION
-IO CH RDY
GROUND
-IOW
GROUND
-IOR
GROUND
NO CONNECTION
BALE
NO CONNECTION
GROUND
IRQ14
-IOCS16
SAI
GROUND
SAO
SA2
GROUND
BURNDY FRS40BD-8P
B-11
PC40-III SERVICE MANUAL
I/O INTERFACE CIRCUIT
NOTE: Wiring shall be ribbon cable or twisted pair.
DIMENSIONS ARE IN INCHES
FIRST
POSITION
INDICATOR
GROUND CIRCUIT
NOTE: Wiring shall be ribbon cable or twisted pair.
DC GROUND SIGNAL GROUND
0.01pF
AC GROUND FRAME GROUND
GROUND CABLE ASSY. — 380811-01
CBM PART NUMBER DESCRIPTION VENDOR
ae
fos] 3045402 —+| ‘TERMINAL 46X03 DIN«&a7 | __WEITKOWIT2 113
[os | _903451-10 | TERMINAL RING TONGUE 643 DIN463 | ____ MOLEX AA
[os | 905451-01 | TERMINAL RING TONGUE 63.2 DIN4624 [SS
Toe | 903753-10 | LEAD WIREAWG 18 BLACKL = 60MM [SS
Foo | _s0se7s-05 | —*TUBEHEATSHRINK. [| SSCS
PC40-III SERVICE MANUAL
PC40-III FLOPPY DISK DRIVE — 380825-01 (Dark Bezel); 380825-02 (Light Bezel)
SCOPE
This specification describes 5-14 ” double-sided 96-TPI minifloppy disk drive (hereafter abbreviated as FDD) CHINON FZ-506.
FEATURES
The features of the FZ-506 are as follows:
(1) Large Capacity Up-to 1.6M bytes
The FZ-506 is a double-sided, high-density, double-track type and its capacity is 1.6M bytes, in unformatted mode. The
read/write selection of the high density 1.6M bytes, 96 TPI and double density 1M bytes, 96 TPI disk can be carried out
by changing either the motor speed (360 rpm/300 rpm) or transfer rate (500K BPS/300K BPS). In addition, as the data
retrieval from 250K bytes, 48 TPI disk to 500K bytes, 96 TPI disk is possible, the former software packages can be read.
(2) Pop-up Mechanism
With the newly employed pop-up mechanism, the disk can be loaded/unloaded with ease, preventing mischucking at disk
insertion.
(3) Low Power Consumption
As a newly designed LSI (C-MOS chip) is employed in the read/write and control circuits, high performance and low power
consumption are achieved. In stand-by mode, power consumption is only 1.59W, and in operation mode 3.81W, making
system design easy.
(4) Built-in Disk-in sensor
With the built-in disk-in-sensor, when no disk is loaded, the motor is stopped. This extends the motor service life and
reduces power consumption. When chucking the disk, the DD motor is rotated temporarily to assure the centering of the
disk. DISK CHANGE signal will be output by the sensor, also.
(5) Various Disk Readings
With the FZ-506, the various disk readings shown below are possible, existing software written in 48 TPI format can be
used without any conversion.
Disk Used Normal Density Be
Track Density 48 TF 96 TP
Storage
Rate of Data 250K/300K | 250K/300K | 250K/300K | 250K/300K 500K BPS
Transfer BPS BPS BPS BPS
Rotational 300/360 300/360 300/360 300/360
Speed rpm rpm rpm rpm
Tomred | o | o | o | o
* Data can be read by this drive, but data can not be read by a head made solely for 48 TPI use.
B-13
PC40-IlI SERVICE MANUAL
SPECIFICATIONS
Specification (1)
HIGH DENSITY
ee
833 KB 1666 KB 500 KB 1000 KB
4935 BPI 9870 BPI 2961 BPI 5922 BPI
125K/150K 250K/300K
0.5 sec or less
Recording mode
Per disk
Unformatted
Per track
Per disk
Per track
Formatted Number
of sectors
Storage capacity
Per sector
Recording density
Rate of data transfer
Power-on to ready time
Single track seek time
Average access time 94 msec
Access time
Settling time
100 msec/83.3 msec
300/360 rpm
Average latency time 83.3 msec
Rotation speed
Number of tracks
Number of cylinders
Track density 96 TPI
Number of heads
Number of index
57.150 mm
Outer Side 0
track
Side O 36.248 mm
Inner
track
Radius of track
B-14
PC40-III SERVICE MANUAL
Specification (2)
Physical dimensions 146 (W) x 41 (H) x 193 (D) mm
DC+12V +5%
Power supply
DC +5 V +5%
290 mA TYP. 14 mA TYP. 1.62 W TYP.
330 mA TYP. 200 mA TYP 4.05 W TYP.
Power consumption i 330 mA TYP. 210 mA TYP. 4.17 W TYP.
260 mA TYP. 440 mA TYP. 6.58 W TYP.
Spindle Motor
Starting current 900 mA MAX.
(0.5 sec. max.)
DC+12V Less than 150 mVp-p (including spike noise)
Ripple voltage allowance
DC +5 V Less than 100 mVp-p (including spike noise)
INoise = Less than 55 phons (class A) (separated from the drive by 1m)
Material: ABS Color: Beige
Cabinet specifications
Material: ABS Color: Beige
B-15
PC40-IIT SERVICE MANUAL
Installation Conditions
Specification
Mounting position
Horizontal Vertical
In horizontal position, the front panel can be raised a maximum of 15°.
During storage
Environment conditions During operation
Humidity During non-operation
Fi ae Amplitude Less than 0.5 mm 5 ~ 25 Hz
Continuous vibration 0.25G
During operation .25G 25 ~ 100 Hz
Single vibration Less than 10G (10 ms)
During non-operation| Continuous vibration Amplitude Less then pau ~ 9Hz
and storage .5G 9 ~ 100 Hz
(W/Protect sheet) Single vibration Less than 30G (10 ms)
Fall height in packing State: 70 cm
(corner: one time, sides: three times, flat surfaces: six times)
Vibration
Drop shock
B-16
PC40-III SERVICE MANUAL
Reliability
MTBF 10,000 POH
MTR ae
Software errors
Error rate Hardware errors
Number of mountings of the media
Life
10,000 H or more
Number of identical track passes 3,000,000 passes or more
10,000 times or more
=
@
o
a.
Number of mountings
* Maintenance is not required under normal use conditions.
*1 Reference value
B-17
PC40-IIT SERVICE MANUAL
DIMENSIONS
a :
Ign let LL
193 +1
ee OS]
474+0.5| 79.2405
B-18
PC40-III SERVICE MANUAL
INTERFACE SIGNALS
The interface signal has 12 input signal lines and 5 output signal lines.
Signal Voltage Levels
The interface signal interfaces with the controller at the TTL level. For all signals, low is true. The I/O signal level into the
drives have the following specifications.
(1) Input level OV to +0.40V
High level +2.40V to +5.25V
Input impedance 1500
(2) Output signal
Low level OV to +0.40V
High level +5.25V max. (by receiving the end terminator)
Output current (for low level) 48 mA (max.)
Output current (for high level) 250 »A (max.)
Input Signals
(1) DRIVE SELECT 0 to 3 signal lines
When one of these signal lines goes into low level, the drive corresponding to the signal line is selected and the I/O gate
is opened. Up to four drives can be controlled using these four signal lines. The drive corresponding to one of the DRIVE
SELECT 0 to 3 signal lines is determined by the position of the short plug in the drive.
(2) MOTOR ON signal line
This line controls the ON/OFF of the spindle motor. When this signal line is set to low level, the spindle motor revolves.
When it is set to high level, it stops. 0.5 seconds is the required start up time of the spindle motor. The motor start
operation is not executed when no disk is loaded.
This signal operates independently of the DRIVE SELECT signals.
(3) DIRECTION SELECT signal line
This signal determines the direction of movement of the head when a pulse is sent via the STEP signal line. When this
signal line is set to low level and the STEP signal pulse is sent, the head moves towards the center of the disk. When
it is set to high level and the STEP signal pulse is sent, the head moves away from the center.
The logic level of this signal should be held for at least 1 microsecond after the trailing edge of the STEP pulse.
(4) STEP signal line
This signal line moves the head. With the rise of a single low level pulse, this signal line changes from LOW level to
HIGH level and the head moves one track in the direction determined by the DIRECTION SELECT signal.
However, this signal is not accepted when the FDD is in WRITE mode. The head is stabilized 20 ms after the trailing
edge of the last STEP pulse, and the FDD is ready for data read/write operation.
(5) WRITE GATE signal line
This signal line specifies drive write and read status. When this signal line is set to:low level, write enable status occurs
and the data is stored on the disk surface by the WRITE DATA signal. When this signal line is set to high level, read
status occurs.
After the writing operation, a period of 1.2 ms is necessary before a valid READ DATA signal appears on the interface.
(6) WRITE DATA signal line
Data written on the disk surface is transferred on the signal line. With the decline of the pulse sent to this signal line
(when the signal line changes from the high level to the low level), data is written on the disk surface.
(7) SIDE SELECT signal line
This signal line selects the head.
When this signal line is set to high level, the side 0 head is selected; when it is set to low level, the side 1 head is selected.
Side 0 stands for the one-sided medium recording surface.
The selection is completed 100 microseconds after the change of the SIDE SELECT signal line, and read/write becomes
possible.
(8) MODE SELECT signal line
This signal status selects either 1.6M Byte mode or 1M Byte mode.
The line can be configured in positive or negative logic by position of short plug.
B-19
PC40-III SERVICE MANUAL
Output Signals
(1) INDEX signal line
Whenever the disk rotates once, this signal line outputs a low level pulse indicating the start of the track. A decline of
the pulse signal (when this signal line changes from high level to low level) indicates the start of the track. However,
the pulse is only output when the disk is inserted.
(2) TRACK 00 signal line
When this signal line is set to low level, the head is located at the track 00 position and the specific phase of the stepping
motor is excited.
(3) WRITE PROTECT signal line
When this signal line is set to low level, the inserted disk cannot be written on. This signal line may also be set to low
level even when no disk is inserted in the drive. The write function of the drive becomes inoperative when write-inhibited
disk is inserted.
(4) READ DATA signal line
This signal line is used for the transfer of the pulse series read from the disk, in which clock pulses and data pulses are
mixed. The negative-going edge (the moment of change from high level to low level) of the pulse output at this signal
line indicates the readout data (clock and data pulses).
(5) READY signal line
When this output signal line is set to low level, the disk is inserted and the number of disk rotations is fixed.
When the READY signal is ON, read and write operations can be performed on the disk. Immediately after the MOTOR
ON signal is turned ON, power is supplied. After the disk is inserted, check that the READY signal is ON before perfor-
ming write and read operations.
(6) DISK CHANGE signal
This signal line is set to low level by power on or when a disk is ejected, and set to high level by STEP signal input
when a disk is loaded.
POWER ON —/
DISK IN ——— af
DISK CHANGE ee eee
STEP — pp. @- &»-
B-20
PC40-III SERVICE MANUAL
Input Signal Line Terminator
The FZ-506 is operable with either daisy chain or star chain systems. It is possible to use 4 pcs. Drives by daisy chain. When
more than one drives are connected, termination resistors of all drives except the drive at the end of interface cable must be
disconnected. (The termination resistors can be disconnected by taking away the short-plug at the connector J1-1) Each of
the input signal lines has a 1500 terminal resistor.
Interface Circuit
(1) Drives-receivers
When recommend the following drivers-receivers.
+5V
CONTROLLER SIDE ORIVE SIDE r— 44
O |
150n L--4d
Ji-!
BS: She eee ee ;
7438 CMOS
or equivalent ! ' CONTROL
LOGIC
+5V
1500
' 1
74LS14 7438
or equivalent or equivalent
(2) Wire material
Flat cables or twisted pair wires
B-21
PC40-III SERVICE MANUAL
CONTROLLER SIDE DRIVE SIDE
MODE SELECT 2
IN USE/HEAD LOAD 4
ORIVE SELECT 3 8 INDEX
6
ORIVE SELECT 0 10
ORIVE SELECT 1 12
ORIVE SELECT 2 14
MOTOR ON 16
OIRECTION SELECT 18
STEP 20
WRITE OATA 22
WRITE GATE 24
26 TRACK OO
28 WRITE PROTECT
30 READ DATA
SIDE SELECT 32
34 READY * (DISK CHANGE)
* possible to change with J1
+12V OC @
DC GROUND SIGNAL GROUND
+12V RETURN ®
100KN 0.01 pF
+ SV RETURN ®
+ SV 0C @
AC GROUND FRAME GROUND
B-22
PC40-IIT SERVICE MANUAL
POWER-ON SEQUENCE
Recalibration of the head position is performed during the power-sequence of the FDD. The figure below shows the power-on
sequence.
Reset all
circuit
600ms oe inca Executed regardless of
max deat Dd eras the DRIVE SELECT signal.
step in
No
Seek to
zero track
Set to the
standby mode
POWER-ON SEQUENCE
POWER SUPPLY INTERFACE
Power Supply Specifications
The DC power (+12V, +5V) shown in Specification is required by the power supply. There are four power lines (+ 12V,
+5V, and the two return lines).
Frame Ground
The frame ground and signal ground are connected through a capacitor and a resistor. The values are as follows:
R = 100 k9 C = 0.01pF
Connect the frame ground where the AC ground and DC ground are one point connected in the host system.
Power Supply Sequence
(1) The power ON sequence is not specified. However, the time in which the supplied power voltage rises up to 90% of
the specified value, should be set to 100 ms or less.
(2) If the drive is in a status other than write operation, and the DC power is disconnected, the disk and the data stored
on the disk are not destroyed. However, its contents will be destroyed if the WRITE GATE is not set to high level.
B-23
PC40-IIT SERVICE MANUAL
INTERFACE CONNECTOR AND PIN ASSIGNMENT
Interface Connector
(1) DC power connector
[ve sitet Side
Connector/housing AMP 172349-1 AMP 1-480424-0
or equivalent or equivalent
or equivalent
(2) Interface signal connector
Connector Card Edge
Connector
Pin Assignment
The assignment of each pin is shown. This diagram shows the back of the drive.
PJ1 (I/O Connector) PJ2 (Power Connector)
PIN ASSIGNMENT
MIN 1.2740.
7.81 Ri 0.9+0.1
v fo)
Be
°
+l
S
2,544 0.08
2.35 40.64+ 0.1
Thickness 1.640. 2
CARD EDGE CONNECTOR
B-24
PC40-IIT SERVICE MANUAL
(1) DC Power connector
[1 [iv ve
| 2 | + 12V RETURN
| 3 | + SV RETURN
4 +5V DC
(2) Interface signal connector
[2 [MODE SELECT
[si_4 [IN USE/HEAD LOAD
[6 | DRIVE SELECT 3
Ts [Npex
[10 | DRIVE SELECTO__
[14 [DRIVE SELECT?
[1s [motor on |
[18 | DIRECTION SELECT __|
[0 [srr
[2 [WRITE DATA
[24 [write Gate
[26 [rRAcK 00
[28 [WRITE PROTECT
[30 [READ DATA
[2 [SIDE SELECT
[=2_34__[ READY/DISK CHANGE _
GND: SIGNAL GROUND
*1; “HEAD LOAD”’ is optional.
*2: As for switching over between READY and DISK CHANGE,
see paragraph 9; SHORT PLUG.
B-25
PC40-III SERVICE MANUAL
SHORT PLUG AND FRONT LED
Short Plug
The assignment of each pin is shown.
FRONT SIDE CONTROL PCB
This diagram shows the side of the drive. SHORT ELUG
CHINON FZ-506 high density 1.6 MB to 1 MB switchable floppy disk drive can be configured in several modes of operation
using ‘‘SSHORT-PLUGS”’ according to the table below.
Connector ‘‘J1”’
1.6 MB to 1 MB variable speed switchable using
Pin #2 as change-over signal input
Pin #2: High =1.6 MB (360 rpm)/Low = 1 MB (300 rpm)
*1 Pin #2: High = 1 MB (300 rpm)/Low = 1.6 MB (360 rpm)
1.6 MB to | MB switchable at 360 rpm, IBM PC/AT compati-
ble, Pin #2 as change-over input
Pin #2: High = 1.6 MB (360 rpm)/Low = 1 MB (360 rpm) *2
1.6 MB 360 rpm non-switchable
(Disregards pin #2 signal
*1. The short-plug is factory set at this position. 12: READY
*2. PC40-III Close 1, 3, 6, 10, 13 13: DISK CHANGE
‘‘o”? = Position closed
‘s_? = Position open
Note: Position 1 through 5 of the ‘‘J1’’ are designated as follows.
POS. 1: Connect the termination resistors when closed
POS. 2: Configure the drive as ‘‘DRIVE 0” when closed
POS. 3: Configure the drive as ‘‘DRIVE 1” when closed
POS. 4: Configure the drive as ‘“DRIVE 2”? when closed
POS. 5: Configure the drive as ‘‘DRIVE 3”? when closed
Note: Only one of the positions 2 through 5 of ‘‘J1’’ can be closed. Above example demonstrates in the case of
‘(DRIVE 0”’ and the termination resistors connected.
PIN #2: Card-Edge Connector (PJ1)-2
Front LED
The front LED lights when the DRIVE SELECT signal selected by the short plug is set to low level.
B-26
PC40-IIT SERVICE MANUAL
Handling of Connectors
(1) Types of connectors
1. PJl : Interface connector (34-pin, card-edge type)
2. PJ2 : Power connector
3. PJ3 : Stepping motor connector
4. PJ4, 5 : Head connectors
5. PJ6 : DD motor connector and track 00 sensor connector
6. PJ7 : Disk-in sensor connector
7. PJ8 : Frond LED connector and index, write protect sensor connector
8. Jl : Short pin connector (13-pair) for drive selection
(2) Removal of connector wire
Be sure that power switch is turned off whenever inserting or removing the connector wire, etc. Pull out the connec-
tor wire can be removed from the connector on the PC board.
(3) Insertion of connector wire
Each connector wire should be set in a proper position as shown in Fig.
Also, as each wire has a stripe on one side make sure to insert so that the striped side is the same side as the pin no.
1 of the connector.
(4) Insertion of head FPC
Side 0 and side 1 of the head FPC are shown in Fig. Make sure to properly insert side 0 FPC into connector PJ4 of
control PCB and side 1 FPC into connector PJ5.
W/P SENSOR
SS
—
INDEX SENSOR
==
0D MOTOR ===
=
TRACK 00 SENSOR —~_=
B-27
PC40-IIT SERVICE MANUAL
Functions of Test Points
The following eight test points (with GND) are provided on the control board, each of which is used in observing the waveform
for FDD adjustment or check.
(1) TP1, TP2 (pre-amp output) and TPC (analog GND)
These are the test points of the read amp output.
Amplified about 200 times by pre-amp, the signal from the head can be observed at TP1 and TP2 through LPF.
TP1 and TP2 are 180° phase off (inverted phase).
For accurate waveform observation, it is necessary to add the signals of both channels together (the signal of the one
channel is inverted in phase) to observe these signals as one waveform using an oscilloscope with two channels. TP3
is used in grounding the oscilloscope.
TP1 and TP2 are used in checking the read/write head for its different characteristics or in checking and adjusting
the tracking alignment, and the index burst timing.
(2) TP4 (read data signal)
This is the test point of the read data pulse. The READ DATA signal appears here.
In FM mode, a data signal with 2F or 1F period is observed, while MFM mode, a data signal with 2F, 1.5F or 1F
period is observed. (See Table)
Chis test point is used in check of asymmetry.
Frequency
(3) TPS (index sensor)
This is the test point of the index sensor photo-transistor output. A waveform with soft leading and trailing edges
appears here, since the sensor output signal is taken out before flowing across the Schmitt inverter. Here it is
necessary to check that the output voltage of the index sensor is normal (with no waveform split).
(4) TP6 (write protect sensor)
This is the test point of the write protect sensor photo-sensor photo-transistor output. The WRITE PROTECT out-
put signal appears here. With a disk in which a measure for write protection is taken (its notches are masked), it
becomes low level.
The voltage at this test point should be more than 3 V in the write enable state (the notches are open) and less than
0.5 V in the write protect state.
This test point is used in check of the write protect sensor.
(5) TP7 (Disk-in sensor)
This is the test point of the disk-in sensor photo-transistor output.
This signal becomes low level when a disk is inserted into the FDD.
(6) TP8 (track 00 sensor)
This is the test point of the tract 00 sensor photo-transistor output. The voltage at this test point should be within
the range shown in the Figure on the following page.
B-28
PC40-III SERVICE MANUAL
Morethan 30V
Less than0.5V
Track position OO 01 02 03 04
Adjust so that the level of the sensor output changes between track 01 (Low level) and track 03 (High level)
TEST POINTS AND CONNECTORS ON THE CONTROL PC BOARD ASSY.
NOTE: When the various signals are extracted, proper test pin should be mounted at the test point since the test point is
not equipped with the test pin.
Sufficient caution should be taken for the mounting of test pin and wiring of signal lines because it may cause
damage if test pin and other places are short circuited.
INSTALLING THE OPTIONAL COMMODORE 910 and 920 FLOPPY DRIVES
In addition to following the general installation instructions given in the manuals for the Commodore 910 and 920 floppy
drives the user must also perform the specific procedures for PC40-III installation described below.
Commodore 910 Floppy Drive
To install the Commodore 910 3.5 inch 720Kb drive as Drive B: in the PC40-III, the user must do the following:
© Set the drive select jumper to position I.
© The M jumper should be in position 5.
© The R-D jumper should be in position 6.
The first time you power up, use the Setup utility to identify your second drive (Diskette 2 on the menu) as a 720Kb 3.5
drive.
Commodore 920 Floppy Drive
To install the Commodore 920 5.25 inch 360Kb floppy drive as Drive B: in the PC40-III, the user must do the following:
e Set the drive select jumper to position 1. ,
© Cut JP6 (located on the bottom side of JP1) in half.
e The first time you power up, use the Setup utility to identify your second drive as a 360Kb 5.25 drive.
B-29
PC40-III SERVICE MANUAL
Stepping motor connector
Head arm Track 00 sensor
Index sensor mounting screw
Index sensor ass‘y
Stepping motor pulley
Write protect sensor ass'y
Write protect sensor a
mounting screw CS >
BS, |
Disk-in sensor ass'y
Front lever
Stepping motor
Stepping motor mounting screw Wire holder mounting screw
DD motor Track 00 sensor ass‘y
B-30
PC40-Ill SERVICE MANUAL
Location of Electrical Parts
TP4 READ DATA
©
nto a '<*
REN OTA
ep] Sas
10 Pu 20 30 34 (C36)
B-31
PC40-III SERVICE MANUAL
SCHEMATIC DIAGRAM FOR CHINON FZ-506
MODE SELECT O-2
MOTOR ON
DIRECTION d 102: TC8604F
STEP
SIDE SELECT
WRITE GATE
WRITE DATA
PC40-Ill SERVICE MANUAL
APPENDIX C
KEYBOARD SECTION
INFORMATION IN THIS SECTION IS FOR REFERENCE ONLY.
COMMODORE WILL NOT SUPPLY COMPONENT PARTS FOR
OEM ASSEMBLIES.
PC40-IlI SERVICE MANUAL
PC40-III KEYBOARD — OPERATIONS
THE COMMODORE PC40-III KEYBOARD
The Commodore PC40-III keyboard is divided into four sections:
— the Typewriter Area
— the Special Key/Cursor Key area
— the Numeric Keypad
— the Function Keys
In using the Commodore PC40-III keyboard, note that:
— All the keys (except for the special keys) repeat as long as they are held down.
— You cannot interchange either the numeral zero (0) and the upper case letter O, or the numeral I and the lower case letter I.
— Keys may be program controlled. This means that their use is defined by the operating system, programming language
or application software currently being used. The description of the specific function of these keys can be found in the
MS-DOS User’s Guide/User’s Reference manual, or in the manual for the particular software being used.
In this appendix, whenever combinations of keys are to be pressed, the names of the keys to be pressed are separated by a
hyphen. For example, Ctrl-Alt-Del means hold the Ctrl and Alt keys down and then press the Del key at the same time. See
Appendix C for a list of special key sequences used in MS-DOS.
The following pages describe each area of the keyboard, including definitions of the individual keys in each area. To make
full use of your PC40-III computer, you should become familiar with the names, locations and functions of all the keys.
FUNCTION SPECIAL KEY ACTIVE
KEYS KEYS LIGHTS
TYPEWRITER CURSOR NUMERIC
KEYS KEYS KEYPAD
FIGURE D-1. _THE COMMODORE PC40-III KEYBOARD
THE COMMODORE PC40-II KEYBOARD
PC40-Ill SERVICE MANUAL
THE NUMERIC KEYPAD
The Numeric Keypad is at the far right of the Commodore PC40-III keyboard. The keys in this section of the keyboard usually
function as number and mathematical keys as long as the Num Lock light is on. With the Num Lock light off, you can use
certain keys to control the position of the cursor on the screen and perform some special functions. Note that many of the
functions of keys in the Special Key/Cursor Key area are available in the Numeric Keypad.
The NUM LOCK Key
When the computer is turned on, the Num Lock indicator light located above the Numeric Keypad goes on and the numeric
keys 0 through 9 are locked into the numeric functions. To turn off Num Lock, press the Num Lock key and this light goes out.
The non-numeric functions on the Numeric Keypad keys (such as scrolling the cursor by using the 2, 4, 6 and 8 keys) can
be obtained while Num Lock is on by holding down the Shift key and pressing the required key.
Controlling the Cursor from the Numeric Keypad
You can control cursor movement from the Numeric Keypad by using the 2, 4, 6 and 8 keys, as follows:
— the 8 key moves the cursor up
— the 2 key moves the cursor down
— the 6 key moves the cursor to the right
— the 4 key moves the cursor to the left
The cursor moves one line or one character position for each time a key is pressed. The cursor will move continuously as
long as you are holding down a key.
The HOME key
This key (the 7 key) moves the cursor to the top left corner of the screen, which is known as the Home position.
The END key
This key (the 1 key) places the cursor one character position to the right of the last character on the line.
The PG UP key
The Pg Up (for ‘‘Page Up’’) key (the 9 key) is a program controlled key that moves the cursor to the previous page (a full
page is 25 lines).
The PG DN key
The Pg Dn (for ‘‘Page Down’’) key (the 3 key) is a program controlled key that moves the cursor to the next page.
The INS key
Pressing the Ins (for ‘‘Insert’’) key (the 0 key) turns the Insert function on. Any characters typed while the Insert function
is on are inserted at the cursor position. To turn the Insert function off, press the Ins key again. Any characters typed when
Insert is off appear at the cursor position, overwriting (i.e., deleting) any character already at the cursor position.
The DEL key
Pressing the Del (for ‘‘Delete’’) key (the decimal point key) deletes the character at the cursor position. The cursor remains
at that position and all the characters to the right of it move one position to the left.
The +, —, * and / keys
These keys are used for mathematical functions: + for addition, — for subtraction, * for multiplication and / for division.
Pressing any one of these keys causes the selected sign to be displayed.
The ENTER key
You can press the Enter key on the Numeric Keypad to transmit a command or information to the computer. In other words,
pressing this key has the same effect as pressing the Enter key on the main keyboard. This can be a program controlled key.
C-2
PC40-III SERVICE MANUAL
THE FUNCTION KEYS
The Function Keys are the keys located in the horizontal row of keys above the Typing Area, and marked F1 through F12.
These keys are program controlled keys — that is, their use is controlled by whatever software you are currently using.
The DELETE key
Pressing the Delete key deletes the character at the cursor position. The cursor remains at the position and all the characters
to the right of it move one position to the left.
The HOME key
This key moves the cursor to the top left corner of the screen, which is known as the Home position.
The END key
This key places the cursor one character position to the right of the last character on the line.
The PAGE UP key
The Page Up key is a program controlled key that moves the cursor to the previous page (a full page is usually 25 lines) in
the program.
The PAGE DOWN key
The Page Down key is a program controlled key that moves the cursor to the next page in the program.
Controlling the Cursor from the Cursor Keypad
Cursor movement is program controlled — that is, cursor movement is defined and enabled by the operating system or ap-
plication software currently being used. Note that in MS-DOS only the left and right cursor keys are active.
There are four cursor keys located in the Cursor Keypad located at the bottom of the keyboard, between the Typewriter Area
and the Numeric Keypad. You can also move the cursor by using the 2, 4, 6, and 8 keys in the Numeric Keypad (see below).
The cursor is controlled from the Cursor Keypad as follows:
— the up arrow key moves the cursor up
— the down arrow key moves the cursor down
— the right arrow key moves the cursor to the right
— the left arrow key moves the cursor to the left
The cursor moves one line or one character position for each time a key is pressed. The cursor will move continuously as
long as you are holding down a key.
THE SPECIAL KEY/CURSOR KEY AREA
This area contains 13 keys, including a four key cursor keypad at the bottom and some special keys. Certain keys have dual
functions (e.g., Pause/Break).
The PRINT SCREEN/SYSTEM REQUEST key
This is a dual function key. The Print Screen (PrtSc) function is used to give a printed copy of the information displayed
on the screen. Alpha/numeric characters displayed on the screen, such as program listings, can be printed on any type of
printer (daisy wheel, dotmatrix, laser, thermal, ink jet, etc.) printers. Graphics information cannot be reproduced on a daisy
wheel printer and, depending on the software being run, may require a specific printer driver to be rendered fully. . .
The System Request (SysRq) function is program controlled.
The SCROLL LOCK Key
This is a program controlled key. It is used typically to halt the scrolling of information on the screen. Usually, to resume
scrolling, you press the key again.
The PAUSE/BREAK key
This is a dual function key. The Pause function is used typically to halt program execution temporarily.
The Break function is program controlled. It is activated by pressing Shift and Pause together. Under MS-DOS, Ctrl-Break
has the same function as Ctrl-C: that is, it aborts the command currently being executed. In GW-BASIC, the Break key is
used with the Ctrl key (i.e., in a Ctrl-Break sequence) to stop a program when it is running.
The INSERT key
Pressing the Insert key turns the Insert function on. Any characters typed while the Insert function is on are inserted at the
cursor position, without overwriting (i.e., deleting) any character already at the cursor position. To turn the Insert function
off, press the Ins key again. Any character typed when Insert is off appears at the cursor position and overwrites any character
already at the cursor position.
C-3
PC40-III SERVICE MANUAL
The ALT key
There are two Alt (for ‘‘Alternate”’) keys, located at either end of the Space Bar in the bottom row of typing keys.
The Alt key has a number of uses:
© Pressing the Alt key simultaneously with the Ctrl and Del keys restarts (or ‘‘reboots’?) MS-DOS.
© Within the GW-BASIC Interpreter, holding down the Alt key and pressing a single alphabetic key A through Z allows you
to enter a GW-BASIC keyword automatically. This is fully described in the GW-BASIC Manual.
© Special characters can be entered using the Alt key and the number keys on the numeric keypad to the right of the main
keyboard. Hold down the Alt key, type the three digit ASCII code for the required character and then release the Alt key.
The character is then displayed. A list of ASCII character codes is shown in Appendix C of the GW-BASIC User’s Guide.
The CTRL key
There are two Ctrl (for ‘‘Control’’) keys, located at either end of the bottom row of typing keys. The Ctrl key is a program
controlled key. It is also used in conjunction with other keys to perform various control functions for MS-DOS.
The ESC key
The Esc (for ‘‘Escape’’) key, located at the far left of the top row of the keyboard, is a program controlled key.
The TAB key
This is the key with small horizontal arrows pointing left and right. The Tab key is located at the far left of the second from
the top row of the typing keys. This key is used to set and remove tabs.
The Space Bar
This is the large key extending most of the way across the bottom of the main keyboard. This key is similar in location and
function to the space bar on a typewriter. The Space Bar moves the cursor to the right, inserting spaces as it moves. If there
are any characters in the path of the cursor movement, they are erased.
THE TYPEWRITER AREA
The Typewriter Area contains a standard (QWERTY) typing keyboard and some additional keys.
The SHIFT keys
There are two Shift keys in the Typewriter Area. They are oversized keys with an upward pointing arrow, and are located at each
end of the row above the Space Bar. Holding down either Shift key and pressing any of the alphabetic keys causes the letter shown
on that key to be displayed in upper case. In addition, the Shift keys are often used with other keys to perform special functions.
If the Caps Lock or Num Lock light is on, pressing the SHIFT key cancels the effect. For example, if Caps Lock is on and
you hold down the SHIFT key and press the A key, then the lower case letter (i.e., a) is displayed.
The CAPS LOCK key
Pressing the Caps Lock key at the left side of the middle row of typing keys locks the characters A through Z into the upper
case position. When you first press the Caps Lock key, an indicator light located above the Numeric Keypad goes on. To
release the Caps Lock key, you press the key again and this light goes out.
Lower case characters can be obtained while the Caps Lock light is on by holding down the SHIFT key and pressing the required
letter key.
The BACKSPACE key
This is an oversized key located on the far right side of the top row of the main keyboard, and having a small horizontal
arrow pointing left. Pressing the Back space key causes the character to the LEFT of the cursor to be erased, while the cursor
and any characters to the RIGHT of the cursor move one position to the left.
The ENTER key
There are two Enter keys: one on the main keyboard, and one in the Numeric Keypad. The Enter key on the main keyboard
is located at the right side of the middle row. On the top of this key is a right-angled arrow that points left. You must press
the Enter key to transmit a command or information to the computer. The Enter key (which can be program controlled) may
be referred to as a Return key or as a CR (Carriage Return) key in some program documentation.
C-4
PC40-III SERVICE MANUAL
PC40-IlI KEYBOARD — HARDWARE
Commodore P/N [| Comtny
312702-01 United Kingdom
312709-02 United States
312702-03 German
312702-04 Italian
312702-05 French
312702-06 Spain
312702-07 Dutch
312702-08 Denmark
312702-09 Norway
312702-10 Sweden/Finland
Key Scan Codes
All keys have two different 8 bits codes, a ‘‘Make”’ -code and a ‘“‘Break”’ -code. (except {-marked keys)
These codes only differ in the MSB (bit 7). ;
Make-code ;: MSB=0
Break-code : MSB=1
A ‘‘Make’’-code is transmitted once a key is depressed.
A ‘‘Break’’-code is transmitted for any released key.
t-marked keys have custom output codes.
See code table-4.
Clock and Data Signals
(1) Data — The transmitted serial data that consists of 1 start bit followed by 8 bits scan code.
Data is transmitted LSB first.
(2) Clock — The synchronizing signal that gives timing to nine bits of transmitted data.
16 Characters FIFO Buffer
The keyboard has a 16 characters FIFO buffer for serial data transmission.
When a key is on or off, the corresponding code is once stored into FIFO buffer in accordance with the regular sequence of
switch-on or switch-off keys and then transmitted in the sequence. However, the keys after 16th keys are ignored on account
of buffer full.
Auto repeat function
The keyboard has auto-repeat feature on all keys.
When a key is depressed, the corresponding ‘‘Make’’-code is transmitted with clock. If the key is held down for more than
500 ms with any other keys off, the keyboard keeps on sending the code with clock at the rate of 10.89 characters per second
until the data key is off or another new key is on.
In case of the plural key on, only the last on-key data code is transmitted like that.
Handshake feature
The keyboard senses the clock line at intervals of approx. 10 ms during key scanning. On sensing the clock line low, resenses
the line low or not for approx. 3.5 ms.
Confirming the line low, stops key-scanning and transmitting the data. After that the keyboard waits until the clock line high.
The line high, sends status data ‘‘Hex AA’’. Then the keyboard clears FIFO buffer and all LEDs get dark.
Caps Lock, Num Lock and Scroll Lock indication
Depressing the ‘‘Caps-Lock’’, ‘‘Num-Lock’’, and ‘‘Scroll-Lock’’ keys turn on each of their LED’s indication.
The color of these LED’s is green.
This state is latched until the key is depressed for the second time. Pressing the ‘‘Caps-Lock’’, ‘‘Num-Lock”’ and ‘‘Scroll-
Lock”’ keys, in conjunction with the ‘‘Ctrl’’ key is not toggle each of their LED’s status. If the clock line is tied low for more
than 3.5 ms, these LEDs are turned off after the clock line high.
C-5
PC40-III SERVICE MANUAL
Data format
CLOCK
bit Transfer speed rate is approx. 9600 baud.
Parameter
12 Vde with 200 micro-second pulse width 1/50 duty cycle 1 mA maximum rating.
5 millisecond initial, 10 millisecond over lifetime.
Keyswitch Contact
Resistance
1,000 ohms - maximum
Keyswitch Capacitance 500 pF - maximum
q
i
|
l
Withstanding Voltage 250 Vac @ one (1) minute
(Dielectric)
i
[
i
t
i
Voltage - Vcc +5 Vdc, +0.25 Vdc
“1”? = 2.4 Vdc - minimum; ‘‘0’’ = 0.4 Vdc - maximum
N-Key rollover shall be provided on all keyswitches.
Keyboard circuitry shall allow for internal power on reset.
Current
Output Logic
Rollover
MECHANICAL PARAMETER
[__Keyawitches |
Operating Force 51 grams (Typical)
:
!
| Zero Travel Force || 15 +10 grams at Q.Smm Travel
f
!
i
Full Travel Force 90 +25 grams at 0.5mm Above Full Travel
Key Travel 4.3 +0.5mm; 4.0 +0.5mm
Key Wobble 0.7mm, Maximum: (+) 300 grams Force Applied to Top of Key in any Direction.
ENVIRONMENTAL SPECIFICATION
[Description ———<[[ SSCS remet —C*d
[Operating Temperature || —SdeCw+s0dg@SSOSCSCSCSCSCSCCCCC*'?
[Operating Humidity || 20% to 80% RH, non-condensing SSCS
[Operating Altitude || 0t03,000meters CSCC
i
5% to 95% RH, non-condensing
RELIABILITY REQUIREMENT
MTBF: 20,000 Hours MTTR: 0.5 Hour.
Switch Operating Life: Standard Key — Five (5) Million Cycles; Function Key — Three (3) Million Cycles.
30-G @ 21 mseconds, 1/2 sine, two (2) shocks in each of six (6) planes (directions).
C-6
PC40-III SERVICE MANUAL
KEYBOARD ARRANGEMENT
C-7
PC40-III SERVICE MANUAL
CIRCUIT DIAGRAM
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C8
PC40-IlI SERVICE MANUAL
APPENDIX D
OPTIONS SECTION
¢ VIDEO PARAMETERS
¢ 1403 MONITOR SPECS
© 1352 MOUSE SPECS
INFORMATION IN THIS SECTION IS FOR REFERENCE ONLY.
COMMODORE WILL NOT SUPPLY COMPONENT PARTS FOR
OEM ASSEMBLIES.
PC40-IlI SERVICE MANUAL
PC40-111 VIDEO MODES
VIDEO MODE NOTES
The Onboard Video Adapter is 100% IBM VGA compatible and can also be placed in CGA and MDA hardware compatible
video modes. The Hardware MDA mode also is 100% Hercules compatible and will run all Hercules software. The Hardware
CGA mode also includes Plantronics mode which can be exploited by any software which understands Plantronics special registers.
The PC40-III video output is always VGA compatible with a 31.5 KHz horizontal rate; vertical rate is either 60 or 70 Hz,
depending on the VGA mode.
Dip switches 1, 2 and 3 in the CONFIG Control (located at the rear of the PC40-III) are used to set the default video mode.
The switch settings are described clearly on the PC40-III’s back label. The choices are as follows:
DISABLE VIDEO — disables onboard video adapter
MDA/HERCULES — sets hardware compatible MDA/Hercules mode.
CGA — sets hardware compatible CGA/Plantronics mode.
VGA AUTO — detects whether attached monitor is MONO or COLOR:
If MONO is detected, VGA mode 7 is set.
If COLOR is detected, VGA mode 2 is set.
(See Video Mode Characteristics table in this appendix.)
VGA COLOR — sets VGA color mode 2 by default regardless of monitor.
VGA MONO — sets VGA mono mode 7 by default regardless of monitor.
132x43 — sets extended 132 column, 43 row text mode regardless of monitor.
132x25 — sets extended 132 column, 25 row text mode regardless of monitor
NOTE: EGA is a subset of VGA. EGA-based software will work when the system is configured as a VGA adapter.
USING THE VMODE UTILITY TO CHANGE VIDEO MODES
The VMODE utility provides a software method to change video modes. Just select the mode you want from the folllowing
table: then type the corresponding command and press Enter.
Video Mode Command
Hardware CGA Vmode —-c
Hardware MDA/HERC Vmode —m
VGA Color Vmode —ve
VGA Mono Vmode —vm
132x25 Text Vmode -tl
132x43 Text Vmode —t2
Help Vmode —h
Invoking VMODE with the Help key will display the information in the table above, so if you are not sure of a command
just type Vmode -h.
IMPORTANT: If you change the video mode setting by the hardware method, you must reboot the system before the changes
will take effect. Video mode changes made by the VMODE utility or the MS-DOS MODE command will take effect immediately.
VIDEO MODE CHARACTERISTICS
ALPHANUMERIC MODES
MODE # COL X ROW CHAR MATRIX RESOLUTION COLORS STANDARD
0, 1 40 X 25 8X8 320 X 200 16 CGA (1)
9X 16 360 X 400 16 OF 256K VGA (2)
2, 3 80 X 25 8X8 640 X 200 16 CGA (1)
9X 16 720 X 400 16 OF 256K VGA (2)
7 80 X 25 9X 14 720 X 350 MONOCHROME MDA
9X 16 720 X 400 MONOCHROME VGA (2)
54 132 X 43 7X9 924 X 387 COLOR ENHANCED
55 132 X 25 7X 16 924 X 400 COLOR ENHANCED
56 132 X 43 7X9 924 X 387 MONOCHROME ENHANCED
57 132 X 25 7X 16 924 X 400 MONOCHROME ENHANCED
D-1
PC40-III SERVICE MANUAL
GRAPHICS MODES:
4,5 320 X 200 4 CGA (1)
4 OF 256K VGA (1 & 2)
6 640 X 200 2 CGA
2 OF 256K VGA (1 & 2)
D 320 X 200 16 OF 256K VGA (1)
E 640 X 200 16 OF 256K VGA (1)
F 640 X 350 MONOCHROME VGA
10 640 X 350 16 OF 256K VGA
11 640 X 480 2 OF 256K VGA/MCGA
12 640 X 480 16 OF 256K VGA
13 320 X 200 256 OF 256K VGA/MCGA
NOTES:
(1) All 200 line modes are double scanned for 400 line resolution.
(2) The VGA implementation of these modes is the default.
VIDEO SIGNALS
Vertical Horizontal sync Vertical sync
Resolution Frequency Polarity Frequency Polarity
350 lines 31.5 KHz + 70.1 Hz -
400 lines 31.5 KHz - 70.1 Hz +
480 lines 31.5 KHz - 59.9 Hz -
600 lines* 35.2 KHz - 56.2 Hz -
*Requires an Analog MultiSync® compatible monitor.
HERCULES GRAPHICS MODE — PROGRAMMING NOTES
This mode is essentially a bitmapped version of the MDA. The video dot clock (16.257 Mhz) and the screen resolution (720x348
pixels) are identical. The memory requirement to hold one full display is just less than 32Kbytes: therefore, two display pages
are available.
Page: address b000:0000h to b000:7FFFh
Pagel: address b000:8000h to b000:FFFFh
NOTE: Page | occupies address space used by CGA video memory. DO NOT switch to this page if an EXPANSION CGA
adapter is installed. Hardware damage to the EXPANSION card or the motherboard may result!
The relevant registers are:
Hercules Enable Register - I/O addr 3bfh
bit0: 0 - disable setting graphics mode
1 - enable setting graphics mode
bitl: 0 - disable changing graphics pages
1 - enable changing graphics pages
Mode Register - I/O addr 3b8h
bitl: 0 - disable Hercules mode (default MDA)
1 - enable Hercules graphics
bit3: 0 - video disable
1 - video enable
bits: 0 - blink disable
1 - blink enable
bit7: 0 - Hercules Paged
1 - Hercules Pagel
PC40-Ill SERVICE MANUAL
Hercules 6845 CRTC parameters:
register #0 36h
#1 2dh
2fh
07h
5bh
00h
57h
53h
02h
03h
00h
00h
00h
00h
Locating specific pixels within the bitmap may be performed with the following equation:
byte offset = (8192* (Y mod 4)) + (90 * INT(Y mod 4)) + INT(X/8); bit position = 7 — (XK mod 8):
where: 0 < X < = 719
0< =Y < = 347
PLANTRONICS COLOR PLUS MODE(S) — PROGRAMMING NOTES
This mode is an enhancement to the graphics modes of the CGA. The dot clock is 14.318 Mhz in the 640x200 mode and 7.16
Mhz in the 320x200 mode. The 640x200 mode offers a choice of 4 out of 16 colors per pixel vs. black & white in the CGA
mode with the same resolution. The 320x200 mode offers 16 out of 16 colors vs. 4 out of 16 colors for the comparable CGA mode.
Plantronics 6845 CRTC parameters:
(actually the same as CGA 320x200 & 640x200)
register #0 38h
#1 28h
2dh
Oah
7fh
06h
64h
70h
02h
Olh
06h
07h
00h
00h
FSF SSIREESS
2FSFSSIRERSES
The 32Kbytes of display RAM are divided into two bit planes.
PlaneO — Even scan lines @ addr b000:8000h to b000:9f3fh Planel — Even scan lines @ addr b000:c000h to b000:df3fh
Odd scan lines @ addr b000:a000h to b000:bf3fh Odd scan lines @ addr b000:e000h to b000:ff3fh
320x200 16 color BIT ORGANIZATION 640x200 4 color BIT ORGANIZATION
| bplane# | bit? | bits | bits | died | bit3 | bit2 | ditt | dito |
| planed | co} c0_|
|_bplane# | bit7 | bits | bits | bits | bdit3 | bit2 | died | bito_|
|__planed ci | co | ct | cof ct [cof ct | 0 |
|_planet ft c3_ [cz | cs fo c2 [cs [cz | cs | 2 |
|__pixel# | pixel | pixel! | pixel2_ | pixel 3__|
| _pixel# | pixelO | pixelt | pixel2 | pixel3 | pixel4 | pixels | pixel6 | pixel |
D-3
PC40-III SERVICE MANUAL
c1/R
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green
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Autoconfig examines the expansion bus for any expansion Advanced Video Adapter BIOS in the 0C0000h — OC7FFFh memory
range. If an expansion video BIOS is found, then an external VGA or EGA controller is assumed to be on the bus and the
onboard VGA controller is disabled to avoid conflict. If an expansion video BIOS is not found, the video output is configured
in accordance with the default CONFIG Control video setting (see Appendices F and H), as defined by the CONFIG dip switches
1, 2 and 3.
You can add an expansion MDA or CGA compatible controller in conjunction with the onboard VGA controller to provide
two video screens. (This makes many CAD packages easier to use.)
NOTE: When using the PC40-III’s onboard video controller, 2a VGA compatible monitor such as Commodore Models 1403
and 1450 (monochrome) or 1950 (color) must be connected to the 15 pin video output connector (no matter what video mode
you have selected).
If you want to use two video screens, there are several things you should remember. First, you should use a CGA, MDA or
compatible adapter — one that has no BIOS ROM of any kind.
Also, if you were to use an MDA/Herc adapter (monochrome) and you have the CONFIG switches set for VGA color, the
PC40-III will boot using your VGA monitor and you will see a blinking cursor on your monochrome monitor, indicating that
it has been initialized.
If, while using the MDA/Herc adapter in the expansion port, you have the CONFIG switches on the back of the System Unit
set to MDA/Herc, your PC40-III will use the monochrome monitor as the boot monitor and the VGA monitor will be initialized
with the blinking cursor.
In either case, you can switch between the VGA and the monochrome monitors by using the MS-DOS MODE command.
The syntax for the MODE command is as follows:
COLOR
e MODE MONO = — ‘sets the MDA as the default monitor
¢ MODE co80 — places the onboard VGA adapter into 80 column mode and sets it as the default monitor
¢ MODE co40 — places the onboard VGA adapter into 40 column mode and sets it as the default monitor
D-4
' PC40-IIT SERVICE MANUAL
VIDEO DIP SWITCHES
Dip switches 1, 2 and 3 are set in combinations as shown below to enable the various video modes that the PC40-III supports.
DISABLE VIDEO CRY
MDA/HERC. UU
123
CGA U id
VGA AUTO. ditt WARNING: POWER OFF UNIT BEFORE
123 CHANGING DIP SWITCHES
TT
VGA COLOR ihhys.s,
VGA MONO. rt iti
123
132 COL. x 43ROW fT
132 COL.X 25ROW Ami
123
PIN DEFINITIONS FOR VIDEO PORT PIN DEFINITIONS FOR MULTISYNC ADAPTER CABLE
1§ 14°13 12 11 15 14 13:12 11
Pin Function NEC Multisync ss tO VGA
1. Red Video
2. Green Video DB9 Female DB 15 Male
3. Blue Video
4. Monitor ID Bit 2 (not used) 1 a 1
5. ground
E
6. Red Return (ground) 2 a ee 2
7. Green Return (ground)
8. Blue Return (ground) 3 srctng ORR: 3
>. Key (no pin) HORIZONTAL
10. Sync Return (ground) 4 aa 13
11. Monitor ID Bit 0 (not used) VERTICAL
12. Monitor ID Bit 1 (not used) 5 ee es 14
13. Horizontal Sync 6 6
14, Vertical Sync
15. not used 7 a
ROUND
Monitor ID Bits are not used in VGA. 8 bated 8
Monitor type is determined on power 9 10
up by an automatic sensing circuit. 11
NOTE: Many Multisync monitors come equipped with a
compatible adapter.
PC40-III SERVICE MANUAL
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PC40-IIT SERVICE MANUAL
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1403 MONOCHROME VGA
COMPATIBLE MONITOR
SERVICE MANUAL
AVAILABLE UNDER
CBM PART NUMBER 314882-01
1. Cathode Ray Tube (CRT)
Size : 14 inch diagonal (DM-3014)
15 inch diagonal (DM-3015)
Deflection Angle : 90 degrees
Neck Diameter :20¢
Face Treatment
Phosphor
2. Power Requirements
Power source
Power consumption
: dark glass, non-glare
: H192 or equivalent
: 110 / 220 volts AC, 0.55 Amp.
: 50 watts
3. Deflection Characteristics
Horizontal
Frequency
Blanking time
Vertical
Frequency
Vertical
Blanking time
a. 50 Hz
480 lines
400 lines
350 lines
b. 60 Hz
480 lines
400 lines
350 lines
c. 70 Hz
400 lines
350 lines
4. Video Response
Bandwidth
Rise time
Fall time
Characters
Horizontal resolution :
Vertical resolution
: 31.468 KHz
: 5.72 usec
: 50 / 60 / 70 Hz
: 4.236 msec
: 6.844 msec
: 8.496 msec
: 0.905 msec
: 3.511 msec
: 5.163 msec
: 1.130 msec
: 2.728 msec
: 30 MHz (—3dB)
: 15 nsec max.
: 15 nsec max.
: Up to 64 gray shades
640 / 720 pixels
: 350 / 400 / 480 lines
PC40-IlI SERVICE MANUAL
CONTRAST
5. Display Format
BRIGHTNESS
Character format : 8 x 14 matrix
Capacity
6. Input Signal
Video signal
Horizontal drive
Vertical drive
8 x 16
9x 16
: 80 characters x 25 rows
80 characters x 30 rows
:0 -— 0.7 Vpp
: 3.5 Vpp
: 3.5 Vpp
7. Display Performance
Picture
Horizontal
Vertical
Linearity
DM-3014 DM-3015
:240mm + 3mm 250mm + 3mm
:180mm + 3mm 190mm + 3mm
: Character height or width will not
vary for more than 10% from the
average character size.
8. Geometric Distortion
DM-3014
Horizontal
Vertical
DM-3015
Horizontal
Vertical
: +2mm
: +2mm
: +3mm
: +3mm
9. Video Cable Input Signal
Pin 2 - Video
Pin 5 - Self test
Pin 7 - Ground
Pin 10 - Ground
Pin 13 - H-sync
Pin 14 - V-sync
D-9
PC40-IIT SERVICE MANUAL
le 20
BALL COVER AND REMOVAL METHOD 2.77
WILL VARY ACCORDING TO VENDOR = i pecans
CONNECTION TABLE
| PIN NO. | _ FUNCTION
BUTTON #2 (RIGHT)
ID LABEL LOCATION
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D-10
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PC40-IIT SERVICE MANUAL
FOR REFERENCE ONLY
1352 MOUSE
PC40-III SERVICE MANUAL
APPENDIX E
TECHNICAL UPDATES
C= commodore
COMPUTERS
Computer Systems Division
1200 Wilson Drive
West Chester, PA 19380
Live Music Archive
Librivox Free Audio
Metropolitan Museum
Cleveland Museum of Art
Internet Arcade
Console Living Room
Books to Borrow
Open Library
TV News
Understanding 9/11